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redid the init again "a bit"
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@ADM228
ADM228 committed Jun 24, 2024
1 parent 00b82b5 commit bae2661
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Showing 2 changed files with 205 additions and 137 deletions.
4 changes: 1 addition & 3 deletions source/gui/SNESFMDemo.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -173,9 +173,7 @@ Start:
%InitSNES()
lda #$80 ; Turn off screen, no brightness
sta INIDISP ;__
SPCTransfer: ; Kept in SlowROM for compatibility/laziness
% ResetDP_PEA()

SPCTransfer:
.LoopConfirm:
LDA APUIO0
CMP #$AA
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338 changes: 204 additions & 134 deletions source/gui/initSNES.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -32,135 +32,13 @@ _InitSNES:
STA $4372 ;so save the return address in a place that won't get overwritten
PLX ;(that place is DMA registers)
STX $4374
LDA #$2100 ;set Direct Page = $2100 for easier writes to VRAM registers
TCD ;Transfer Accumulator to Direct Register
dpbase $2100 ; tell Asar to optimize the following everything

SEP #$30 ; mem/A = 8 bit, idx/XY = 8 bit

LDA #$8F
STA INIDISP ;turn screen off for now, set brightness to normal

LDX #$01
.Loop00: ;regs $2101-$210C
STZ INIDISP,X ;set Sprite,Character,Tile sizes to lowest, and set addresses to $0000
INX
CPX #$0D
BNE .Loop00

.Loop01: ;regs $210D-$2114
STZ INIDISP,X ;Set all BG scroll values to $0000
STZ INIDISP,X
INX
CPX #$15
BNE .Loop01

LDA #$80 ;reg $2115
STA VMAIN ; Initialize VRAM transfer mode to word-access, increment by 1

STZ VMADDL ;regs $2116-$2117
STZ VMADDH ;VRAM address = $0000

;reg $2118-$2119
;VRAM write register... don't need to initialize

STZ M7A ;clear Mode7 setting

LDX #$1B
.Loop02: ;regs $211B-$2120
STZ INIDISP,X ;clear out the Mode7 matrix values
STZ INIDISP,X
INX
CPX #$21
BNE .Loop02

;reg $2121 - Color address, doesn't need initilaizing
;reg $2122 - Color data, is initialized later

LDX #$23
.Loop03: ;regs $2123-$2133
STZ INIDISP,X ;turn off windows, main screens, sub screens, color addition,
INX ;fixed color = $00, no super-impose (external synchronization),
CPX #$34 ;no interlaced mode, normal resolution
BNE .Loop03

;regs $2134-$2136 - multiplication result, no initialization needed
;reg $2137 - software H/V latch, no initialization needed
;reg $2138 - Sprite data read, no initialization needed
;regs $2139-$213A - VRAM data read, no initialization needed
;reg $213B - Color RAM data read, no initialization needed
;regs $213C-$213D - H/V latched data read, no initialization needed

STZ STAT77 ;reg $213E - might not be necesary, but selects PPU master/slave mode
;reg $213F - PPU status flag, no initialization needed

;reg $2140-$2143 - APU communication regs, no initialization required

;reg $2180 - read/write WRAM register, no initialization required
;reg $2181-$2183 - WRAM address, no initialization required

;reg $4016-$4017 - serial JoyPad read registers, no need to initialize


STZ $4200 ;reg $4200 - disable timers, NMI, and auto-joyread

LDA #$FF
STA $4201 ;reg $4201 - programmable I/O write port, initalize to allow reading at in-port

;regs $4202-$4203 - multiplication registers, no initialization required
;regs $4204-$4206 - division registers, no initialization required

;regs $4207-$4208 - Horizontal-IRQ timer setting, since we disabled this, it is OK to not init
;regs $4209-$420A - Vertical-IRQ timer setting, since we disabled this, it is OK to not init

STZ $420B ;reg $420B - turn off all general DMA channels
STZ $420C ;reg $420C - turn off all H-MA channels

if !INIT_USE_FASTROM
STA $420D ;reg $420D - ROM access time to fast (3.78Mhz)
else
STZ $420D ;reg $420D - ROM access time to slow (2.68Mhz)
endif

LDA $4210 ;reg $4210 - NMI status, reading resets

;reg $4211 - IRQ status, no need to initialize
;reg $4212 - H/V blank and JoyRead status, no need to initialize
;reg $4213 - programmable I/O inport, no need to initialize

;reg $4214-$4215 - divide results, no need to initialize
;reg $4216-$4217 - multiplication or remainder results, no need to initialize

;regs $4218-$421f - JoyPad read registers, no need to initialize

;regs $4300-$437F
;no need to intialize because DMA was disabled above
;also, we're not sure what all of the registers do, so it is better to leave them at
;their reset state value

JSR ClearVRAM ;Reset VRAM
JSR ClearPalette ;Reset colors

;**** clear Sprite tables ********

STZ $2102 ;sprites initialized to be off the screen, palette 0, character 0
STZ $2103
LDX #$80
LDA #$F0
.Loop08:
STA $2104 ;set X = 240
STA $2104 ;set Y = 240
STZ $2104 ;set character = $00
STZ $2104 ;set priority=0, no flips
DEX
BNE .Loop08

LDX #$20
.Loop09:
STZ $2104 ;set size bit=0, x MSB = 0
DEX
BNE .Loop09
JSR SetRegisters
JSR ClearVRAM
JSR ClearPalette
JSR ClearOAM

.ClearWRAM:
;**** clear WRAM ********
Expand All @@ -172,22 +50,21 @@ _InitSNES:

REP #$10 ; idx/XY = 16 bit

STZ $2181 ;set WRAM address to $000000
STZ $2182
STZ $2183
STX WMADDL ; (X is 0 after the loop)
STZ WMADDH ;set WRAM address to $000000

; it is not worth it to set the DP to $4300

LDX #$8008
STX $4300 ;Set DMA mode to fixed source, BYTE to $2180
LDX #!WRAM_FILL_BYTE
STX $4302 ;Set source offset
LDA #$00 ;DMA doesn't care about FastROM
LDA.b #bank(!WRAM_FILL_BYTE)
STA $4304 ;Set source bank
#..WRAMFillInstr: LDX #$0000
PHX ; Push to return to DP $0000 later on
STX $4305 ;Set transfer size to 64k bytes
LDA #$01
LDA.b #$01
STA $420B ;Initiate transfer
STA $420B ;Initiate second transfer for 64k more bytes

Expand All @@ -212,7 +89,7 @@ _InitSNES:
; ClearVRAM -- Sets every byte of VRAM to zero
; In: None
; Out: None
; Modifies: flags
; Modifies: Nothing
;----------------------------------------------------------------------------
ClearVRAM:
pha
Expand Down Expand Up @@ -248,7 +125,7 @@ ClearVRAM:
; ClearPalette -- Reset all palette colors to zero
; In: None
; Out: None
; Modifies: flags
; Modifies: Nothing
;----------------------------------------------------------------------------
ClearPalette:
PHX
Expand All @@ -275,6 +152,199 @@ ClearPalette:
PLX
RTS


;----------------------------------------------------------------------------
; ClearPalette -- Reset all palette colors to zero
; In: None
; Out: None
; Modifies: Nothing
;----------------------------------------------------------------------------
ClearOAM:
PHA
PHX
PHP
PHD
SEP #$20 ; mem/A = 8 bit
REP #$10 ; idx/XY = 16 bit

PEA $2100 ; set DP to $2100
PLD ; for faster access
dpbase $2100 ; tell Asar that

STZ OAMADDL ;sprites initialized to be off the screen, palette 0, character 0
STZ OAMADDH
LDX.w #$80
LDA #$01
.Loop08:
STA OAMDATA ;set X = 1 (-255 really because of the next loop)
STZ OAMDATA ;set Y = 0
STZ OAMDATA ;set character = $00
STZ OAMDATA ;set priority=0, no flips
DEX
BNE .Loop08

LDX.w #$20
LDA #%01010101
.Loop09:
STA OAMDATA ;set size bit=0, x MSB = 1
DEX
BNE .Loop09

PLD
PLP
PLX
PLA
RTS

;----------------------------------------------------------------------------
; SetRegisters -- set PPU and CPU registers to a known state (as per snesdev)
; In: None
; Out: None
; Modifies: Nothing
;----------------------------------------------------------------------------
SetRegisters:
PHD
PHA
PHX
PHY
PHP

PEA $2100 ;set Direct Page = $2100 for easier writes to VRAM registers
PLD ;Transfer Accumulator to Direct Register
dpbase $2100 ; tell Asar to optimize the following everything

SEP #$30 ; mem/A = 8 bit, idx/XY = 8 bit

STZ NMITIMEN ;reg $4200 - disable timers, NMI, and auto-joyread
STZ HDMAEN ;reg $420C - turn off all HDMA channels

LDA #$8F
STA INIDISP ;turn screen off for now, set brightness to normal

LDX #(BG34NBA-OBSEL)
.Loop00: ;regs $2101-$210C
STZ OBSEL,X ;set Sprite,Character,Tile sizes to lowest, and set addresses to $0000
DEX
BPL .Loop00

LDA #$FF
LDX #(BG4VOFS-BG1HOFS)
.ScrollClearLoop: ;regs $210D-$2114
STA BG1VOFS,X ;Set all vertical BG scroll values to $FFFF (-1)
STA BG1VOFS,X

STZ BG1HOFS,X ;Set all horizontal BG scroll values to $0000
STZ BG1HOFS,X
DEX
DEX
BPL .ScrollClearLoop

LDA #$80 ;reg $2115
STA VMAIN ; Initialize VRAM transfer mode to word-access, increment by 1

STZ VMADDL ;regs $2116-$2117
STZ VMADDH ;VRAM address = $0000

;reg $2118-$2119
;VRAM write register... don't need to initialize

LDA #$01
STZ M7A ;clear Mode7 setting
STA M7A

STZ M7D
STA M7D

LDX #1
.Mode7BCXYLoop: ;regs $211B-$2120
STZ M7B,X ;clear out the Mode7 matrix values
STZ M7B,X
STZ M7X,X
STZ M7X,X
DEX
BPL .Mode7BCXYLoop

;reg $2121 - Color address, doesn't need initilaizing
;reg $2122 - Color data, is initialized later

LDX #(TSW-W12SEL)
.WindowEnableLoop: ;regs $2123-$2133
STZ W12SEL,X ;turn off windows, main screens, sub screens
DEX
BPL .WindowEnableLoop

LDA #%00110000 ;deactivate windows, no direct color mode, use fixed color as base
STA CGWSEL

STZ CGADSUB ;color math on nothing, add, no halving

LDA #%11100000 ;Fixed color: write color 0 to bgr
STA COLDATA

STZ SETINI ;no super-impose (external synchronization),
;no interlaced mode, normal resolution

;regs $2134-$2136 - multiplication result, no initialization needed
;reg $2137 - software H/V latch, no initialization needed
;reg $2138 - Sprite data read, no initialization needed
;regs $2139-$213A - VRAM data read, no initialization needed
;reg $213B - Color RAM data read, no initialization needed
;regs $213C-$213D - H/V latched data read, no initialization needed

;reg $213E - PPU1 status flags, no initialization needed
;reg $213F - PPU2 status flags, no initialization needed

;reg $2140-$2143 - APU communication regs, no initialization required

;reg $2180 - read/write WRAM register, no initialization required
;reg $2181-$2183 - WRAM address, no initialization required

;reg $4016-$4017 - serial JoyPad read registers, no need to initialize


LDA #$FF
STA WRIO ;reg $4201 - programmable I/O write port, initalize to allow reading at in-port

;regs $4202-$4203 - multiplication registers, no initialization required
;regs $4204-$4206 - division registers, no initialization required

;regs $4207-$4208 - Horizontal-IRQ timer setting, since we disabled this, it is OK to not init
;regs $4209-$420A - Vertical-IRQ timer setting, since we disabled this, it is OK to not init

STZ MDMAEN ;reg $420B - turn off all general DMA channels

if !INIT_USE_FASTROM
STA MEMSEL ;reg $420D - ROM access time to fast (3.78Mhz)
else
STZ MEMSEL ;reg $420D - ROM access time to slow (2.68Mhz)
endif

LDA RDNMI ;reg $4210 - NMI status, reading resets

;reg $4211 - IRQ status, no need to initialize
;reg $4212 - H/V blank and JoyRead status, no need to initialize
;reg $4213 - programmable I/O inport, no need to initialize

;reg $4214-$4215 - divide results, no need to initialize
;reg $4216-$4217 - multiplication or remainder results, no need to initialize

;regs $4218-$421f - JoyPad read registers, no need to initialize

;regs $4300-$437F
;no need to intialize because DMA was disabled above
;also, we're not sure what all of the registers do, so it is better to leave them at
;their reset state value
PLP
PLY
PLX
PLA
PLD
dpbase $0000
RTS



;----------------------------------------------------------------------------
; InitSNES -- the "standard" initialization of SNES memory and registers
;----------------------------------------------------------------------------
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