Verilator build warnings

[kallisti5]

kallisti5@eris verilog-6502 :( $ verilator -sv -cc -Wno-fatal cpu.v 
%Warning-WIDTH: ALU.v:57: Operator OR expects 9 bits on the LHS, but LHS's VARREF 'AI' generates 8 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: ALU.v:57: Operator OR expects 9 bits on the RHS, but RHS's VARREF 'BI' generates 8 bits.
%Warning-WIDTH: ALU.v:58: Operator AND expects 9 bits on the LHS, but LHS's VARREF 'AI' generates 8 bits.
%Warning-WIDTH: ALU.v:58: Operator AND expects 9 bits on the RHS, but RHS's VARREF 'BI' generates 8 bits.
%Warning-WIDTH: ALU.v:59: Operator XOR expects 9 bits on the LHS, but LHS's VARREF 'AI' generates 8 bits.
%Warning-WIDTH: ALU.v:59: Operator XOR expects 9 bits on the RHS, but RHS's VARREF 'BI' generates 8 bits.
%Warning-WIDTH: ALU.v:60: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS's VARREF 'AI' generates 8 bits.
%Warning-WIDTH: ALU.v:73: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'temp_logic' generates 9 bits.
%Warning-WIDTH: ALU.v:90: Operator ADD expects 5 bits on the RHS, but RHS's VARREF 'adder_CI' generates 1 bits.
%Warning-WIDTH: ALU.v:91: Operator ADD expects 5 bits on the RHS, but RHS's VARREF 'temp_HC' generates 1 bits.
%Warning-WIDTH: cpu.v:351: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'PC_inc' generates 1 bits.
%Warning-WIDTH: cpu.v:598: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '1'bx' generates 1 bits.
%Warning-CASEX: cpu.v:502: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:516: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:872: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEINCOMPLETE: cpu.v:872: Case values incompletely covered (example pattern 0x2)
%Warning-CASEINCOMPLETE: cpu.v:870: Case values incompletely covered (example pattern 0x32)
%Warning-CASEX: cpu.v:979: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEOVERLAP: cpu.v:988: Case values overlap (example pattern 0x88)
%Warning-CASEX: cpu.v:996: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1016: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEOVERLAP: cpu.v:1023: Case values overlap (example pattern 0x8e)
%Warning-CASEX: cpu.v:1037: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1049: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1060: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1071: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1079: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1089: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1098: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1107: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1117: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1128: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1137: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1147: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1173: Suggest casez (with ?'s) in place of casex (with X's)

[adumont]

@kallisti5 I fixed Verilator'd issues in

adumont/ad6502@3c92dd8

I should open a PR for that...