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1 parent 35406df commit ddb0d1bCopy full SHA for ddb0d1b
simphony/tests/test_simulation.py
@@ -184,7 +184,7 @@ def test_context(self, mzi):
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assert l1.circuit == gc_input.circuit == sim1.circuit
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assert d1.circuit == gc_output.circuit == sim1.circuit
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- with Simulation() as sim2:
+ with Simulation() as _:
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assert sim1.circuit is None
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assert l1.circuit != gc_input.circuit
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assert d1.circuit != gc_output.circuit
@@ -196,7 +196,7 @@ def test_sampling(self, mzi):
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Laser().connect(gc_input)
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Detector().connect(gc_output)
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- with pytest.raises(Exception) as e:
+ with pytest.raises(Exception) as _:
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# sample only takes odd numbers
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sim1.sample(100)
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