Skip to content

Commit

Permalink
Implement the hazard module (#107)
Browse files Browse the repository at this point in the history
* Adds the structure for the hazard module

* Implements the hazard module

* Starts integrating the hazard module

* Fixes delay in hazard module

* Finishes the hazard module

* Finishes implementing the hazard module and integrating it
  • Loading branch information
cchaine authored Apr 27, 2024
1 parent cc80935 commit fde58f0
Show file tree
Hide file tree
Showing 19 changed files with 1,397 additions and 82 deletions.
95 changes: 81 additions & 14 deletions config/gtkwave/config/ecap5_dproc.gtkw
Original file line number Diff line number Diff line change
@@ -1,15 +1,15 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Thu Apr 25 15:50:13 2024
[*] Sat Apr 27 07:13:35 2024
[*]
[dumpfile] "/Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/proc/build/tests/waves/ecap5_dproc.vcd"
[dumpfile_mtime] "Thu Apr 25 15:39:04 2024"
[dumpfile_size] 62521
[dumpfile_mtime] "Sat Apr 27 07:12:25 2024"
[dumpfile_size] 74071
[savefile] "/Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/proc/config/gtkwave/config/ecap5_dproc.gtkw"
[timestart] 70
[size] 2320 783
[timestart] 242
[size] 2320 982
[pos] -1 -1
*-5.572440 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*-5.572440 153 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[markername] AA
[markername] BB
[markername] CC
Expand Down Expand Up @@ -42,7 +42,7 @@
[sst_width] 253
[signals_width] 351
[sst_expanded] 1
[sst_vpaned_height] 450
[sst_vpaned_height] 377
@2024
[color] 1
^1 /Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/proc/config/gtkwave/filters/ecap5_dproc_testcase_filter.gtkw
Expand All @@ -55,42 +55,63 @@ TOP.tb_ecap5_dproc.dut.irq_i
@c00200
-Master Wishbone
@22
[color] 2
TOP.tb_ecap5_dproc.dut.wb_adr_o[31:0]
[color] 2
TOP.tb_ecap5_dproc.dut.wb_dat_i[31:0]
[color] 2
TOP.tb_ecap5_dproc.dut.wb_dat_o[31:0]
@28
[color] 2
TOP.tb_ecap5_dproc.dut.wb_we_o
@22
[color] 2
TOP.tb_ecap5_dproc.dut.wb_sel_o[3:0]
@28
[color] 2
TOP.tb_ecap5_dproc.dut.wb_stb_o
[color] 2
TOP.tb_ecap5_dproc.dut.wb_ack_i
[color] 2
TOP.tb_ecap5_dproc.dut.wb_cyc_o
[color] 2
TOP.tb_ecap5_dproc.dut.wb_stall_i
@1401200
-Master Wishbone
@c00200
-IFM
@28
[color] 5
TOP.tb_ecap5_dproc.dut.branch
@22
[color] 5
TOP.tb_ecap5_dproc.dut.branch_target[31:0]
@c00200
@800200
-IFM Wishbone
@22
[color] 5
TOP.tb_ecap5_dproc.dut.if_wb_adr_o[31:0]
[color] 5
TOP.tb_ecap5_dproc.dut.if_wb_dat_i[31:0]
[color] 5
TOP.tb_ecap5_dproc.dut.if_wb_sel_o[3:0]
@28
[color] 5
TOP.tb_ecap5_dproc.dut.if_wb_we_o
[color] 5
TOP.tb_ecap5_dproc.dut.if_wb_stb_o
[color] 5
TOP.tb_ecap5_dproc.dut.if_wb_ack_i
[color] 5
TOP.tb_ecap5_dproc.dut.if_wb_cyc_o
[color] 5
TOP.tb_ecap5_dproc.dut.if_wb_stall_i
@1401200
@1000200
-IFM Wishbone
@22
[color] 5
TOP.tb_ecap5_dproc.dut.if_instr[31:0]
[color] 5
TOP.tb_ecap5_dproc.dut.if_pc[31:0]
@1401200
-IFM
Expand All @@ -100,27 +121,43 @@ TOP.tb_ecap5_dproc.dut.if_dec_valid
@c00200
-DECM
@22
[color] 3
TOP.tb_ecap5_dproc.dut.dec_pc[31:0]
[color] 3
TOP.tb_ecap5_dproc.dut.dec_alu_operand1[31:0]
[color] 3
TOP.tb_ecap5_dproc.dut.dec_alu_operand2[31:0]
@28
[color] 3
TOP.tb_ecap5_dproc.dut.dec_alu_op[2:0]
[color] 3
TOP.tb_ecap5_dproc.dut.dec_alu_sub
[color] 3
TOP.tb_ecap5_dproc.dut.dec_alu_shift_left
[color] 3
TOP.tb_ecap5_dproc.dut.dec_alu_signed_shift
[color] 3
TOP.tb_ecap5_dproc.dut.dec_branch_cond[2:0]
@22
[color] 3
TOP.tb_ecap5_dproc.dut.dec_branch_offset[19:0]
@28
[color] 3
TOP.tb_ecap5_dproc.dut.dec_ls_enable
[color] 3
TOP.tb_ecap5_dproc.dut.dec_ls_write
@22
[color] 3
TOP.tb_ecap5_dproc.dut.dec_ls_write_data[31:0]
[color] 3
TOP.tb_ecap5_dproc.dut.dec_ls_sel[3:0]
@28
[color] 3
TOP.tb_ecap5_dproc.dut.dec_ls_unsigned_load
[color] 3
TOP.tb_ecap5_dproc.dut.dec_reg_write
@22
[color] 3
TOP.tb_ecap5_dproc.dut.dec_reg_addr[4:0]
@1401200
-DECM
Expand All @@ -130,19 +167,27 @@ TOP.tb_ecap5_dproc.dut.dec_ex_valid
@c00200
-EXM
@22
[color] 7
TOP.tb_ecap5_dproc.dut.ex_result[31:0]
@28
[color] 7
TOP.tb_ecap5_dproc.dut.ex_ls_enable
@22
[color] 7
TOP.tb_ecap5_dproc.dut.ex_ls_sel[3:0]
@28
[color] 7
TOP.tb_ecap5_dproc.dut.ex_ls_unsigned_load
[color] 7
TOP.tb_ecap5_dproc.dut.ex_ls_write
@22
[color] 7
TOP.tb_ecap5_dproc.dut.ex_ls_write_data[31:0]
@28
[color] 7
TOP.tb_ecap5_dproc.dut.ex_reg_write
@22
[color] 7
TOP.tb_ecap5_dproc.dut.ex_reg_addr[4:0]
@1401200
-EXM
Expand All @@ -153,42 +198,64 @@ TOP.tb_ecap5_dproc.dut.ex_ls_ready
-LSM
-LSM Wishbone
@22
[color] 6
TOP.tb_ecap5_dproc.dut.ls_wb_adr_o[31:0]
[color] 6
TOP.tb_ecap5_dproc.dut.ls_wb_dat_i[31:0]
[color] 6
TOP.tb_ecap5_dproc.dut.ls_wb_dat_o[31:0]
@28
[color] 6
TOP.tb_ecap5_dproc.dut.ls_wb_we_o
@22
[color] 6
TOP.tb_ecap5_dproc.dut.ls_wb_sel_o[3:0]
@28
[color] 6
TOP.tb_ecap5_dproc.dut.ls_wb_stb_o
[color] 6
TOP.tb_ecap5_dproc.dut.ls_wb_ack_i
[color] 6
TOP.tb_ecap5_dproc.dut.ls_wb_cyc_o
[color] 6
TOP.tb_ecap5_dproc.dut.ls_wb_stall_i
@1401200
-LSM Wishbone
@28
[color] 6
TOP.tb_ecap5_dproc.dut.ls_reg_write
@22
[color] 6
TOP.tb_ecap5_dproc.dut.ls_reg_addr[4:0]
[color] 6
TOP.tb_ecap5_dproc.dut.ls_reg_data[31:0]
@1401200
-LSM
@28
TOP.tb_ecap5_dproc.dut.ls_valid
@c00201
@c00200
-REGM
@23
@22
[color] 1
TOP.tb_ecap5_dproc.dut.reg_raddr1[4:0]
[color] 1
TOP.tb_ecap5_dproc.dut.reg_rdata1[31:0]
[color] 1
TOP.tb_ecap5_dproc.dut.reg_raddr2[4:0]
[color] 1
TOP.tb_ecap5_dproc.dut.reg_rdata2[31:0]
@29
@28
[color] 1
TOP.tb_ecap5_dproc.dut.reg_write
@23
@22
[color] 1
TOP.tb_ecap5_dproc.dut.reg_waddr[4:0]
[color] 1
TOP.tb_ecap5_dproc.dut.reg_wdata[31:0]
@1401201
@1401200
-REGM
@28
TOP.tb_ecap5_dproc.dut.hzd_dec_stall_request
TOP.tb_ecap5_dproc.dut.hzd_ex_discard_request
[pattern_trace] 1
[pattern_trace] 0
93 changes: 93 additions & 0 deletions config/gtkwave/config/hazard.gtkw
Original file line number Diff line number Diff line change
@@ -0,0 +1,93 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Sat Apr 27 11:30:28 2024
[*]
[dumpfile] "/Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/proc/build/tests/waves/hazard.vcd"
[dumpfile_mtime] "Sat Apr 27 11:30:16 2024"
[dumpfile_size] 6372
[savefile] "/Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/proc/config/gtkwave/config/hazard.gtkw"
[timestart] 177
[size] 1288 600
[pos] -1 -1
*-5.093879 235 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[markername] AA
[markername] BB
[markername] CC
[markername] DD
[markername] EE
[markername] FF
[markername] GG
[markername] HH
[markername] II
[markername] JJ
[markername] KK
[markername] LL
[markername] MM
[markername] NN
[markername] OO
[markername] PP
[markername] QQ
[markername] RR
[markername] SS
[markername] TT
[markername] UU
[markername] VV
[markername] WW
[markername] XX
[markername] YY
[markername] ZZ
[treeopen] TOP.
[treeopen] TOP.tb_hazard.
[sst_width] 253
[signals_width] 264
[sst_expanded] 1
[sst_vpaned_height] 159
@2024
[color] 1
^1 /Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/proc/config/gtkwave/filters/hazard_testcase_filter.gtkw
TOP.tb_hazard.testcase[31:0]
@28
TOP.tb_hazard.clk_i
TOP.tb_hazard.rst_i
@800200
-Control
@28
TOP.tb_hazard.branch_i
TOP.tb_hazard.ex_discard_request_o
@1000200
-Control
@800200
-Data
@22
TOP.tb_hazard.reg_raddr1_i[4:0]
TOP.tb_hazard.reg_raddr2_i[4:0]
@28
[color] 2
TOP.tb_hazard.dec_reg_write_i
@22
[color] 2
TOP.tb_hazard.dec_reg_addr_i[4:0]
@28
[color] 2
TOP.tb_hazard.ex_reg_write_i
@22
[color] 2
TOP.tb_hazard.ex_reg_addr_i[4:0]
@28
[color] 2
TOP.tb_hazard.ls_reg_write_i
@22
[color] 2
TOP.tb_hazard.ls_reg_addr_i[4:0]
@28
[color] 2
TOP.tb_hazard.reg_write_i
@22
[color] 2
TOP.tb_hazard.reg_waddr_i[4:0]
@28
TOP.tb_hazard.dec_stall_request_o
@1000200
-Data
[pattern_trace] 1
[pattern_trace] 0
Loading

0 comments on commit fde58f0

Please sign in to comment.