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Adds missing tests #134

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May 16, 2024
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Adds missing tests #134

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2 changes: 1 addition & 1 deletion CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@
cmake_minimum_required(VERSION 3.12)
include(FetchContent)

project(ECAP5_DPROC VERSION 1.0)
project(ECAP5_DPROC VERSION 1.0.0)

set(CMAKE_MODULE_PATH "${CMAKE_CURRENT_LIST_DIR}/cmake")
set(CMAKE_PREFIX_PATH "${CMAKE_CURRENT_LIST_DIR}/cmake")
Expand Down
39 changes: 20 additions & 19 deletions config/traceability-matrix.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -240,8 +240,6 @@ tb_ecap5_dproc.data_hazard.01
tb_ecap5_dproc.data_hazard.02
tb_ecap5_dproc.data_hazard.03
tb_ecap5_dproc.data_hazard.04
tb_ecap5_dproc.reset.01;I_RESET_01
tb_ecap5_dproc.irq.01;I_IRQ_01
tb_execute.alu.ADD_01;A_FUNCTIONAL_PARTITIONING_05
tb_execute.alu.ADD_02;A_FUNCTIONAL_PARTITIONING_05
tb_execute.alu.ADD_03;A_FUNCTIONAL_PARTITIONING_05
Expand Down Expand Up @@ -315,6 +313,8 @@ tb_execute.hazard.01;A_FUNCTIONAL_PARTITIONING_05;A_PIPELINE_DROP_01
tb_execute.hazard.02;A_FUNCTIONAL_PARTITIONING_05;A_PIPELINE_DROP_01
tb_execute.hazard.03;A_FUNCTIONAL_PARTITIONING_05;A_PIPELINE_DROP_01
tb_fetch.reset.01;I_RESET_01
tb_fetch.reset.02;I_RESET_01
tb_fetch.reset.03;I_RESET_01
tb_fetch.no_stall.01;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.no_stall.02;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03;F_REGISTER_RESET_01
tb_fetch.no_stall.03;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
Expand All @@ -329,30 +329,31 @@ tb_fetch.pipeline_wait.01;A_FUNCTIONAL_PARTITIONING_02;A_PIPELINE_WAIT_01;F_REGI
tb_fetch.pipeline_wait.02;A_FUNCTIONAL_PARTITIONING_02;A_PIPELINE_WAIT_01;F_REGISTER_03
tb_fetch.pipeline_wait.03;A_FUNCTIONAL_PARTITIONING_02;A_PIPELINE_WAIT_01;F_REGISTER_03
tb_fetch.pipeline_wait.04;A_FUNCTIONAL_PARTITIONING_02;A_PIPELINE_WAIT_01;A_PIPELINE_STALL_01;F_REGISTER_03
tb_fetch.jump_after_reset.01;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_after_reset.02;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_during_ack.01;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_during_ack.02;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_during_wait.01;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_during_wait.02;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_during_memory_stall.01;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_during_memory_stall.02;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_on_output_handshake.01;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_on_output_handshake.02;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_during_pipeline_wait.01;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_during_pipeline_wait.02;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_back_to_back.01;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_back_to_back.02;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.precedence_interrupt.01;A_FUNCTIONAL_PARTITIONING_02;I_IRQ_01;F_REGISTER_03
tb_fetch.jump_after_reset.01;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_after_reset.02;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_during_ack.01;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_during_ack.02;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_during_wait.01;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_during_wait.02;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_during_memory_stall.01;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_during_memory_stall.02;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_on_output_handshake.01;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_on_output_handshake.02;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_during_pipeline_wait.01;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_during_pipeline_wait.02;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_back_to_back.01;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.jump_back_to_back.02;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.precedence_branch.01;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_fetch.precedence_increment.01;A_FUNCTIONAL_PARTITIONING_02;F_REGISTER_03
tb_hazard.reset.01;I_RESET_01
tb_hazard.reset.02;I_RESET_01
tb_hazard.control.01;A_FUNCTIONAL_PARTITIONING_08;A_HAZARD_02
tb_hazard.data.X0_01;A_FUNCTIONAL_PARTITIONING_08;A_HAZARD_01
tb_hazard.data.PORT1_01;A_FUNCTIONAL_PARTITIONING_08;A_HAZARD_01
tb_hazard.data.PORT2_01;A_FUNCTIONAL_PARTITIONING_08;A_HAZARD_01
tb_hazard.data.MULTIPLE_01;A_FUNCTIONAL_PARTITIONING_08;A_HAZARD_01
tb_loadstore.reset.01;I_RESET_01
tb_loadstore.reset.02;I_RESET_01
tb_loadstore.no_stall.LB_01;A_FUNCTIONAL_PARTITIONING_06
tb_loadstore.no_stall.LB_02;A_FUNCTIONAL_PARTITIONING_06
tb_loadstore.no_stall.LB_03;A_FUNCTIONAL_PARTITIONING_06
Expand Down Expand Up @@ -416,6 +417,8 @@ tb_loadstore_w_slave.no_stall.SW_02;A_FUNCTIONAL_PARTITIONING_06
tb_loadstore_w_slave.no_stall.SW_03;A_FUNCTIONAL_PARTITIONING_06
tb_loadstore_w_slave.no_stall.SW_04;A_FUNCTIONAL_PARTITIONING_06
tb_memory.reset.01;I_RESET_01;F_WISHBONE_RESET_01;F_WISHBONE_RESET_02;F_WISHBONE_RESET_03
tb_memory.reset.02;I_RESET_01;F_WISHBONE_RESET_01;F_WISHBONE_RESET_02;F_WISHBONE_RESET_03
tb_memory.reset.03;I_RESET_01;F_WISHBONE_RESET_01;F_WISHBONE_RESET_02;F_WISHBONE_RESET_03
tb_memory.port1_read.01;A_FUNCTIONAL_PARTITIONING_01
tb_memory.port1_read.02;A_FUNCTIONAL_PARTITIONING_01
tb_memory.port1_read.03;A_FUNCTIONAL_PARTITIONING_01
Expand Down Expand Up @@ -460,15 +463,13 @@ tb_memory.back_to_back.02;A_FUNCTIONAL_PARTITIONING_01
tb_memory.back_to_back.03;A_FUNCTIONAL_PARTITIONING_01
tb_memory.back_to_back.04;A_FUNCTIONAL_PARTITIONING_01
tb_memory.back_to_back.05;A_FUNCTIONAL_PARTITIONING_01
tb_registers.reset.01;I_RESET_01;F_REGISTER_01
tb_registers.read_x0.01;A_FUNCTIONAL_PARTITIONING_04;F_REGISTER_01;F_REGISTER_02
tb_registers.read_port_a.01;A_FUNCTIONAL_PARTITIONING_04;F_REGISTER_01
tb_registers.read_port_b.01;A_FUNCTIONAL_PARTITIONING_04;F_REGISTER_01
tb_registers.write_x0.01;A_FUNCTIONAL_PARTITIONING_04;F_REGISTER_01;F_REGISTER_02
tb_registers.write.01;A_FUNCTIONAL_PARTITIONING_04;F_REGISTER_01
tb_registers.parallel_read.01;A_FUNCTIONAL_PARTITIONING_04;F_REGISTER_01
tb_registers.read_before_write.01;A_FUNCTIONAL_PARTITIONING_04;F_REGISTER_01
tb_writeback.reset.01;I_RESET_01
tb_writeback.write.01;A_FUNCTIONAL_PARTITIONING_07;A_WRITEBACK_01
tb_writeback.bypass.01;A_FUNCTIONAL_PARTITIONING_07;A_WRITEBACK_01
tb_writeback.bubble.01;A_FUNCTIONAL_PARTITIONING_07;A_WRITEBACK_01;A_PIPELINE_BUBBLE_01
Expand Down
8 changes: 0 additions & 8 deletions docs/src/arch/2_overall-description.rst
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Expand Up @@ -64,14 +64,6 @@ The polarity of the reset signal mentionned in :req:ref:`U_RESET_01` is not spec

The address at which ECAP5-DPROC jumps after the reset signal is deasserted shall be hardware-configurable.

.. requirement:: U_HARDWARE_INTERRUPT_01

ECAP5-DPROC shall provide a signal which shall interrupt ECAP5-DPROC's execution flow while asserted.

.. requirement:: U_HARDWARE_INTERRUPT_02

ECAP5-DPROC shall jump to a hardware-configurable address when it is interrupted.

.. requirement:: U_DEBUG_01

ECAP5-DPROC shall be compliant with the RISC-V External Debug Support specification.
Expand Down
9 changes: 0 additions & 9 deletions docs/src/arch/3_requirements.rst
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Expand Up @@ -22,10 +22,6 @@ External Interface Requirements
- I
- 1
- Hardware reset.
* - irq_i
- I
- 1
- External interrupt request.

.. requirement:: I_CLK_01

Expand All @@ -36,11 +32,6 @@ External Interface Requirements

The rst_i signal shall hold ECAP5-DPROC in a reset state while asserted.

.. requirement:: I_IRQ_01
:derivedfrom: U_HARDWARE_INTERRUPT_01, U_HARDWARE_INTERRUPT_02

ECAP5-DPROC shall interrupt its execution flow when input irq_i is asserted and jump to a hardware-configurable address.

.. list-table:: ECAP5-DPROC memory interface signals
:header-rows: 1
:width: 100%
Expand Down
5 changes: 0 additions & 5 deletions docs/src/arch/4_configuration.rst
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Expand Up @@ -22,8 +22,3 @@ ECAP5-DPROC can be parameterized at build-time through instanciation parameters.
- 32
- Boot address loaded after reset
- 0000_1000h
* - IRQ_HANDLER_ADDR
- logic
- 32
- Address of the interrupt request handler
- 0000_0000h
10 changes: 2 additions & 8 deletions src/ecap5_dproc.sv
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Expand Up @@ -21,14 +21,11 @@
*/

module ecap5_dproc #(
parameter logic[31:0] BOOT_ADDRESS = 32'h00001000,
parameter logic[31:0] INTERRUPT_ADDRESS = 32'h00000000
parameter logic[31:0] BOOT_ADDRESS = 32'h00001000
)(
input logic clk_i,
input logic rst_i,

input logic irq_i,

output logic[31:0] wb_adr_o,
input logic[31:0] wb_dat_i,
output logic[31:0] wb_dat_o,
Expand Down Expand Up @@ -132,14 +129,11 @@ registers registers_inst (
);

fetch #(
.BOOT_ADDRESS (BOOT_ADDRESS),
.INTERRUPT_ADDRESS (INTERRUPT_ADDRESS)
.BOOT_ADDRESS (BOOT_ADDRESS)
) fetch_inst (
.clk_i (clk_i),
.rst_i (rst_i),

.irq_i (irq_i),

.branch_i (branch),
.branch_target_i (branch_target),

Expand Down
19 changes: 6 additions & 13 deletions src/fetch.sv
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Expand Up @@ -21,13 +21,11 @@
*/

module fetch #(
parameter logic[31:0] BOOT_ADDRESS = 32'h00001000,
parameter logic[31:0] INTERRUPT_ADDRESS = 32'h00000000
parameter logic[31:0] BOOT_ADDRESS = 32'h00001000
)(
input logic clk_i,
input logic rst_i,
// Jump inputs
input logic irq_i,
input logic branch_i,
input logic[31:0] branch_target_i,
// Wishbone master
Expand Down Expand Up @@ -248,24 +246,19 @@ end

/*
* The next value of PC comes from (in order of precedence):
* 0. External interrupt
* 1. Control flow change request (branch)
* 2. Default increment
* 0. Control flow change request (branch)
* 1. Default increment
*/
always_comb begin : pc_update
pc_d = pc_q;
// 2. Default increment
// 1. Default increment
if (output_valid_q && output_ready_i) begin
pc_d = pc_q + 4;
end
// 1. Control flow change request
// 0. Control flow change request
if (branch_i && !pending_jump_q) begin
pc_d = branch_target_i;
end
// 0. External interrupt
if (irq_i) begin
pc_d = INTERRUPT_ADDRESS;
end
end

always_ff @(posedge clk_i) begin
Expand All @@ -287,7 +280,7 @@ always_ff @(posedge clk_i) begin
pc_q <= pc_d;

// Jump triggering
if(irq_i || branch_i) begin
if(branch_i) begin
pending_jump_q <= 1;
output_valid_q <= 0;
end else begin
Expand Down
15 changes: 13 additions & 2 deletions tests/benches/decode/tb_decode.cpp
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Expand Up @@ -376,11 +376,22 @@ void tb_decode_reset(TB_Decode * tb) {
Vtb_decode * core = tb->core;
core->testcase = T_RESET;

//=================================
// Tick (0)

tb->reset();

//`````````````````````````````````
// Checks

tb->check(COND_output_valid, (core->output_valid_o == 0));

//`````````````````````````````````
// Formal Checks

CHECK("tb_decode.reset.01",
false,
"TODO");
tb->conditions[COND_output_valid],
"Failed to implement the output handshake", tb->err_cycles[COND_output_valid]);
}

void tb_decode_lui(TB_Decode * tb) {
Expand Down
31 changes: 1 addition & 30 deletions tests/benches/ecap5_dproc/tb_ecap5_dproc.cpp
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Expand Up @@ -53,9 +53,7 @@ enum TestcaseId {
T_LSM_ENABLE = 3,
T_BRANCH = 4,
T_BACK_TO_BACK = 5,
T_DATA_HAZARD = 6,
T_RESET = 7,
T_IRQ = 8
T_DATA_HAZARD = 6
};

class TB_Ecap5_dproc : public Testbench<Vtb_ecap5_dproc> {
Expand Down Expand Up @@ -102,7 +100,6 @@ class TB_Ecap5_dproc : public Testbench<Vtb_ecap5_dproc> {
}

void _nop() {
this->core->irq_i = 0;
this->core->wb_dat_i = 0;
this->core->wb_ack_i = 0;
this->core->wb_stall_i = 0;
Expand Down Expand Up @@ -987,28 +984,6 @@ void tb_ecap5_dproc_back_to_back(TB_Ecap5_dproc * tb) {
tb->reset();
}

void tb_ecap5_dproc_reset(TB_Ecap5_dproc * tb) {
Vtb_ecap5_dproc * core = tb->core;
core->testcase = T_RESET;

tb->reset();

CHECK("tb_ecap5_dproc.reset.01",
false,
"TODO");
}

void tb_ecap5_dproc_irq(TB_Ecap5_dproc * tb) {
Vtb_ecap5_dproc * core = tb->core;
core->testcase = T_IRQ;

tb->reset();

CHECK("tb_ecap5_dproc.irq.01",
false,
"TODO");
}

int main(int argc, char ** argv, char ** env) {
srand(time(NULL));
Verilated::traceEverOn(true);
Expand All @@ -1033,10 +1008,6 @@ int main(int argc, char ** argv, char ** env) {

tb_ecap5_dproc_back_to_back(tb);

tb_ecap5_dproc_reset(tb);

tb_ecap5_dproc_irq(tb);

/************************************************************/

printf("[ECAP5_DPROC]: ");
Expand Down
4 changes: 0 additions & 4 deletions tests/benches/ecap5_dproc/tb_ecap5_dproc.sv
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Expand Up @@ -26,8 +26,6 @@ module tb_ecap5_dproc (
input logic clk_i,
input logic rst_i,

input logic irq_i,

output logic[31:0] wb_adr_o,
input logic[31:0] wb_dat_i,
output logic[31:0] wb_dat_o,
Expand All @@ -43,8 +41,6 @@ ecap5_dproc dut (
.clk_i (clk_i),
.rst_i (rst_i),

.irq_i (irq_i),

.wb_adr_o (wb_adr_o),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
Expand Down
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