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portable: aarch64_sre: add the configuration and status registers to the fpu saved context
FPSR and FPCR are two 64-bits registers where only the lower 32 bits are defined. Save them when doing context switch with FPU context saving enabled. Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
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portable/GCC/ARM_AARCH64_SRE/port.c

Lines changed: 2 additions & 2 deletions
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@@ -122,8 +122,8 @@
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}
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/* The space on the stack required to hold the FPU registers.
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* There are 32 128-bit registers.*/
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#define portFPU_REGISTER_WORDS ( 32 * 2 )
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* There are 32 128-bit plus 2 64-bit status registers.*/
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#define portFPU_REGISTER_WORDS ( (32 * 2) + 2 )
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/*-----------------------------------------------------------*/
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portable/GCC/ARM_AARCH64_SRE/portASM.S

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@
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LDR X0, ullPortTaskHasFPUContextConst
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LDR X2, [X0]
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/* Save the FPU context, if any (32 128-bit registers). */
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/* Save the FPU context, if any (32 128-bit plus two 64-bit status registers). */
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CMP X2, #0
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B.EQ 1f
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STP Q0, Q1, [SP,#-0x20]!
@@ -107,6 +107,11 @@
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STP Q28, Q29, [SP,#-0x20]!
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STP Q30, Q31, [SP,#-0x20]!
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/* Even though upper 32 bits of FPSR and FPCR are reserved, save and restore the whole 64 bits to keep 16-byte SP alignement. */
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MRS X9, FPSR
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MRS X10, FPCR
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STP X9, X10, [SP, #-0x10]!
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110115
1:
111116
/* Store the critical nesting count and FPU context indicator. */
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STP X2, X3, [SP, #-0x10]!
@@ -157,6 +162,7 @@
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/* Restore the FPU context, if any. */
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CMP X2, #0
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B.EQ 1f
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LDP X9, X10, [SP], #0x10
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LDP Q30, Q31, [SP], #0x20
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LDP Q28, Q29, [SP], #0x20
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LDP Q26, Q27, [SP], #0x20
@@ -173,6 +179,8 @@
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LDP Q4, Q5, [SP], #0x20
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LDP Q2, Q3, [SP], #0x20
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LDP Q0, Q1, [SP], #0x20
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MSR FPSR, X9
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MSR FPCR, X10
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1:
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LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
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