-
Notifications
You must be signed in to change notification settings - Fork 6
/
Copy patharm6.c
1841 lines (1712 loc) · 50.5 KB
/
arm6.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#include "dill.h"
#include "dill_internal.h"
#include "arm6.h"
#include "config.h"
#include <stdio.h>
#ifdef HAVE_MALLOC_H
#include <malloc.h>
#endif
#undef NDEBUG
#include <assert.h>
#include <stdlib.h>
#include <string.h>
#define INSN_OUT(s, insn) do {\
if (s->p->cur_ip >= s->p->code_limit) {\
extend_dill_stream(s);\
}\
*(int*)s->p->cur_ip = (unsigned int)insn;\
if (s->dill_debug) dump_cur_dill_insn(s);\
s->p->cur_ip = (void*)(((long)s->p->cur_ip)+4);\
} while (0)\
#define COND(x) ((unsigned)((x)&0xf) << 28)
#define CLASS(x) (((x)&0x7) << 25)
#define OPCODE(x) (((x)&0xf) << 21) /* opcode field */
#define p(x) (((x)&0x1) << 23)
#define D(x) (((x)&0x1) << 22)
#define q(x) (((x)&0x1) << 21)
#define r(x) (((x)&0x1) << 20)
#define S(x) (((x)&0x1) << 20) /* update cond codes? */
#define FN(x) (((x)&0xf) << 16) /* Fn field */
#define FD(x) (((x)&0xf) << 12) /* Fn field */
#define cp_num(x) (((x)&0xf) << 8) /* cpu */
#define N(x) (((x)&0x1) << 7)
#define s(x) (((x)&0x1) << 6)
#define M(x) (((x)&0x1) << 5)
#define RN(x) (((x)&0xf) << 16) /* Rn field */
#define RD(x) (((x)&0xf) << 12) /* Rd field */
#define RM(x) (((x)&0xf) << 0) /* Rm field */
#define SHIFTI(x,t) ((((x)&0x1f) << 7) | ((t)&0x3)<<5)
#define SHIFTR(r,t) ((((r)&0xf) << 8) | ((t)&0x3)<<5| 1<<4)
#define IMM(x,r) (((x)&0xff) | ((((32-(r))>>1)&0xf)<< 8) | (1<<25)) /* simm8 field */
#define IM 0x2000
#define P(x) (((x)&0x1)<<19)
#define arm6_savei(s, imm) arm6_dproci(s, SUB, 0, _sp, _sp, ar_size);
#define arm6_andi(s, dest, src, imm) arm6_dproci(s, AND, 0, dest, src, imm)
#define arm6_movi(s, dest, src) arm6_dproc(s, MOV, 0, dest, 0, src)
#define arm6_movf(s, dest, src) arm6_fproc2(s, 0, 0, 0, dest, src)
#define arm6_movd(s, dest, src) arm6_fproc2(s, 0, 1, 0, dest, src)
#define arm6_lshi(s, dest, src,imm) arm6_dproci(s, MOV, LLshift, dest, src, imm)
#define arm6_rshi(s,dest,src,imm) arm6_dproci(s, MOV, LRshift, dest, src, imm)
#define arm6_rshai(s,dest,src,imm) arm6_dproci(s, MOV, ARshift, dest, src, imm)
#define arm6_nop(s) arm6_movi(s, _r0, _r0)
#define arm6_raw_push(s, reg) INSN_OUT(s, COND(AL)|CLASS(2)|1<<24|1<<21|0xd<<16|reg<<12|4)
#define arm6_raw_pop(s, reg) INSN_OUT(s, COND(AL)|CLASS(2)|1<<23|1<<20|0xd<<16|reg<<12|4)
#define IREG 0
#define FREG 1
#define roundup(a,b) ((a + (b-1)) & (-b))
static void
arm6_pldsti(dill_stream s, int type, int ls, int dest, int src, long offset);
static void
arm6_pldst(dill_stream s, int type, int ls, int dest, int src1, int src2);
static void int_arm6_bswap(dill_stream s, int type, int reg);
extern void
arm6_bswap(dill_stream s, int type, int data2, int dest, int src)
{
switch(type) {
case DILL_L: case DILL_UL: case DILL_I: case DILL_U:
INSN_OUT(s, COND(AL)| 0b011010111111<<16|RD(dest)|RM(src)|0xf<<8|3<<4);
break;
case DILL_US: case DILL_S:
INSN_OUT(s, COND(AL)| 0b011010111111<<16|RD(dest)|RM(src)|0xf<<8|0xb<<4);
break;
case DILL_C: case DILL_UC:
/* nothing to do */
break;
case DILL_F:
INSN_OUT(s, COND(AL)| CLASS(7)|OPCODE(0)|1<<20|FN(src>>1)|N(src)|RD(_r0)|cp_num(0xa)|1<<4);/*fmrs*/
int_arm6_bswap(s, DILL_L, _r0);
INSN_OUT(s, COND(AL)| CLASS(7)|OPCODE(0)|0<<20|FN(dest>>1)|N(dest)|RD(_r0)|cp_num(0xa)|1<<4);/*fmsr*/
break;
case DILL_D:
INSN_OUT(s, COND(AL)| CLASS(6)|OPCODE(2)|r(1)|FN(_r1)|RD(_r0)|cp_num(0xb)|1<<4|(src>>1)|(src&1)<<5);/*fmrrd*/
int_arm6_bswap(s, DILL_L, _r0);
int_arm6_bswap(s, DILL_L, _r1);
INSN_OUT(s, COND(AL)| CLASS(6)|OPCODE(2)|FN(_r0)|RD(_r1)|cp_num(0xb)|1<<4|(dest>>1)|(dest&1)<<5);/*fmdrr*/
break;
}
}
static void
int_arm6_bswap(dill_stream s, int type, int reg)
{
arm6_bswap(s, type, 0, reg, reg);
}
extern void
arm6_pbsloadi(dill_stream s, int type, int junk, int dest, int src, long offset)
{
arm6_pldsti(s, type, 1, dest, src, offset);
int_arm6_bswap(s, type, dest);
}
extern void
arm6_pbsload(dill_stream s, int type, int junk, int dest, int src1, int src2)
{
arm6_pldst(s, type, 1, dest, src1, src2);
int_arm6_bswap(s, type, dest);
}
static
struct basic_type_info
{ char size;
char align;
char reg_type;
} type_info[] = {
{ 1, 1, IREG}, /* C */
{ 1, 1, IREG}, /* UC */
{ 2, 2, IREG}, /* S */
{ 2, 2, IREG}, /* US */
{ 4, 4, IREG}, /* I */
{ 4, 4, IREG}, /* U */
{ sizeof(long), sizeof(long), IREG}, /* UL */
{ sizeof(long), sizeof(long), IREG}, /* L */
{ sizeof(char*), sizeof(char*), IREG}, /* P */
{ sizeof(float), sizeof(float), FREG}, /* F */
{ sizeof(double), 4, FREG}, /* D */
{ 0, 8, IREG}, /* V */
{ -1, 8, IREG}, /* B */
{ 4, 8, IREG}, /* EC */
};
int arm6_type_align[] = {
1, /* C */
1, /* UC */
2, /* S */
2, /* US */
4, /* I */
4, /* U */
sizeof(unsigned long), /* UL */
sizeof(long), /* L */
sizeof(char*), /* P */
4, /* F */
4, /* D */
1, /* V */
4, /* B */
sizeof(long), /* EC */
};
int arm6_type_size[] = {
1, /* C */
1, /* UC */
2, /* S */
2, /* US */
4, /* I */
4, /* U */
sizeof(unsigned long), /* UL */
sizeof(long), /* L */
sizeof(char*), /* P */
4, /* F */
8, /* D */
1, /* V */
8, /* B */
sizeof(char*), /* EC */
};
extern void arm6_dproc(dill_stream s, int op, int shift_code, int dest, int src1, int src2)
{
int shift = 0;
if (shift_code != 0) {
shift_code &= 0x3;
shift = SHIFTR(src2, shift_code);
src2 = src1;
src1 = 0;
}
INSN_OUT(s, COND(AL)|CLASS(0x0)|OPCODE(op)|S(0)|RN(src1)|RD(dest)|RM(src2)|shift);
}
extern void arm6_dproc2(dill_stream s, int op, int fop, int dest, int src)
{
if (op == RSB) {
arm6_dproci(s, RSB, 0, dest, src, 0);
} else if (op == CMN) { /* !a */
INSN_OUT(s, COND(AL)|CLASS(0x0)|OPCODE(CMP)|S(1)|RN(src)|RD(src)|IMM(0,0));
INSN_OUT(s, COND(NE)|CLASS(0x0)|OPCODE(MOV)|S(0)|RN(0)|RD(dest)|IMM(0, 0));
INSN_OUT(s, COND(EQ)|CLASS(0x0)|OPCODE(MOV)|S(0)|RN(0)|RD(dest)|IMM(1, 0));
} else {
INSN_OUT(s, COND(AL)|CLASS(0x0)|OPCODE(op)|S(0)|RN(src)|RD(dest)|RM(src));
}
}
extern void arm6_negf(dill_stream s, int op, int fd, int dest, int src)
{
arm6_fproc2(s, op, fd, 0, dest, src);
}
extern void arm6_fproc2(dill_stream s, int op, int fd, int n, int dest, int src)
{
INSN_OUT(s, COND(AL)|CLASS(0x7)|p(1)|D(dest&1)|q(1)|r(1)|FN(op)|N(n)|FD(dest>>1)|(0xa+fd)<<8|s(1)|M(src&1)|((src>>1)&0xf));
}
extern int
arm6_local(dill_stream s, int type)
{
arm6_mach_info ami = (arm6_mach_info) s->p->mach_info;
ami->act_rec_size += roundup(type_info[type].size, ami->stack_align);
return (-ami->act_rec_size) - 14 * 4 /* int regs to save */
- 8 * 3 * 4 /* float regs to save */;
}
extern int
arm6_localb(dill_stream s, int size)
{
arm6_mach_info ami = (arm6_mach_info) s->p->mach_info;
if (size < 0) size = 0;
ami->act_rec_size = roundup(ami->act_rec_size, size);
ami->act_rec_size += roundup(size, ami->stack_align);
return (-ami->act_rec_size) - 14 * 4 /* int regs to save */
- 8 * 3 * 4 /* float regs to save */;
}
extern int arm6_local_op(dill_stream s, int flag, int val)
{
int size = val;
if (flag == 0) {
size = type_info[val].size;
}
if (size < 0) size = 0;
return arm6_localb(s, size);
}
static int
is_temp(int ireg)
{
return (ireg <= _r4); /* higher regs are saved by the callee */
}
static int
is_ftemp(int freg)
{
return (freg <= _f4); /* higher regs are saved by the callee */
}
extern void
arm6_save_restore_op(dill_stream s, int save_restore, int type, int reg)
{
arm6_mach_info ami = (arm6_mach_info) s->p->mach_info;
if (save_restore == 0) { /* save */
switch (type) {
case DILL_D: case DILL_F:
if (is_ftemp(reg)) {
arm6_pstorei(s, type, 0, reg, _fp, - 13*4 - reg * 12);
}
break;
default:
if (is_temp(reg)) {
arm6_pstorei(s, type, 0, reg, _sp, ami->gp_save_offset + (reg - _r0) * ami->stack_align);
}
break;
}
} else { /* restore */
switch (type) {
case DILL_D: case DILL_F:
if (is_ftemp(reg)) {
arm6_ploadi(s, type, 0, reg, _fp, -13*4 - reg * 12);
}
break;
default:
if (is_temp(reg)) {
arm6_ploadi(s, type, 0, reg, _sp, ami->gp_save_offset + (reg - _r0) * ami->stack_align);
}
break;
}
}
}
static void
arm6_movi2f(dill_stream s, int dest, int src)
{
arm6_mach_info ami = (arm6_mach_info) s->p->mach_info;
arm6_pstorei(s, DILL_I, 0, src, _fp, ami->conversion_word);
arm6_ploadi(s, DILL_F, 0, dest, _fp, ami->conversion_word);
}
static void
arm6_movf2i(dill_stream s, int dest, int src)
{
arm6_mach_info ami = (arm6_mach_info) s->p->mach_info;
arm6_pstorei(s, DILL_F, 0, src, _fp, ami->conversion_word);
arm6_ploadi(s, DILL_I, 0, dest, _fp, ami->conversion_word);
}
static void
arm6_movd2i(dill_stream s, int dest, int src)
{
arm6_mach_info ami = (arm6_mach_info) s->p->mach_info;
arm6_pstorei(s, DILL_D, 0, src, _fp, ami->conversion_word);
if (ami->stack_align == 8) {
arm6_ploadi(s, DILL_L, 0, dest, _fp, ami->conversion_word);
} else {
arm6_ploadi(s, DILL_I, 0, dest, _fp, ami->conversion_word);
arm6_ploadi(s, DILL_I, 0, dest+1, _fp, ami->conversion_word+4);
}
}
static void
arm6_movi2d(dill_stream s, int dest, int src)
{
arm6_mach_info ami = (arm6_mach_info) s->p->mach_info;
if (ami->stack_align == 8) {
arm6_pstorei(s, DILL_L, 0, src, _fp, ami->conversion_word);
} else {
arm6_pstorei(s, DILL_I, 0, src, _fp, ami->conversion_word);
arm6_pstorei(s, DILL_I, 0, src+1, _fp, ami->conversion_word+4);
}
arm6_ploadi(s, DILL_D, 0, dest, _fp, ami->conversion_word);
}
extern void arm6_fproc(dill_stream s, int arm6_op, int fd, int dest, int src1, int src2)
{
INSN_OUT(s, COND(AL)|CLASS(0x7)|D(dest&0x1)|p(arm6_op>>3)|q(arm6_op>>2)|r(arm6_op>>1)|s(arm6_op)|(arm6_op&0x1)<<15|((src1>>1)&0xf)<<16|((dest>>1)&0xf)<<12|(0xa+(fd))<<8|(src1&1)<<7|(src2>>1)&0xf|(src2&0x1)<<5);
}
extern void arm6_dproci(dill_stream s, int op, int shift_code, int dest, int src1, long imm)
{
int shift = 0;
int setcc = 0;
if (op == CMP) setcc = 1;
if (shift_code != 0) {
/* must already be a mov op */
shift_code &= 0x3;
shift = SHIFTI(imm, shift_code);
INSN_OUT(s, COND(AL)|CLASS(0x0)|OPCODE(op)|S(0)|RN(src1)|RD(dest)|shift|RM(src1));
return;
}
if ((imm >= 0) && (imm < 256)) {
/* arith format */
INSN_OUT(s, COND(AL)|CLASS(0x0)|OPCODE(op)|S(setcc)|RN(src1)|RD(dest)|IMM(imm, 0));
} else {
arm6_set(s, _v1, imm);
INSN_OUT(s, COND(AL)|CLASS(0x0)|OPCODE(op)|S(setcc)|RN(src1)|RD(dest)|RM(_v1));
}
}
/*
* ARM stack frame organization
*
* pushed args
* ------------ SP value at entry FP value
* callee-saved int regs
* pushed with stmdb space for 14
* callee-saved float regs space for 8
*
* ------------ SP value after STMDB
* local variables
* ------------ final SP value
*/
extern void
arm6_proc_start(dill_stream s, char *subr_name, int arg_count, arg_info_list args,
dill_reg *arglist)
{
int i;
arm6_mach_info ami = (arm6_mach_info) s->p->mach_info;
int cur_arg_offset = 0;
int next_core_register = _r0;
int next_float_register = _f0;
/* emit start insns */
INSN_OUT(s, 0xFF000000);
INSN_OUT(s, 0xFF000000);
INSN_OUT(s, 0xFF000000);
arm6_movi(s, _r12, _sp);
/* stmdb sp!, {r11, r12, lr, pc} */
INSN_OUT(s, COND(AL)|CLASS(4)|1<<24/*p*/|RN(_sp)|1<<_r11|1<<_r12|1<<_link|1<<_pc);
arm6_dproci(s, SUB, 0, _sp, _sp, 14*4 ); /* instead of write back */
arm6_nop(s); /* placeholder for float save */
arm6_dproci(s, SUB, 0, _r11, _r12, 4);
ami->save_insn_offset = (long)s->p->cur_ip - (long)s->p->code_base;
arm6_nop(s); /* room for largest stack adjust insn, 5 nops */
arm6_nop(s);
arm6_nop(s);
arm6_nop(s);
arm6_nop(s);
ami->conversion_word = arm6_local(s, DILL_D);
ami->conversion_word = arm6_local(s, DILL_D);
ami->conversion_word = arm6_local(s, DILL_D);
/* load params from regs */
for (i = 0; i < arg_count; i++) {
int item_size = 1;
switch (args[i].type) {
case DILL_D:
if (ami->hard_float) {
if (next_float_register % 2) {
/* double is only even regs, skip one */
next_float_register++;
}
} else {
if (next_core_register % 2) {
/* double is only even regs, skip one */
next_core_register++;
cur_arg_offset += 4;
}
}
item_size = 2;
case DILL_F:
/* falling through */
if (ami->hard_float) {
if (next_float_register <= _f31) {
args[i].is_register = 1;
args[i].in_reg = next_float_register;
args[i].out_reg = next_float_register;
} else {
args[i].is_register = 0;
}
next_float_register += ((args[i].type == DILL_D) ? 2 : 1);
break;
}
/* if soft float, fall through, with item size at 2 for D */
default:
if (next_core_register < _r4) {
args[i].is_register = 1;
args[i].in_reg = next_core_register;
args[i].out_reg = next_core_register;
} else {
args[i].is_register = 0;
}
next_core_register+=item_size;
break;
}
args[i].offset = cur_arg_offset;
cur_arg_offset += roundup(type_info[(int)args[i].type].size, ami->stack_align);
}
for (i = 0; i < arg_count; i++) {
int tmp_reg;
// printf("Handling arg %d, is_reg %d\n", i, args[i].is_register);
if (args[i].is_register) {
/* only some moved into registers */
if (!dill_raw_getreg(s, &tmp_reg, args[i].type, DILL_VAR)) {
/* not enough regs for this, store it to the stack */
int real_offset = - args[i].offset - 4*4;
if (arglist != NULL) arglist[i] = -1;
arm6_pstorei(s, DILL_I, 0, args[i].in_reg, _fp,
real_offset);
args[i].in_reg = -1;
args[i].out_reg = -1;
args[i].offset = real_offset;
args[i].is_register = 0;
continue;
}
if (args[i].is_register) {
if ((args[i].type != DILL_F) && (args[i].type != DILL_D)) {
arm6_movi(s, tmp_reg, args[i].in_reg);
} else if (args[i].type == DILL_F) { /* must be float */
if (ami->hard_float) {
arm6_movf(s, tmp_reg, args[i].in_reg);
} else {
int src = args[i].in_reg;
int dest = tmp_reg;
INSN_OUT(s, COND(AL)| CLASS(7)|OPCODE(0)|0<<20|FN(dest>>1)|N(dest)|RD(src)|cp_num(0xa)|1<<4);/*fmsr*/
}
} else {
if (ami->hard_float) {
arm6_movd(s, tmp_reg, args[i].in_reg);
} else {
INSN_OUT(s, COND(AL)| CLASS(6)|OPCODE(2)|FN(args[i].in_reg+1)|RD(args[i].in_reg)|cp_num(0xb)|1<<4|(tmp_reg>>1)|(tmp_reg&1)<<5);/*fmdrr*/
}
}
} else {
/* general offset from fp*/
int real_offset = args[i].offset - 3*4;
arm6_ploadi(s, args[i].type, 0, tmp_reg, _fp, real_offset);
}
if (arglist != NULL) arglist[i] = tmp_reg;
args[i].in_reg = tmp_reg;
args[i].is_register = 1;
} else {
if (!ami->hard_float && ((args[i].type == DILL_F) || (args[i].type == DILL_D))) {
int tmp_reg;
dill_raw_getreg(s, &tmp_reg, args[i].type, DILL_VAR);
/* general offset from fp*/
int real_offset = args[i].offset - 3*4;
arm6_ploadi(s, args[i].type, 0, tmp_reg, _fp, real_offset);
if (arglist != NULL) arglist[i] = tmp_reg;
args[i].in_reg = tmp_reg;
args[i].is_register = 1;
} else {
/* leave it on the stack */
int real_offset = args[i].offset - 3*4;
if (arglist != NULL) arglist[i] = -1;
args[i].in_reg = -1;
args[i].out_reg = -1;
args[i].offset = real_offset;
}
}
}
}
extern void
arm6_ploadi(dill_stream s, int type, int junk, int dest, int src, long offset)
{
arm6_pldsti(s, type, 1, dest, src, offset);
}
extern void
arm6_pload(dill_stream s, int type, int junk, int dest, int src1, int src2)
{
arm6_pldst(s, type, 1, dest, src1, src2);
}
/* byte and whole word version */
#define ARM6_LDSTI(s,u,b,ls,rn,rd,offset) INSN_OUT(s, COND(AL)|CLASS(2)|(1<<24)|((u&1)<<23)|((b&1)<<22)|(ls&1)<<20|RN(rn)|RD(rd)|(0x7ff&offset))
/* halfword version */
#define ARM6_LDSTHI(s,u,ls,rn,rd,sh,offset) INSN_OUT(s, COND(AL)|CLASS(0)|(1<<24)|((u&1)<<23)|(1<<22)|(ls&1)<<20|RN(rn)|RD(rd)|(1<<7)|((sh&0x3)<<5)|(1<<4)|(0xf&offset)|((offset&0xf0)<<4))
/* float version */
#define ARM6_LDSTFI(s,u,fd,ls,rn,rd,offset) INSN_OUT(s, COND(AL)|CLASS(6)|(1<<24)|((u&1)<<23)|(ls&1)<<20|RN(rn)|D(rd&1)|RD(rd>>1)|((0xa+(fd))<<8)|(0xff&(offset>>2)))
extern void
arm6_pstorei(dill_stream s, int type, int junk, int dest, int src, long offset)
{
arm6_pldsti(s, type, 0, dest, src, offset);
}
static void
arm6_pldsti(dill_stream s, int type, int ls, int dest, int src, long offset)
{
int u = 1;
int max_offset;
switch (type) {
case DILL_S: case DILL_US: case DILL_D: case DILL_F:
max_offset = 256;
break;
default:
max_offset = 2048;
break;
}
if (((long)offset) >= max_offset || ((long)offset) < -max_offset) {
arm6_set(s, _v1, offset);
arm6_pldst(s, type, ls, dest, src, _v1);
return;
}
if (offset < 0) {
u = 0;
offset = -offset;
}
switch (type) {
case DILL_F:
ARM6_LDSTFI(s, u, 0, ls, src, dest, offset);
break;
case DILL_D:
ARM6_LDSTFI(s, u, 1, ls, src, dest, offset);
break;
case DILL_C:
case DILL_UC:
ARM6_LDSTI(s, u, 1, ls, src, dest, offset);
break;
case DILL_I:
case DILL_U:
case DILL_L:
case DILL_UL:
case DILL_P:
ARM6_LDSTI(s, u, 0, ls, src, dest, offset);
break;
case DILL_S:
if (ls == 1) { /* this is a load */
ARM6_LDSTHI(s,u,ls,src,dest,0x3,offset);
break;
}
/* fall through */
case DILL_US:
ARM6_LDSTHI(s,u,ls,src,dest,0x1,offset);
break;
default:
break;
}
}
#define ARM6_LDST(s,u,b,ls,rn,rd,rm) INSN_OUT(s, COND(AL)|CLASS(3)|(1<<24)|((u&1)<<23)|((b&1)<<22)|(ls&1)<<20|RN(rn)|RD(rd)|(0xf&rm))
#define ARM6_LDSTH(s,u,ls,rn,rd,sh,rm) INSN_OUT(s, COND(AL)|CLASS(0)|(1<<24)|((u&1)<<23)|(ls&1)<<20|RN(rn)|RD(rd)|(1<<7)|((sh&0x3)<<5)|(1<<4)|(0xf&rm))
extern void
arm6_pstore(dill_stream s, int type, int junk, int dest, int src1, int src2)
{
arm6_pldst(s, type, 0, dest, src1, src2);
}
static void
arm6_pldst(dill_stream s, int type, int ls, int dest, int src1, int src2)
{
switch (type) {
case DILL_F:
arm6_dproc(s, ADD, 0, _v1, src1, src2);
ARM6_LDSTFI(s, 0, 0, ls, _v1, dest, 0);
break;
case DILL_D:
arm6_dproc(s, ADD, 0, _v1, src1, src2);
ARM6_LDSTFI(s, 0, 1, ls, _v1, dest, 0);
break;
case DILL_L: case DILL_UL: case DILL_P: case DILL_I: case DILL_U: case DILL_EC:
ARM6_LDST(s,1,0,ls,src1,dest,src2);
break;
case DILL_S:
if (ls == 1) { /* this is a load */
ARM6_LDSTH(s,1,ls,src1,dest,0x3,src2);
break;
}
/* fall through */
case DILL_US:
ARM6_LDSTH(s,1,ls,src1,dest,0x1,src2);
break;
case DILL_C: case DILL_UC:
ARM6_LDST(s,1,1,ls,src1,dest,src2);
break;
default:
break;
}
}
extern int arm6_hidden_modi(int a, int b);
extern long arm6_hidden_mod(long a, long b);
extern unsigned long arm6_hidden_umod(unsigned long a, unsigned long b);
extern unsigned int arm6_hidden_umodi(unsigned int a, unsigned int b);
extern double arm6_hidden_ultod(unsigned long a);
extern float arm6_hidden_ultof(unsigned long a);
extern unsigned long arm6_hidden_dtoul(double a);
extern unsigned int arm6_hidden_dtou(double a);
extern unsigned long arm6_hidden_ftoul(float a);
extern unsigned int arm6_hidden_ftou(float a);
extern unsigned long arm6_hidden_udiv(unsigned long a, unsigned long b);
extern long arm6_hidden_div(long a, long b);
#define FIX_SRC2_POSTFIX \
if (tmp_src2 != -1) {\
arm6_raw_pop(s, tmp_src2);\
}
#define FIX_SRC2_PREFIX \
int tmp_src2 = -1;\
/* \
* DILL lets us use ret_reg in operators in some circumstances, so src1 \
* or src2 might be ret_reg. This is a problem if it's src2 and we do \
* a call.\
*/\
if (src2 == _a1) {\
tmp_src2 = _a4; /* arbitrary */\
if (src1 == tmp_src2) tmp_src2 = _a3;\
arm6_raw_push(s, tmp_src2);\
dill_movl(s, tmp_src2, _a1);\
src2 = tmp_src2;\
}
extern void arm6_mod(dill_stream s, int sign, int type_long, int dest,
int src1, int src2)
{
int return_reg;
FIX_SRC2_PREFIX;
if (sign == 1) {
/* signed case */
if (type_long) {
return_reg = dill_scalll(s, (void*)arm6_hidden_mod, "arm6_hidden_mod", "%l%l", src1, src2);
dill_movl(s, dest, return_reg);
} else {
return_reg = dill_scalli(s, (void*)arm6_hidden_modi, "arm6_hidden_modi", "%i%i", src1, src2);
dill_movi(s, dest, return_reg);
}
} else {
/* unsigned case */
if (type_long) {
return_reg = dill_scalll(s, (void*)arm6_hidden_umod, "arm6_hidden_umod", "%l%l", src1, src2);
dill_movul(s, dest, return_reg);
} else {
return_reg = dill_scallu(s, (void*)arm6_hidden_umodi, "arm6_hidden_umodi", "%u%u", src1, src2);
dill_movu(s, dest, return_reg);
}
}
FIX_SRC2_POSTFIX;
}
extern void arm6_modi(dill_stream s, int data1, int data2, int dest, int src1,
long imm)
{
arm6_set(s, _v1, imm);
arm6_mod(s, data1, data2, dest, src1, _v1);
}
extern void arm6_div(dill_stream s, int unsign, int junk, int dest, int src1,
int src2)
{
int return_reg;
void *routine = (void*) &arm6_hidden_div;
if (unsign) routine = (void*) &arm6_hidden_udiv;
FIX_SRC2_PREFIX;
return_reg = dill_scalll(s, routine, "routine", "%l%l", src1, src2);
FIX_SRC2_POSTFIX;
dill_movl(s, dest, return_reg);
}
#define MUL(s,A,S,Rd,Rs,Rm) INSN_OUT(s, COND(AL)|(A&1)<<21|(S&1)<<20|RN(Rd)|RD(0)|(Rs&0xf)<<8|0x90|(Rm&0xf))
extern void arm6_mul(dill_stream s, int unsign, int junk, int dest, int src1,
int src2)
{
MUL(s, 0, 0, dest, src1, src2);
}
extern void arm6_muli(dill_stream s, int unsign, int junk, int dest, int src,
long imm)
{
arm6_set(s, _v1, imm);
MUL(s, 0, 0, dest, src, _v1);
}
extern void arm6_divi(dill_stream s, int unsign, int junk, int dest, int src,
long imm)
{
arm6_set(s, _v1, imm);
arm6_div(s, unsign, junk, dest, src, _v1);
}
extern void
arm6_mov(dill_stream s, int type, int junk, int dest, int src)
{
if (src == dest) return;
switch(type) {
case DILL_D:
arm6_movd(s, dest, src);
break;
case DILL_F:
arm6_movf(s, dest, src);
break;
default:
arm6_movi(s, dest, src);
}
}
static void
arm6_saverestore_floats(dill_stream s, int saverestore)
{
int i;
for (i=1; i <8; i++) {
if (dill_mustsave(&s->p->tmp_f, i)) {
arm6_save_restore_op(s, saverestore, DILL_D, i);
}
}
}
#define CONV(x,y) ((x*100)+y)
extern void
arm6_convert(dill_stream s, int from_type, int to_type,
int dest, int src)
{
from_type &= 0xf;
to_type &= 0xf;
switch(CONV(from_type, to_type)) {
case CONV(DILL_I, DILL_L):
case CONV(DILL_I, DILL_U):
case CONV(DILL_I,DILL_UL):
case CONV(DILL_UL,DILL_I):
case CONV(DILL_UL,DILL_U):
case CONV(DILL_L,DILL_U):
case CONV(DILL_U,DILL_UL):
case CONV(DILL_U,DILL_L):
case CONV(DILL_L,DILL_I):
case CONV(DILL_UL,DILL_L):
case CONV(DILL_L,DILL_UL):
case CONV(DILL_P,DILL_UL):
case CONV(DILL_UL,DILL_P):
case CONV(DILL_U,DILL_I):
if(src == dest) return;
arm6_movi(s, dest,src);
break;
case CONV(DILL_F,DILL_D):
arm6_fproc2(s, 0b0111, 0, 1, dest, src); /* fcvtds */
break;
case CONV(DILL_F,DILL_L):
case CONV(DILL_F,DILL_I):
case CONV(DILL_F,DILL_S):
case CONV(DILL_F,DILL_C):
arm6_fproc2(s, 0b1101, 0, 1, src, src); /* ftosis */
INSN_OUT(s, COND(AL)| CLASS(7)|OPCODE(0)|1<<20|FN(src>>1)|N(src)|RD(dest)|cp_num(0xa)|1<<4);/*fmrs*/
break;
case CONV(DILL_F,DILL_U):
case CONV(DILL_F,DILL_US):
case CONV(DILL_F,DILL_UC):
{
int ret;
arm6_saverestore_floats(s, 0);
ret = dill_scallu(s, (void*)arm6_hidden_ftou, "arm6_hidden_ftou", "%f", src);
arm6_saverestore_floats(s, 1);
arm6_mov(s, DILL_UL, 0, dest, ret);
}
break;
/* fallthrough */
case CONV(DILL_F,DILL_UL):
{
int ret;
arm6_saverestore_floats(s, 0);
ret = dill_scallul(s, (void*)arm6_hidden_ftoul, "arm6_hidden_ftoul", "%f", src);
arm6_saverestore_floats(s, 1);
arm6_mov(s, DILL_UL, 0, dest, ret);
}
break;
case CONV(DILL_D,DILL_F):
arm6_fproc2(s, 0b0111, 1, 1, dest, src); /* fcvtds */
break;
case CONV(DILL_D,DILL_L):
case CONV(DILL_D,DILL_I):
case CONV(DILL_D,DILL_S):
case CONV(DILL_D,DILL_C):
arm6_fproc2(s, 0b1101, 1, 1, src, src); /* ftosid */
INSN_OUT(s, COND(AL)| CLASS(7)|OPCODE(0)|1<<20|FN(src>>1)|N(src)|RD(dest)|cp_num(0xa)|1<<4);/*fmsr*/
break;
case CONV(DILL_D,DILL_U):
case CONV(DILL_D,DILL_US):
case CONV(DILL_D,DILL_UC):
{
int ret;
arm6_saverestore_floats(s, 0);
ret = dill_scallu(s, (void*)arm6_hidden_dtou, "arm6_hidden_dtou", "%d", src);
arm6_saverestore_floats(s, 1);
arm6_mov(s, DILL_U, 0, dest, ret);
}
break;
case CONV(DILL_D,DILL_UL):
{
int ret;
arm6_saverestore_floats(s, 0);
ret = dill_scallul(s, (void*)arm6_hidden_dtoul, "arm6_hidden_dtoul", "%d", src);
arm6_saverestore_floats(s, 1);
arm6_mov(s, DILL_UL, 0, dest, ret);
}
break;
case CONV(DILL_I,DILL_D):
case CONV(DILL_L,DILL_D):
case CONV(DILL_C,DILL_D):
case CONV(DILL_S,DILL_D):
INSN_OUT(s, COND(AL)| CLASS(7)|OPCODE(0)|0<<20|FN(dest>>1)|N(dest)|RD(src)|cp_num(0xa)|1<<4);/*fmsr*/
arm6_fproc2(s, 0x8, 1, 1, dest, dest); /* fsitod */
break;
case CONV(DILL_U,DILL_D):
case CONV(DILL_UL,DILL_D):
case CONV(DILL_UC,DILL_D):
case CONV(DILL_US,DILL_D):
{
int ret;
arm6_saverestore_floats(s, 0);
ret = dill_scalld(s, (void*)arm6_hidden_ultod, "arm6_hidden_ultod", "%l", src);
arm6_saverestore_floats(s, 1);
arm6_mov(s, DILL_D, 0, dest, ret);
}
break;
case CONV(DILL_I,DILL_F):
case CONV(DILL_L,DILL_F):
case CONV(DILL_C,DILL_F):
case CONV(DILL_S,DILL_F):
INSN_OUT(s, COND(AL)| CLASS(7)|OPCODE(0)|0<<20|FN(dest>>1)|N(dest)|RD(src)|cp_num(0xa)|1<<4);/*fmsr*/
arm6_fproc2(s, 0x8, 0, 1, dest, dest); /* fsitos */
break;
case CONV(DILL_U,DILL_F):
case CONV(DILL_UL,DILL_F):
case CONV(DILL_UC,DILL_F):
case CONV(DILL_US,DILL_F):
{
int ret;
arm6_saverestore_floats(s, 0);
ret = dill_scallf(s, (void*)arm6_hidden_ultof, "arm6_hidden_ultof", "%l", src);
arm6_saverestore_floats(s, 1);
arm6_mov(s, DILL_D, 0, dest, ret);
}
break;
case CONV(DILL_C,DILL_UL):
case CONV(DILL_C,DILL_L):
case CONV(DILL_C,DILL_I):
case CONV(DILL_C,DILL_U):
case CONV(DILL_C, DILL_S):
case CONV(DILL_S, DILL_C):
case CONV(DILL_US, DILL_C):
arm6_lshi(s, dest, src, 24);
arm6_rshai(s, dest, dest, 24);
break;
case CONV(DILL_I, DILL_C):
case CONV(DILL_U, DILL_C):
case CONV(DILL_L, DILL_C):
case CONV(DILL_UL, DILL_C):
case CONV(DILL_C, DILL_UC):
case CONV(DILL_I, DILL_UC):
case CONV(DILL_S, DILL_UC):
case CONV(DILL_U, DILL_UC):
case CONV(DILL_L, DILL_UC):
case CONV(DILL_UL, DILL_UC):
case CONV(DILL_US, DILL_UC):
arm6_andi(s, dest, src, 0xff);
break;
case CONV(DILL_S,DILL_L):
case CONV(DILL_S,DILL_UL):
case CONV(DILL_S,DILL_I):
case CONV(DILL_S,DILL_U):
case CONV(DILL_S,DILL_US):
case CONV(DILL_US,DILL_S):
arm6_lshi(s, dest, src, 16);
arm6_rshai(s, dest, dest, 16);
break;
case CONV(DILL_C, DILL_US):
/* signext24 - lsh24, rsha24, trunc 16 */
arm6_lshi(s, dest, src, 24);
arm6_rshai(s, dest, dest, 24);
arm6_andi(s, dest, dest, 0xffff);
break;
case CONV(DILL_US,DILL_I):
case CONV(DILL_US,DILL_L):
case CONV(DILL_US,DILL_U):
case CONV(DILL_US,DILL_UL):
case CONV(DILL_I,DILL_S):
case CONV(DILL_U,DILL_S):
case CONV(DILL_L,DILL_S):
case CONV(DILL_UL,DILL_S):
case CONV(DILL_I,DILL_US):
case CONV(DILL_U,DILL_US):
case CONV(DILL_L,DILL_US):
case CONV(DILL_UL,DILL_US):
arm6_lshi(s, dest, src, 16);
arm6_rshi(s, dest, dest, 16);
break;
default:
printf("Unknown case in arm convert %d\n", CONV(from_type,to_type));
}
}
static signed char op_conds[] = {
EQ, /* dill_beq_code */ /* signed */
GE, /* dill_bge_code */
GT, /* dill_bgt_code */
LE, /* dill_ble_code */
LT, /* dill_blt_code */
NE, /* dill_bne_code */
EQ, /* dill_beq_code */ /* unsigned */
CS, /* dill_bge_code */
HI, /* dill_bgt_code */
LS, /* dill_ble_code */
CC, /* dill_blt_code */
NE, /* dill_bne_code */
};
#define CMF 0x4
extern void
arm6_branch(dill_stream s, int op, int type, int src1, int src2, int label)
{
switch(type) {
case DILL_D:
case DILL_F:
arm6_fproc2(s, 0b0100, (type == DILL_D), 0, src1, src2); /* fcmps */
INSN_OUT(s, COND(AL)|0b111011110001<<16|0b1111101000010000); /* fmstat */
dill_mark_branch_location(s, label);
INSN_OUT(s, COND(op_conds[op])|CLASS(0x5)|/*disp */0);/* b*/
break;
break;
case DILL_U:
case DILL_UL:
op += 6; /* second set of codes */
/* fall through */
default:
INSN_OUT(s, COND(AL)|CLASS(0x0)|OPCODE(CMP)|S(1)|RN(src1)|RD(0)|RM(src2));
dill_mark_branch_location(s, label);
INSN_OUT(s, COND(op_conds[op])|CLASS(0x5)|/*disp */0);/* b*/
}
/* arm6_nop(s);*/
}
extern void
arm6_compare(dill_stream s, int op, int type, int dest, int src1, int src2)
{
int setcc = 0;
if (op == CMP) setcc = 1;
arm6_set(s, dest, 0);
switch(type) {
case DILL_D:
case DILL_F:
arm6_fproc2(s, 0b0100, (type == DILL_D), 0, src1, src2); /* fcmps */
INSN_OUT(s, COND(AL)|0b111011110001<<16|0b1111101000010000); /* fmstat */
INSN_OUT(s, COND(op_conds[op])|CLASS(0x0)|OPCODE(MOV)|S(setcc)|RN(src1)|RD(dest)|IMM(1, 0));
break;
case DILL_U: