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Verify CTS/RTS flow control
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Docs: add warnings:
- Create MIG on vivado or modify the design for the target FPGA/Software tool in ddr_memory_interface.sv
- Modify clocking wizard for the target FPGA/Software in system_clocking.sv
- Modify multiplier for the target latency or FPGA/Software in integer_multiplier.sv
- Modify multiplier for the target latency or FPGA/Software in float_multiplier.sv
- Modify the path of the boot memory in ZenithSoC.sv
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Verify FPU
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Build I2C device
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Integrate VGA
SPI add disable RX Add write strobe to Eth registers Change abs path to sine wave gen