diff --git a/security-monitor/src/core/architecture/riscv/sbi/covh_extension.rs b/security-monitor/src/core/architecture/riscv/sbi/covh_extension.rs
index 2c40fc3..6d4a008 100644
--- a/security-monitor/src/core/architecture/riscv/sbi/covh_extension.rs
+++ b/security-monitor/src/core/architecture/riscv/sbi/covh_extension.rs
@@ -65,6 +65,7 @@ impl TsmInfo {
     pub const COVE_TSM_STATE_LOADED: u32 = 1;
     pub const COVE_TSM_STATE_READY: u32 = 2;
     pub const COVE_TSM_IMPL_ACE: u32 = 2;
+    pub const COVE_TSM_CAP_PROMOTE_TVM: u64 = 1 << 0;
     pub const COVE_TSM_CAP_ATTESTATION_LOCAL_MASK: u64 = 1 << 1;
     pub const COVE_TSM_CAP_ATTESTATION_REMOTE_MASK: u64 = 1 << 2;
     pub const COVE_TSM_CAP_AIA_MASK: u64 = 1 << 3;
diff --git a/security-monitor/src/non_confidential_flow/handlers/cove_host_extension/get_security_monitor_info.rs b/security-monitor/src/non_confidential_flow/handlers/cove_host_extension/get_security_monitor_info.rs
index d057142..c8e92e5 100644
--- a/security-monitor/src/non_confidential_flow/handlers/cove_host_extension/get_security_monitor_info.rs
+++ b/security-monitor/src/non_confidential_flow/handlers/cove_host_extension/get_security_monitor_info.rs
@@ -41,7 +41,7 @@ impl GetSecurityMonitorInfo {
             tsm_state: TsmInfo::COVE_TSM_STATE_READY,
             tsm_impl_id: TsmInfo::COVE_TSM_IMPL_ACE,
             tsm_version: self.get_version(),
-            tsm_capabilities: TsmInfo::COVE_TSM_CAP_ATTESTATION_LOCAL_MASK,
+            tsm_capabilities: TsmInfo::COVE_TSM_CAP_PROMOTE_TVM | TsmInfo::COVE_TSM_CAP_ATTESTATION_LOCAL_MASK,
             state_pages: 0,
             max_vcpus: u64::try_from(ConfidentialVm::MAX_NUMBER_OF_HARTS_PER_VM).unwrap_or(0),
             vcpu_state_pages: 0,