Merge pull request #4 from Kev-J/add_err_i_sig

Martoni · web-flow · commit e1fa2e6dcc12 · 2024-12-12T08:25:42.000+01:00
Add wishbone error signals as options
diff --git a/.gitignore b/.gitignore
@@ -0,0 +1,4 @@
+project/
+target/
+
+**/*.swp
diff --git a/src/main/scala/wbplumbing/wbplumbing.scala b/src/main/scala/wbplumbing/wbplumbing.scala
@@ -8,35 +8,39 @@ import chisel3.experimental._
 // (no SEL, no TAG, no pipeline, ...)
 class WbMaster (val dwidth: Int,
                 val awidth: Int,
-                val iname: String = "Noname") extends Bundle {
+                val iname: String = "Noname",
+                val feature_err: Boolean = false) extends Bundle {
     val adr_o = Output(UInt(awidth.W))
     val dat_i = Input(UInt(dwidth.W))
     val dat_o = Output(UInt(dwidth.W))
     val we_o = Output(Bool())
     val stb_o = Output(Bool())
     val ack_i = Input(Bool())
     val cyc_o = Output(Bool())
+    val err_i = if (feature_err == true) Some(Input(Bool())) else None
 }
 
 // Wishbone slave interface
 class WbSlave (val dwidth: Int,
                val awidth: Int,
-               val iname: String = "Noname") extends Bundle {
+               val iname: String = "Noname",
+               val feature_err: Boolean = false) extends Bundle {
   val adr_i = Input(UInt(awidth.W))
   val dat_i = Input(UInt(dwidth.W))
   val dat_o = Output(UInt(dwidth.W))
   val we_i  = Input(Bool())
   val stb_i = Input(Bool())
   val ack_o = Output(Bool())
+  val err_o = if (feature_err == true) Some(Output(Bool())) else None
   val cyc_i = Input(Bool())
 }
 
 // Wishbone Intercon Pass Trought : one master, one slave
 class WbInterconPT (val awbm: WbMaster,
                     val awbs: WbSlave) extends Module {
   val io = IO(new Bundle{
-    val wbm = Flipped(new WbMaster(awbm.dwidth, awbm.awidth))
-    val wbs = Flipped(new WbSlave(awbs.dwidth, awbs.awidth))
+    val wbm = Flipped(new WbMaster(awbm.dwidth, awbm.awidth, awbm.iname, awbm.feature_err))
+    val wbs = Flipped(new WbSlave(awbs.dwidth, awbs.awidth, awbs.iname, awbs.feature_err))
   })
 
   assert(awbm.dwidth == awbs.dwidth,
@@ -54,21 +58,28 @@ class WbInterconPT (val awbm: WbMaster,
   io.wbm.ack_i := io.wbs.ack_o
   io.wbm.dat_i := io.wbs.dat_o
 
+  if (io.wbm.feature_err && io.wbs.feature_err) {
+    io.wbm.err_i.get := io.wbs.err_o.get
+  }
 }
 
 // Wishbone Intercon with one master and several slaves
 // data bus is same size as master
 class WbInterconOneMaster(val awbm: WbMaster,
-                          val awbs: Seq[WbSlave]) extends Module {
+                          val awbs: Seq[WbSlave]
+                          ) extends Module {
     val io = IO(new Bundle{
-      val wbm = Flipped(new WbMaster(awbm.dwidth, awbm.awidth))
-      val wbs = MixedVec(awbs.map{i => Flipped(new WbSlave(i.dwidth, i.awidth, i.iname))})
+      val wbm = Flipped(new WbMaster(awbm.dwidth, awbm.awidth, awbm.iname, awbm.feature_err))
+      val wbs = MixedVec(awbs.map{i => Flipped(new WbSlave(i.dwidth, i.awidth, i.iname, i.feature_err))})
     })
 
     var addrSlave = Seq(0)
 
     io.wbm.dat_i := 0.U
     io.wbm.ack_i := 0.U
+    if (io.wbm.feature_err) {
+      io.wbm.err_i.get := false.B
+    }
     val dataByteSize = awbm.dwidth/8
     for(wbs <- io.wbs) {
       val slaveInterfaceName = wbs.iname
@@ -94,6 +105,13 @@ class WbInterconOneMaster(val awbm: WbMaster,
           wbs.cyc_i := io.wbm.cyc_o
           io.wbm.dat_i := wbs.dat_o
           io.wbm.ack_i := wbs.ack_o
+          if (wbs.feature_err) {
+            io.wbm.err_i.get := wbs.err_o.get
+          }
+        }.otherwise {
+          if (io.wbm.feature_err) {
+            io.wbm.err_i.get := true.B
+          }
         }
       }
 
diff --git a/src/test/scala/wbplumbing/testwbplumbing.scala b/src/test/scala/wbplumbing/testwbplumbing.scala
@@ -3,7 +3,7 @@ package wbplumbing
 import chisel3._
 import chisel3.experimental.BundleLiterals._
 import chisel3.simulator.EphemeralSimulator._
-import org.scalatest.freespec.AnyFreeSpec
+import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.must.Matchers
 
 object general {
@@ -13,13 +13,15 @@ object general {
                   )
 }
 
-class WbInterconPTSpec extends AnyFreeSpec with Matchers {
+class WbInterconPTSpec extends AnyFlatSpec with Matchers {
 
-  "WbInterconPT should read and write wishbone value on one slave" in {
+  behavior of "WbInterconPT"
+
+  it should "read and write wishbone value on one slave" in {
     val args = general.optn
     val dataWidth = 16
-    val wbm = new WbMaster(dataWidth, 2)
-    val wbs = new WbSlave(dataWidth, 2)
+    val wbm = new WbMaster(dataWidth, 2, feature_err=true)
+    val wbs = new WbSlave(dataWidth, 2, feature_err=true)
 
     simulate(new WbInterconPT(wbm, wbs)){ dut =>
       // just a stupid testbench that verify point to point connexion
@@ -29,6 +31,7 @@ class WbInterconPTSpec extends AnyFreeSpec with Matchers {
       dut.io.wbm.stb_o.poke(true.B)
       dut.io.wbm.cyc_o.poke(true.B)
       dut.io.wbs.ack_o.poke(true.B)
+      dut.io.wbs.err_o.get.poke(true.B)
       dut.io.wbs.dat_o.poke(1.U)
       dut.clock.step(1)
       dut.io.wbm.adr_o.expect(1.U, "Wrong value read on wbm.adr_o")
@@ -37,13 +40,15 @@ class WbInterconPTSpec extends AnyFreeSpec with Matchers {
       dut.io.wbm.stb_o.expect(true.B, "Wrong value read on wbm.stb_o")
       dut.io.wbm.cyc_o.expect(true.B, "Wrong value read on wbm.cyc_o")
       dut.io.wbs.ack_o.expect(true.B, "Wrong value read on wbs.ack_o")
+      dut.io.wbs.err_o.get.expect(true.B, "Wrong value read on wbs.err_o")
       dut.io.wbs.dat_o.expect(1.U, "Wrong value read on wbs.dat_o")
       dut.io.wbm.adr_o.poke(0.U)
       dut.io.wbm.dat_o.poke(0.U)
       dut.io.wbm.we_o.poke(false.B)
       dut.io.wbm.stb_o.poke(false.B)
       dut.io.wbm.cyc_o.poke(false.B)
       dut.io.wbs.ack_o.poke(false.B)
+      dut.io.wbs.err_o.get.poke(false.B)
       dut.io.wbs.dat_o.poke(0.U)
       dut.clock.step(1)
       dut.io.wbm.adr_o.expect(0.U, "Wrong value read on wbm.adr_o")
@@ -52,14 +57,17 @@ class WbInterconPTSpec extends AnyFreeSpec with Matchers {
       dut.io.wbm.stb_o.expect(false.B, "Wrong value read on wbm.stb_o")
       dut.io.wbm.cyc_o.expect(false.B, "Wrong value read on wbm.cyc_o")
       dut.io.wbs.ack_o.expect(false.B, "Wrong value read on wbs.ack_o")
+      dut.io.wbs.err_o.get.expect(false.B, "Wrong value read on wbs.err_o")
       dut.io.wbs.dat_o.expect(0.U, "Wrong value read on wbs.dat_o")
     }
   }
 }
 
-class WbInterconOneMasterSpec extends AnyFreeSpec with Matchers {
+class WbInterconOneMasterSpec extends AnyFlatSpec with Matchers {
+
+  behavior of "WbInterconOneMaster"
 
-   "A WbInterconOneMaster should read and write wishbone value on two slaves" in {
+   it should "read and write wishbone value on two slaves" in {
     val args = general.optn
     val dataWidth = 16
     val wbm =  new WbMaster(dataWidth, 7, "Spi2WbMaster")
@@ -93,4 +101,80 @@ class WbInterconOneMasterSpec extends AnyFreeSpec with Matchers {
 
     }
   }
+
+  it should "raise the err_i line of the master if read address is unmapped" in {
+    val dataWidth = 16
+    val wbm =  new WbMaster(dataWidth, 3, "Spi2WbMaster", feature_err=true)
+    val wbs1 = new WbSlave(dataWidth, 2, "Ksz1")
+
+    simulate(new WbInterconOneMaster(wbm, Seq(wbs1))) { dut =>
+      dut.io.wbm.err_i.get.expect(false.B, "bad init of err_i")
+
+      // Read on unmapped address
+      dut.io.wbm.adr_o.poke(0x4)
+      dut.io.wbm.we_o.poke(false.B)
+      dut.io.wbm.cyc_o.poke(true.B)
+      dut.io.wbm.stb_o.poke(true.B)
+      dut.clock.step(1)
+      dut.io.wbm.err_i.get.expect(true.B, "err_i not raised")
+
+      // Stop transaction
+      dut.io.wbm.cyc_o.poke(false.B)
+      dut.io.wbm.stb_o.poke(false.B)
+      dut.clock.step(1)
+      dut.io.wbm.err_i.get.expect(false.B, "err_i not resetted correctly")
+    }
+  }
+
+  it should "raise the err_i line of the master if write address is unmapped" in {
+    val dataWidth = 16
+    val wbm =  new WbMaster(dataWidth, 3, "Spi2WbMaster", feature_err=true)
+    val wbs1 = new WbSlave(dataWidth, 2, "Ksz1")
+
+    simulate(new WbInterconOneMaster(wbm, Seq(wbs1))) { dut =>
+      dut.io.wbm.err_i.get.expect(false.B, "bad init of err_i")
+
+      // Write on unmapped address
+      dut.io.wbm.adr_o.poke(0x4)
+      dut.io.wbm.we_o.poke(true.B)
+      dut.io.wbm.cyc_o.poke(true.B)
+      dut.io.wbm.stb_o.poke(true.B)
+      dut.clock.step(1)
+      dut.io.wbm.err_i.get.expect(true.B, "err_i not raised")
+
+      // Stop transaction
+      dut.io.wbm.we_o.poke(false.B)
+      dut.io.wbm.cyc_o.poke(false.B)
+      dut.io.wbm.stb_o.poke(false.B)
+      dut.clock.step(1)
+      dut.io.wbm.err_i.get.expect(false.B, "err_i not resetted correctly")
+    }
+  }
+
+  it should "pass through the err_o line of the slave to the err_i line of the master" in {
+    val dataWidth = 16
+    val wbm =  new WbMaster(dataWidth, 3, "Spi2WbMaster", feature_err=true)
+    val wbs1 = new WbSlave(dataWidth, 2, "Ksz1", feature_err=true)
+
+    simulate(new WbInterconOneMaster(wbm, Seq(wbs1))) { dut =>
+      dut.io.wbm.err_i.get.expect(false.B, "bad init of err_i")
+
+      // Write on unmapped address
+      dut.io.wbm.adr_o.poke(0x0)
+      dut.io.wbm.we_o.poke(false.B)
+      dut.io.wbm.cyc_o.poke(true.B)
+      dut.io.wbm.stb_o.poke(true.B)
+      dut.clock.step(1)
+      dut.io.wbs(0).err_o.get.poke(true.B)
+      dut.io.wbm.err_i.get.expect(true.B, "err_i not raised")
+
+      // Reset err_o
+      dut.io.wbm.we_o.poke(false.B)
+      dut.io.wbm.cyc_o.poke(false.B)
+      dut.io.wbm.stb_o.poke(false.B)
+      dut.io.wbs(0).err_o.get.poke(false.B)
+      dut.clock.step(1)
+      dut.io.wbm.err_i.get.expect(false.B, "err_i not resetted correctly")
+    }
+  }
 }
