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sstv_merged.cov
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:::::::::::::::::::::::::::::::::::::::::::::::::::
:: ::
:: Covered -- Verilog Coverage Detailed Report ::
:: ::
:::::::::::::::::::::::::::::::::::::::::::::::::::
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ GENERAL INFORMATION ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Report generated from CDD file : sstv_merged.cdd
* Reported by : Module
* Report generated from CDD file that was merged from the following files:
Filename Leading Hierarchy
-----------------------------------------------------------------------------------------------------------------
sstv_cal.cdd sstv_cal_tb
sstv.cdd sstv_tb
sstv_pixel.cdd sstv_pixel_tb
sstv_vis.cdd sstv_vis_tb
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ LINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Module/Task/Function Filename Hit/ Miss/Total Percent hit
---------------------------------------------------------------------------------------------------------------------
$root NA 0/ 0/ 0 100%
sstv_cal sstv_cal.v 42/ 4/ 46 91%
sstv_pixel sstv_pixel.v 10/ 0/ 10 100%
sstv_vis sstv_vis.v 59/ 2/ 61 97%
assert_never assert_never.vlib 7/ 1/ 8 88%
assert_never.ovl_err std_ovl_task.h 0/ 12/ 12 0%
assert_never.ovl_fin std_ovl_task.h 0/ 0/ 0 100%
assert_never.ovl_ini std_ovl_task.h 0/ 0/ 0 100%
assert_never.ovl_cov std_ovl_task.h 0/ 2/ 2 0%
assert_never.ovl_fir std_ovl_task.h 0/ 4/ 4 0%
assert_never.ovl_fir std_ovl_task.h 0/ 4/ 4 0%
assert_never.ovl_fir std_ovl_task.h 0/ 4/ 4 0%
---------------------------------------------------------------------------------------------------------------------
Accumulated 118/ 33/ 151 78%
---------------------------------------------------------------------------------------------------------------------
Module: sstv_cal, File: sstv_cal.v
-------------------------------------------------------------------------------------------------------------
Missed Lines
79: next_cal_state = SSTV_CAL_IDLE
94: next_cal_state = SSTV_CAL_IDLE
96: next_cal_state = SSTV_CAL_IDLE
166: cal_ok <= 0
Module: sstv_vis, File: sstv_vis.v
-------------------------------------------------------------------------------------------------------------
Missed Lines
87: next_vis_state = SSTV_VIS_IDLE
106: next_vis_state = SSTV_VIS_END
Module: assert_never, File: std_ovl/assert_never.vlib
-------------------------------------------------------------------------------------------------------------
Missed Lines
57: fire_xcheck_1 = 1'b1
Task: assert_never.ovl_error_t, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Missed Lines
21: err_typ = "OVL_FATAL"
22: err_typ = "OVL_ERROR"
23: err_typ = "OVL_WARNING"
24: err_typ = "OVL_INFO"
27: err_typ = "OVL_ERROR"
39: error_count = error_count + 1
43: if( xcheck == 0 )
45: error_count = error_count + 1
57: if( severity_level == 0 )
61: ovl_finish_t
65: if( xcheck == 0 )
66: ovl_finish_t
Task: assert_never.ovl_cover_t, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Missed Lines
122: cover_count = cover_count + 1
126: if( coverage_level > 15 )
Function: assert_never.ovl_fire_2state_f, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Missed Lines
163: ovl_fire_2state_f = 1'b1
165: ovl_fire_2state_f = 1'b1
166: ovl_fire_2state_f = 1'b0
167: ovl_fire_2state_f = 1'b0
Function: assert_never.ovl_fire_xcheck_f, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Missed Lines
183: ovl_fire_xcheck_f = 1'b1
185: ovl_fire_xcheck_f = 1'b0
186: ovl_fire_xcheck_f = 1'b0
187: ovl_fire_xcheck_f = 1'b0
Function: assert_never.ovl_fire_cover_f, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Missed Lines
197: ovl_fire_cover_f = 1'b0
203: ovl_fire_cover_f = 1'b1
204: ovl_fire_cover_f = 1'b0
205: ovl_fire_cover_f = 1'b0
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TOGGLE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Toggle 0 -> 1 Toggle 1 -> 0
Module/Task/Function Filename Hit/ Miss/Total Percent hit Hit/ Miss/Total Percent hit
---------------------------------------------------------------------------------------------------------------------
$root NA 0/ 0/ 0 100% 0/ 0/ 0 100%
sstv_cal sstv_cal.v 40/ 17/ 57 70% 40/ 17/ 57 70%
sstv_pixel sstv_pixel.v 14/ 1/ 15 93% 14/ 1/ 15 93%
sstv_vis sstv_vis.v 54/ 24/ 78 69% 53/ 25/ 78 68%
assert_never assert_never.vlib 4/ 66/ 70 6% 4/ 66/ 70 6%
assert_never.ovl_err std_ovl_task.h 0/ 1153/ 1153 0% 0/ 1153/ 1153 0%
assert_never.ovl_fin std_ovl_task.h 0/ 0/ 0 100% 0/ 0/ 0 100%
assert_never.ovl_ini std_ovl_task.h 0/ 0/ 0 100% 0/ 0/ 0 100%
assert_never.ovl_cov std_ovl_task.h 0/ 1024/ 1024 0% 0/ 1024/ 1024 0%
assert_never.ovl_fir std_ovl_task.h 0/ 33/ 33 0% 0/ 33/ 33 0%
assert_never.ovl_fir std_ovl_task.h 0/ 33/ 33 0% 0/ 33/ 33 0%
assert_never.ovl_fir std_ovl_task.h 0/ 33/ 33 0% 0/ 33/ 33 0%
---------------------------------------------------------------------------------------------------------------------
Accumulated 112/ 2384/ 2496 4% 111/ 2385/ 2496 4%
---------------------------------------------------------------------------------------------------------------------
Module: sstv_cal, File: sstv_cal.v
-------------------------------------------------------------------------------------------------------------
Signals not getting 100% toggle coverage
Signal Toggle
---------------------------------------------------------------------------------------------------------
cal_counter 0->1: 32'h0000_7fff
......................... 1->0: 32'h0000_7fff ...
Module: sstv_pixel, File: sstv_pixel.v
-------------------------------------------------------------------------------------------------------------
Signals not getting 100% toggle coverage
Signal Toggle
---------------------------------------------------------------------------------------------------------
reset 0->1: 1'h0
......................... 1->0: 1'h1 ...
freq 0->1: 12'hfff
......................... 1->0: 12'h7ff ...
Module: sstv_vis, File: sstv_vis.v
-------------------------------------------------------------------------------------------------------------
Signals not getting 100% toggle coverage
Signal Toggle
---------------------------------------------------------------------------------------------------------
freq 0->1: 12'h5fc
......................... 1->0: 12'h1fc ...
delay_counter 0->1: 32'h0000_0fff
......................... 1->0: 32'h0000_0fff ...
Module: assert_never, File: std_ovl/assert_never.vlib
-------------------------------------------------------------------------------------------------------------
Signals not getting 100% toggle coverage
Signal Toggle
---------------------------------------------------------------------------------------------------------
error_count 0->1: 32'h0000_0000
......................... 1->0: 32'h0000_0000 ...
cover_count 0->1: 32'h0000_0000
......................... 1->0: 32'h0000_0000 ...
fire_xcheck_1 0->1: 1'h0
......................... 1->0: 1'h0 ...
valid_test_expr 0->1: 1'h0
......................... 1->0: 1'h0 ...
Task: assert_never.ovl_error_t, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Signals not getting 100% toggle coverage
Signal Toggle
---------------------------------------------------------------------------------------------------------
xcheck 0->1: 1'h0
......................... 1->0: 1'h0 ...
err_msg 0->1: 1024'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000
......................... 1->0: 1024'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ...
err_typ 0->1: 128'h0000_0000_0000_0000_0000_0000_0000_0000
......................... 1->0: 128'h0000_0000_0000_0000_0000_0000_0000_0000 ...
Task: assert_never.ovl_cover_t, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Signals not getting 100% toggle coverage
Signal Toggle
---------------------------------------------------------------------------------------------------------
cvr_msg 0->1: 1024'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000
......................... 1->0: 1024'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ...
Function: assert_never.ovl_fire_2state_f, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Signals not getting 100% toggle coverage
Signal Toggle
---------------------------------------------------------------------------------------------------------
ovl_fire_2state_f 0->1: 1'h0
......................... 1->0: 1'h0 ...
property_type 0->1: 32'h0000_0000
......................... 1->0: 32'h0000_0000 ...
Function: assert_never.ovl_fire_xcheck_f, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Signals not getting 100% toggle coverage
Signal Toggle
---------------------------------------------------------------------------------------------------------
ovl_fire_xcheck_f 0->1: 1'h0
......................... 1->0: 1'h0 ...
property_type 0->1: 32'h0000_0000
......................... 1->0: 32'h0000_0000 ...
Function: assert_never.ovl_fire_cover_f, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Signals not getting 100% toggle coverage
Signal Toggle
---------------------------------------------------------------------------------------------------------
ovl_fire_cover_f 0->1: 1'h0
......................... 1->0: 1'h0 ...
coverage_level 0->1: 32'h0000_0000
......................... 1->0: 32'h0000_0000 ...
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ COMBINATIONAL LOGIC COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Logic Combinations
Module/Task/Function Filename Hit/Miss/Total Percent hit
---------------------------------------------------------------------------------------------------------------------
$root NA 0/ 0/ 0 100%
sstv_cal sstv_cal.v 38/ 10/ 48 79%
sstv_pixel sstv_pixel.v 24/ 0/ 24 100%
sstv_vis sstv_vis.v 72/ 10/ 82 88%
assert_never assert_never.vlib 7/ 4/ 11 64%
assert_never.ovl_error_t std_ovl_task.h 0/ 8/ 8 0%
assert_never.ovl_finish_t std_ovl_task.h 0/ 0/ 0 100%
assert_never.ovl_init_msg_t std_ovl_task.h 0/ 0/ 0 100%
assert_never.ovl_cover_t std_ovl_task.h 0/ 2/ 2 0%
assert_never.ovl_fire_2state_f std_ovl_task.h 0/ 0/ 0 100%
assert_never.ovl_fire_xcheck_f std_ovl_task.h 0/ 0/ 0 100%
assert_never.ovl_fire_cover_f std_ovl_task.h 0/ 0/ 0 100%
---------------------------------------------------------------------------------------------------------------------
Accumulated 141/ 34/ 175 81%
---------------------------------------------------------------------------------------------------------------------
Module: sstv_cal, File: sstv_cal.v
-------------------------------------------------------------------------------------------------------------
Missed Combinations (* = missed value)
=========================================================================================================
Line # Expression
=========================================================================================================
48: cal_state <= next_cal_state
|-----1------|
Expression 1 (1/2)
^^^^^^^^^^^^^ -
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
57: case( cal_state )
|---1---|
SSTV_CAL_IDLE :
Expression 1 (1/2)
^^^^^^^^^^^^^ -
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
76: if( cal_counter >= CLK_TICKS_300MS )
|-------------1--------------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - >=
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
88: if( FREQ_1900HZ == freq )
|--------1--------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - ==
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
91: if( cal_counter >= CLK_TICKS_10MS )
|-------------1-------------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - >=
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
126: case( cal_state )
|---1---|
SSTV_CAL_IDLE :
Expression 1 (1/2)
^^^^^^^^^^^^^ -
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
139: cal_counter <= cal_counter + 1
|------1------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - +
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
149: cal_counter <= cal_counter + 1
|------1------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - +
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
161: cal_counter <= cal_counter + 1
|------1------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - +
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
163: if( cal_counter >= CLK_TICKS_300MS )
|-------------1--------------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - >=
E | E
=0=|=1=
*
Module: sstv_vis, File: sstv_vis.v
-------------------------------------------------------------------------------------------------------------
Missed Combinations (* = missed value)
=========================================================================================================
Line # Expression
=========================================================================================================
64: vis_state <= next_vis_state
|-----1------|
Expression 1 (1/2)
^^^^^^^^^^^^^ -
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
75: case( vis_state )
|---1---|
SSTV_VIS_IDLE :
Expression 1 (1/2)
^^^^^^^^^^^^^ -
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
85: if( ((CLK_TICKS_30MS / 2) == delay_counter) &&
|--------------------2----------------------
(FREQ_1200HZ != freq) )
|---------1---------|
----------2---------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - !=
E | E
=0=|=1=
*
Expression 2 (2/3)
^^^^^^^^^^^^^ - &&
LR | LR | LR
=0-=|=-0=|=11=
*
=========================================================================================================
Line # Expression
=========================================================================================================
104: if( (bit_num == SSTV_VIS_LENGTH) &&
|---------------1----------------
(CLK_TICKS_30MS == delay_counter) )
----------------1---------------|
Expression 1 (2/3)
^^^^^^^^^^^^^ - &&
LR | LR | LR
=0-=|=-0=|=11=
*
=========================================================================================================
Line # Expression
=========================================================================================================
145: case( vis_state )
|---1---|
SSTV_VIS_IDLE :
Expression 1 (1/2)
^^^^^^^^^^^^^ -
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
156: delay_counter <= delay_counter + 32'b1
|---------1---------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - +
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
165: delay_counter <= delay_counter + 32'b1
|---------1---------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - +
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
168: bit_num <= bit_num + 1
|----1----|
Expression 1 (1/2)
^^^^^^^^^^^^^ - +
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
183: delay_counter <= delay_counter + 32'b1
|---------1---------|
Expression 1 (1/2)
^^^^^^^^^^^^^ - +
E | E
=0=|=1=
*
Module: assert_never, File: std_ovl/assert_never.vlib
-------------------------------------------------------------------------------------------------------------
Missed Combinations (* = missed value)
=========================================================================================================
Line # Expression
=========================================================================================================
50: valid_test_expr = ((test_expr ^ test_expr) == 1'b0)
|----------1----------|
|---------------2---------------|
Expression 1 (2/4)
^^^^^^^^^^^^^ - ^
LR | LR | LR | LR
=00=|=01=|=10=|=11=
* *
Expression 2 (1/2)
^^^^^^^^^^^^^ - ==
E | E
=0=|=1=
*
=========================================================================================================
Line # Expression
=========================================================================================================
53: if( valid_test_expr )
|------1------|
Expression 1 (1/2)
^^^^^^^^^^^^^ -
E | E
=0=|=1=
*
Task: assert_never.ovl_error_t, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Missed Combinations (* = missed value)
=========================================================================================================
Line # Expression
=========================================================================================================
39: error_count = error_count + 1
|------1------|
Expression 1 (0/2)
^^^^^^^^^^^^^ - +
E | E
=0=|=1=
* *
=========================================================================================================
Line # Expression
=========================================================================================================
43: if( xcheck == 0 )
|----1----|
Expression 1 (0/2)
^^^^^^^^^^^^^ - ==
E | E
=0=|=1=
* *
=========================================================================================================
Line # Expression
=========================================================================================================
45: error_count = error_count + 1
|------1------|
Expression 1 (0/2)
^^^^^^^^^^^^^ - +
E | E
=0=|=1=
* *
=========================================================================================================
Line # Expression
=========================================================================================================
65: if( xcheck == 0 )
|----1----|
Expression 1 (0/2)
^^^^^^^^^^^^^ - ==
E | E
=0=|=1=
* *
Task: assert_never.ovl_cover_t, File: std_ovl/std_ovl_task.h
-------------------------------------------------------------------------------------------------------------
Missed Combinations (* = missed value)
=========================================================================================================
Line # Expression
=========================================================================================================
122: cover_count = cover_count + 1
|------1------|
Expression 1 (0/2)
^^^^^^^^^^^^^ - +
E | E
=0=|=1=
* *
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ FINITE STATE MACHINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
State Arc
Module/Task/Function Filename Hit/Miss/Total Percent Hit Hit/Miss/Total Percent hit
---------------------------------------------------------------------------------------------------------------------
$root NA 0/ 0/ 0 100% 0/ 0/ 0 100%
sstv_cal sstv_cal.v 0/ 0/ 0 100% 0/ 0/ 0 100%
sstv_pixel sstv_pixel.v 0/ 0/ 0 100% 0/ 0/ 0 100%
sstv_vis sstv_vis.v 0/ 0/ 0 100% 0/ 0/ 0 100%
assert_never assert_never.vlib 0/ 0/ 0 100% 0/ 0/ 0 100%
assert_never.ovl_err std_ovl_task.h 0/ 0/ 0 100% 0/ 0/ 0 100%
assert_never.ovl_fin std_ovl_task.h 0/ 0/ 0 100% 0/ 0/ 0 100%
assert_never.ovl_ini std_ovl_task.h 0/ 0/ 0 100% 0/ 0/ 0 100%
assert_never.ovl_cov std_ovl_task.h 0/ 0/ 0 100% 0/ 0/ 0 100%
assert_never.ovl_fir std_ovl_task.h 0/ 0/ 0 100% 0/ 0/ 0 100%
assert_never.ovl_fir std_ovl_task.h 0/ 0/ 0 100% 0/ 0/ 0 100%
assert_never.ovl_fir std_ovl_task.h 0/ 0/ 0 100% 0/ 0/ 0 100%
---------------------------------------------------------------------------------------------------------------------
Accumulated 0/ 0/ 0 100% 0/ 0/ 0 100%