diff --git a/patch/kernel/archive/sunxi-6.6/drv-phy-realtek-revert-faulty-patch.patch b/patch/kernel/archive/sunxi-6.6/drv-phy-realtek-revert-faulty-patch.patch
new file mode 100644
index 000000000000..414ec51cebfc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.6/drv-phy-realtek-revert-faulty-patch.patch
@@ -0,0 +1,75 @@
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index 95dbe5e8e1d8ff..0f09609718007e 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -1,5 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0+
++/*
++ * drivers/net/phy/realtek.c
+-/* drivers/net/phy/realtek.c
+  *
+  * Driver for Realtek PHYs
+  *
+@@ -31,9 +32,9 @@
+ #define RTL8211F_TX_DELAY			BIT(8)
+ #define RTL8211F_RX_DELAY			BIT(3)
+ 
++#define RTL8211E_TX_DELAY			BIT(1)
++#define RTL8211E_RX_DELAY			BIT(2)
++#define RTL8211E_MODE_MII_GMII			BIT(3)
+-#define RTL8211E_CTRL_DELAY			BIT(13)
+-#define RTL8211E_TX_DELAY			BIT(12)
+-#define RTL8211E_RX_DELAY			BIT(11)
+ 
+ #define RTL8201F_ISR				0x1e
+ #define RTL8201F_IER				0x13
+@@ -245,16 +246,16 @@ static int rtl8211e_config_init(struct phy_device *phydev)
+ 	/* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
+ 	switch (phydev->interface) {
+ 	case PHY_INTERFACE_MODE_RGMII:
++		val = 0;
+-		val = RTL8211E_CTRL_DELAY | 0;
+ 		break;
+ 	case PHY_INTERFACE_MODE_RGMII_ID:
++		val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
+-		val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
+ 		break;
+ 	case PHY_INTERFACE_MODE_RGMII_RXID:
++		val = RTL8211E_RX_DELAY;
+-		val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
+ 		break;
+ 	case PHY_INTERFACE_MODE_RGMII_TXID:
++		val = RTL8211E_TX_DELAY;
+-		val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
+ 		break;
+ 	default: /* the rest of the modes imply leaving delays as is. */
+ 		return 0;
+@@ -262,12 +263,11 @@ static int rtl8211e_config_init(struct phy_device *phydev)
+ 
+ 	/* According to a sample driver there is a 0x1c config register on the
+ 	 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
++	 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can
++	 * also be used to customize the whole configuration register:
++	 * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select,
++	 * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet
++	 * for details).
+-	 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
+-	 * The configuration register definition:
+-	 * 14 = reserved
+-	 * 13 = Force Tx RX Delay controlled by bit12 bit11,
+-	 * 12 = RX Delay, 11 = TX Delay
+-	 * 10:0 = Test && debug settings reserved by realtek
+ 	 */
+ 	oldpage = phy_select_page(phydev, 0x7);
+ 	if (oldpage < 0)
+@@ -277,8 +277,7 @@ static int rtl8211e_config_init(struct phy_device *phydev)
+ 	if (ret)
+ 		goto err_restore_page;
+ 
++	ret = __phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
+-	ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
+-			   | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
+ 			   val);
+ 
+ err_restore_page:
+ 
\ No newline at end of file