From 2ce11cb71d382dda2680e5301e74765e67b970c3 Mon Sep 17 00:00:00 2001 From: Leonardo Benedette Lopes Date: Wed, 4 May 2016 15:20:49 -0300 Subject: [PATCH] Update fallthrough_small_fifo_v2.v Fix the name of the module fallthrough_small_fifo_v2.v in declaration. --- lib/verilog/core/utils/src/fallthrough_small_fifo_v2.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/verilog/core/utils/src/fallthrough_small_fifo_v2.v b/lib/verilog/core/utils/src/fallthrough_small_fifo_v2.v index 6812e911..1b71d888 100644 --- a/lib/verilog/core/utils/src/fallthrough_small_fifo_v2.v +++ b/lib/verilog/core/utils/src/fallthrough_small_fifo_v2.v @@ -1,7 +1,7 @@ /////////////////////////////////////////////////////////////////////////////// // $Id: small_fifo.v 1998 2007-07-21 01:22:57Z grg $ // -// Module: fallthrough_small_fifo.v +// Module: fallthrough_small_fifo_v2.v // Project: utils // Description: small fifo with fallthrough i.e. data valid when rd is high // @@ -12,7 +12,7 @@ /////////////////////////////////////////////////////////////////////////////// `timescale 1ns/1ps - module fallthrough_small_fifo + module fallthrough_small_fifo_v2 #(parameter WIDTH = 72, parameter MAX_DEPTH_BITS = 3, parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1)