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Merge branch 'beta_0.x_revisao_shift' into beta_0.x
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Ver detalhes no Issue #39
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@carlosdelfino
carlosdelfino committed Apr 14, 2021
2 parents f4ecac4 + e9c68e6 commit 8fcd025
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Showing 5 changed files with 43 additions and 35 deletions.
4 changes: 1 addition & 3 deletions .gitignore
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Expand Up @@ -10,11 +10,9 @@ teste.cpp
main.cpp
CMakeLists.txt
docs
.gitkwaverc
.gtkwaverc
vsim.wlf

vish_stacktrace.vstf
vsim.wlf
tcl_stacktrace.txt

*.bck
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9 changes: 4 additions & 5 deletions InstructionDecoder.v
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Expand Up @@ -2,7 +2,7 @@ module IntegerBasicInstructionDecoder (
input [31:0] instr,
output [15:0] op_code,

output jump, branch, load_pc,
output branch, load_pc,

output alu_sel,

Expand Down Expand Up @@ -121,12 +121,12 @@ assign rs1_sel = TYPE_I ||
assign rs2_sel = TYPE_B || TYPE_S || TYPE_R ? instr[24:20] :
5'bx;

assign imm_rs2_sel = TYPE_I || TYPE_S || TYPE_B || TYPE_U;
assign imm_rs2_sel = TYPE_J || TYPE_I || TYPE_S || TYPE_B || TYPE_U;

// Indica se ativa ou não a ALU
// quais instruções fazem uso da ALU?
// apenas ativa se for uma das instruções que usam a ALU, as demais ignora
assign alu_sel = TYPE_B || AUIPC ||
assign alu_sel = TYPE_J || AUIPC || TYPE_B ||
ADDI || ADD ||
SLTI || SLTIU || SLT ||
LBU || LHU ||
Expand Down Expand Up @@ -174,8 +174,7 @@ assign data_r = TYPE_IL;

assign unsigned_value = LBU || LHU || SLTIU; // no caso LBU e LHU fn3 tem o bit 2 igual a 1

assign jump = TYPE_J;
assign branch = TYPE_B;
assign load_pc = AUIPC;
assign load_pc = TYPE_J || AUIPC;

endmodule
11 changes: 6 additions & 5 deletions IntegerBasicALU.v
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@@ -1,10 +1,10 @@
module IntegerBasicALU #(
parameter DATA_WIDTH = 32
)(
input E,
input [15:0] alu_op,
input [DATA_WIDTH-1:0] A, B,
output [DATA_WIDTH-1:0] out
input E,
input [15:0] alu_op,
input signed [DATA_WIDTH-1:0] A, B,
output signed [DATA_WIDTH-1:0] out
);

localparam TYPE_IL = 7'b0000011;
Expand Down Expand Up @@ -61,6 +61,7 @@ localparam OR = {7'b0000000, 3'b110, TYPE_R }; // b0000-0110-0011-0011
localparam AND = {7'b0000000, 3'b111, TYPE_R }; // b0000-0111-0011-0011 h0733

assign out = !E ? {DATA_WIDTH{1'b0}} :
alu_op == JAL ||
alu_op == BEQ ||
alu_op == BNE ||
alu_op == BLT ||
Expand Down Expand Up @@ -88,7 +89,7 @@ assign out = !E ? {DATA_WIDTH{1'b0}} :
alu_op == SRL ? $signed(A) >> $signed(B) :

alu_op == SRAI ||
alu_op == SRA ? $signed(A) >>> $signed(B) :
alu_op == SRA ? $signed($signed(A) >>> B) :

alu_op == SLTIU ? A < B :

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8 changes: 4 additions & 4 deletions RISCuin.v
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Expand Up @@ -24,7 +24,7 @@ wire [1:0] bus_size;

wire local_rst = rst | ~rb_ready;

wire jump, branch, load_pc;
wire branch, load_pc;

wire reg_w;
wire [4:0] rd_sel, rs1_sel, rs2_sel;
Expand Down Expand Up @@ -52,7 +52,7 @@ initial begin
end

wire [31:0] alu_A = branch || load_pc ? {pc,2'b0} : rs1_data;
wire [31:0] alu_B = imm_rs2_sel ? imm : rs2_data;
wire [31:0] alu_B = imm_rs2_sel ? imm : rs2_data;

wire do_branch = branch ?
op_code == BEQ ? rs1_data == rs2_data :
Expand All @@ -62,7 +62,7 @@ wire do_branch = branch ?
op_code == BLTU ? rs1_data < rs2_data :
op_code == BGEU ? rs1_data > rs2_data :
1'b0:
jump;
load_pc;
// 00 -> alu
// 01 -> bus (data_eei é o dado processado do barramento)
// 10 -> imm
Expand Down Expand Up @@ -119,7 +119,7 @@ ProgramMemory #(.INSTR_ADDR_WIDTH(`INSTR_ADDR_WIDTH))
Decodificador de instruções RV32I básico.
*/
IntegerBasicInstructionDecoder ib_id(.instr(instr), .op_code(op_code),
.alu_sel(alu_sel), .jump(jump), .branch(branch), .load_pc(load_pc),
.alu_sel(alu_sel), .branch(branch), .load_pc(load_pc),
.rs1_sel(rs1_sel), .rs2_sel(rs2_sel), .rd_sel(rd_sel),
.rd_data_sel(rd_data_sel),
.reg_w(reg_w),
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46 changes: 28 additions & 18 deletions prog_32.hex
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@@ -1,24 +1,34 @@
//============================
//Post-assembly program listing
//PC instruction basic assembly original assembly Notes
// (31:0) code code
//00 0x00300093 addi x1 x0 3 addi x1, x0, 3 # x1 = x0 + 3 = 3 rs1 = x0 (always 0) + imm offset = 3
//04 0xffb08113 addi x2 x1 -5 addi x2, x1, -5 # x2 = x1 - 5 = 3 + 0xfffffffb (-5 sign-extended to 32-bits) = //-2 (0xfffffffe)
//08 0x00100613 addi x12 x0 1 addi x12, x0, 1 # x12 = 1
//0c 0x00c00693 addi x13 x0 12 addi x13, x0, 12 # x13 = 12
//10 0x01f00713 addi x14 x0 31 addi x14, x0, 31 # x14 = 31
//14 0x01c00793 addi x15 x0 28 addi x15, x0, 28 # x15 = 28
//18 0x00300813 addi x16 x0 3 addi x16, x0, 3 # x16 = 3
//1c 0x01e00893 addi x17 x0 30 addi x17, x0, 30 # x17 = 30
//20 0x00c091b3 sll x3 x1 x12 sll x3, x1, x12 # x3 = 0b110 shift 0b11 logical left 1 bit
//24 0x00d11233 sll x4 x2 x13 sll x4, x2, x13 # x4 = 0xffffe000 shift 0xfffffffe logical left 12 bits
//28 0x00e092b3 sll x5 x1 x14 sll x5, x1, x14 # x5 = 0x80000000 shift 0b11 logical left 31 bits. Bit 1 drops //off to left
//2c 0x00c0d333 srl x6 x1 x12 srl x6, x1, x12 # x6 = 0b1 shift 0b11 logical right 1 bit
//30 0x00c153b3 srl x7 x2 x12 srl x7, x2, x12 # x7 = 0x7fffffff, shifts 0 into bit 31. Shifts (31:1) to (30:0)//. Bit 0 drops off to right
//34 0x00f15433 srl x8 x2 x15 srl x8, x2, x15 # x8 = 0x0000000f, shifts 0s into bits (31:4). Shifts (31:28) //to (3:0). Bits (27:0) drop off to right
//38 0x40c2d4b3 sra x9 x5 x12 sra x9, x5, x12 # x9 = 0xc0000000, shift 1 into bit 31. Shift bits (31:1) to //(30:0). Bit 0 drops off to right
//3c 0x4102d533 sra x10 x5 x16 sra x10, x5, x16 # x10 = 0xf0000000, shifts 1s into bits (31:29). Shifts //(28:3) to (25:0). Bits (2:0) drop off to right
//40 0x4112d5b3 sra x11 x5 x17 sra x11, x5, x17 # x11 = 0xfffffffe, shifts 1s into bits (31:2). Shifts //(31:30) to (1:0). Bits (29:0) drop off to right
//44 0x0000006f jal x0 0 1b: jal zero,1b # repeat the NOP instruction, recommended rather than 1b: beq //x0,x0,1b
//
//# https://www.kvakil.me/venus/
//# Video tutorial: https://www.vicilogic.com/vicilearn/run_step/?s_id=1452
//
//# assembly program # Notes  (default imm format is decimal 0d)
//main:
//addi x12, x0, -1 # x12 = 0xffffffff
//auipc x11, 0x7ffff # x11 = 0x7ffff004 (since current PC = 4)
//nop
//nop
//nop
//nop
//sw x12, 0x8(x11) # store x12 in MEM(x11 + 8) = MEM(0x7ffff00c)
//

// 0 1 2 3
// 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
fff00613 7ffff597 00c5a423 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00300093 ffb08113 00100613 00c00693
01f00713 01c00793 00300813 01e00893
00c091b3 00d11233 00e092b3 00c0d333
00c153b3 00f15433 40c2d4b3 4102d533
4112d5b3 0000006f 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000

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