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This repository was archived by the owner on Feb 25, 2025. It is now read-only.

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Modifying README.md to note the move of the repository to the
github Efabless account.
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README.md

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# Analog IP design example: 8-bit Resistive ladder DAC ![](../../workflows/cace/badge.svg)
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## Important note:
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This project has been moved to [github/efabless](https://github.com/efabless/sky130_ef_ip__rdac3v_8bit). This local repository has been archived, and continued development will be done under the Efabless github location.
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This is a simple 8-bit DAC demonstrating the use
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of the CACE system. It requires [CACE](https://github.com/efabless/cace) to run the testbenches.
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First, the environment is set up and CACE is started. Then the `run/` directory is uploaded so that it can be viewed later. Finally, the summary is added to the step overview.
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Take a look at the latest runs under [actions](https://github.com/RTimothyEdwards/sky130_ef_ip__rdac3v_8bit/actions). If you are logged in to GitHub, you can also click on a run and view the summary.
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Take a look at the latest runs under [actions](https://github.com/RTimothyEdwards/sky130_ef_ip__rdac3v_8bit/actions). If you are logged in to GitHub, you can also click on a run and view the summary.

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