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Commit b9a018c

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Rename to full name
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lef/dac_3v_8bit.lef renamed to lef/sky130_ef_ip__rdac3v_8bit.lef

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@ VERSION 5.7 ;
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NOWIREEXTENSIONATPIN ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
5-
MACRO dac_3v_8bit
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MACRO sky130_ef_ip__rdac3v_8bit
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CLASS BLOCK ;
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FOREIGN dac_3v_8bit ;
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FOREIGN sky130_ef_ip__rdac3v_8bit ;
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ORIGIN 0.000 0.000 ;
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SIZE 129.695 BY 121.595 ;
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PIN b0
@@ -159,6 +159,6 @@ MACRO dac_3v_8bit
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LAYER met5 ;
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RECT 38.415 8.850 114.635 70.550 ;
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END
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END dac_3v_8bit
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END sky130_ef_ip__rdac3v_8bit
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END LIBRARY
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verilog/dac_3v_8bit.v renamed to verilog/sky130_ef_ip__rdac3v_8bit.v

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -26,14 +26,13 @@
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/*--------------------------------------------------------------*/
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`default_nettype none
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`timescale 1 ns / 1 ps
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module sample_and_hold #(parameter FUNCTIONAL = 1)(
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module sky130_ef_ip__rdac3v_8bit #(parameter FUNCTIONAL = 1)(
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`ifdef USE_POWER_PINS
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input vdd,
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input vss,
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input dvdd,
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input dvss,
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inout vdd,
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inout vss,
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inout dvdd,
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inout dvss,
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`endif
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input real Vlow,
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input real Vhigh,

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