nvsim.cfg

//-DesignTarget: cache
-DesignTarget: RAM
//-DesignTarget: CAM

-CacheAccessMode: Normal
//-CacheAccessMode: Fast
//-CacheAccessMode: Sequential

//-OptimizationTarget: ReadLatency
//-OptimizationTarget: WriteLatency
//-OptimizationTarget: ReadDynamicEnergy
//-OptimizationTarget: WriteDynamicEnergy
//-OptimizationTarget: ReadEDP
//-OptimizationTarget: WriteEDP
//-OptimizationTarget: LeakagePower
//-OptimizationTarget: Area
//-OptimizationTarget: Exploration

//-OutputFilePrefix: sram

-EnablePruning: Yes

//-ProcessNode: 200
//-ProcessNode: 120
//-ProcessNode: 90
//-ProcessNode: 65
//-ProcessNode: 45
-ProcessNode: 32
//-ProcessNode: 22

-Capacity (KB): 128
//-Capacity (MB): 16
-WordWidth (bit): 512
//-Associativity (for cache only): 4

-DeviceRoadmap: HP
//-DeviceRoadmap: LSTP
//-DeviceRoadmap: LOP

-LocalWireType: LocalAggressive
//-LocalWireType: LocalConservative
//-LocalWireType: SemiAggressive
//-LocalWireType: SemiConservative
//-LocalWireType: GlobalAggressive
//-LocalWireType: GlobalConservative
-LocalWireRepeaterType: RepeatedNone
//-LocalWireRepeaterType: RepeatedOpt
//-LocalWireRepeaterType: Repeated5%Penalty
//-LocalWireRepeaterType: Repeated10%Penalty
//-LocalWireRepeaterType: Repeated20%Penalty
//-LocalWireRepeaterType: Repeated30%Penalty
//-LocalWireRepeaterType: Repeated40%Penalty
//-LocalWireRepeaterType: Repeated50%Penalty

//-LocalWireUseLowSwing: Yes
-LocalWireUseLowSwing: No

//-GlobalWireType: LocalAggressive
//-GlobalWireType: LocalConservative
//-GlobalWireType: SemiAggressive
//-GlobalWireType: SemiConservative
-GlobalWireType: GlobalAggressive
//-GlobalWireType: GlobalConservative
-GlobalWireRepeaterType: RepeatedNone
//-GlobalWireRepeaterType: RepeatedOpt
//-GlobalWireRepeaterType: Repeated5%Penalty
//-GlobalWireRepeaterType: Repeated10%Penalty
//-GlobalWireRepeaterType: Repeated20%Penalty
//-GlobalWireRepeaterType: Repeated30%Penalty
//-GlobalWireRepeaterType: Repeated40%Penalty
//-GlobalWireRepeaterType: Repeated50%Penalty

//-GlobalWireUseLowSwing: Yes
-GlobalWireUseLowSwing: No

-Routing: H-tree
//-Routing: non-H-tree

-InternalSensing: true
//-InternalSensing: false

//-MaxNmosSize (F): 150

-MemoryCellInputFile: SRAM.cell
//-MemoryCellInputFile: sample_SLCNAND.cell
//-MemoryCellInputFile: sample_RRAM.cell
//-MemoryCellInputFile: sample_STTRAM.cell
//-MemoryCellInputFile: sample_PCRAM.cell

-Temperature (K): 350

-BufferDesignOptimization: latency
//-BufferDesignOptimization: area
//-BufferDesignOptimization: balance

-ForceBank (Total AxB, Active CxD): 4x4, 1x4
-ForceMat (Total AxB, Active CxD): 2x2, 1x2
-ForceMuxSenseAmp: 2
-ForceMuxOutputLev1: 1
-ForceMuxOutputLev2: 1
//-UseCactiAssumption: Yes

//-ApplyReadLatencyConstraint: 37.4
//-ApplyWriteLatencyConstraint: 0.5
//-ApplyReadDynamicEnergyConstraint: 0.5
//-ApplyWriteDynamicEnergyConstraint: 0.5
//-ApplyLeakageConstraint: 0.5
//-ApplyAreaConstraint: 1
//-ApplyReadEdpConstraint: 0.5
//-ApplyWriteEdpConstraint: 0.5