From e4ed1e0af33de1917f09154a8c406285a413fb20 Mon Sep 17 00:00:00 2001 From: GiHub Action Bot Date: Mon, 19 Aug 2024 09:12:49 +0000 Subject: [PATCH] update .pot files --- .../gettext/SpinalHDL/Data types/Int.pot | 4 +- .../gettext/SpinalHDL/Data types/Vec.pot | 6 +- .../gettext/SpinalHDL/Data types/bool.pot | 4 +- .../gettext/SpinalHDL/Data types/index.pot | 4 +- .../Developers area/spinalhdl_datamodel.pot | 6 +- .../SpinalHDL/Developers area/types.pot | 4 +- .../Examples/Advanced ones/slots.pot | 6 +- .../Examples/Advanced ones/timer.pot | 6 +- .../Examples/Intermediates ones/vga.pot | 6 +- .../gettext/SpinalHDL/Foreword/index.pot | 4 +- .../SpinalHDL/Formal verification/index.pot | 8 +- .../Getting Started/Install and setup.pot | 4 +- .../Introduction/Projects using SpinalHDL.pot | 4 +- .../Legacy/pinsec/hardware_toplevel.pot | 4 +- .../SpinalHDL/Legacy/pinsec/introduction.pot | 4 +- .../locale/gettext/SpinalHDL/Legacy/riscv.pot | 4 +- .../Libraries/Bus/amba3/ahblite3.pot | 4 +- .../SpinalHDL/Libraries/Bus/amba3/apb3.pot | 4 +- .../SpinalHDL/Libraries/Bus/amba4/axi4.pot | 4 +- .../Libraries/Bus/avalon/avalonmm.pot | 4 +- .../Libraries/Bus/tilelink/tilelink.pot | 6 +- .../Bus/tilelink/tilelink_fabric.pot | 10 +- .../SpinalHDL/Libraries/Com/usb_device.pot | 22 +- .../SpinalHDL/Libraries/Com/usb_ohci.pot | 8 +- .../Libraries/EDA/altera/qsysify.pot | 4 +- .../Libraries/Misc/PLIC/plic_mapper.pot | 8 +- .../Libraries/Misc/service_plugin.pot | 12 +- .../Libraries/Pipeline/introduction.pot | 28 +- .../gettext/SpinalHDL/Libraries/fiber.pot | 6 +- .../gettext/SpinalHDL/Libraries/flow.pot | 4 +- .../gettext/SpinalHDL/Libraries/fsm.pot | 6 +- .../gettext/SpinalHDL/Libraries/index.pot | 4 +- .../gettext/SpinalHDL/Libraries/regIf.pot | 16 +- .../gettext/SpinalHDL/Libraries/stream.pot | 10 +- .../gettext/SpinalHDL/Libraries/utils.pot | 9 +- .../scope_property.pot | 4 +- .../Other language features/stub.pot | 4 +- .../SpinalHDL/Semantic/assignments.pot | 6 +- .../gettext/SpinalHDL/Semantic/rules.pot | 6 +- .../SpinalHDL/Simulation/bootstraps.pot | 4 +- .../gettext/SpinalHDL/Simulation/clock.pot | 14 +- .../Simulation/install/Icarus Verilog.pot | 4 +- .../SpinalHDL/Simulation/install/VCS.pot | 4 +- .../Simulation/install/Verilator.pot | 4 +- .../SpinalHDL/Structuring/clock_domain.pot | 6 +- .../Structuring/components_hierarchy.pot | 4 +- .../gettext/SpinalHDL/Structuring/index.pot | 4 +- .../gettext/SpinalHDL/Structuring/naming.pot | 16 +- .../SpinalHDL/Structuring/parametrization.pot | 8 +- .../miscelenea/core/core_components.pot | 12 +- .../SpinalHDL/miscelenea/frequent_errors.pot | 8 +- .../LC_MESSAGES/SpinalHDL/Data types/Int.po | 7 +- .../LC_MESSAGES/SpinalHDL/Data types/Vec.po | 37 +- .../LC_MESSAGES/SpinalHDL/Data types/bool.po | 186 ++++---- .../LC_MESSAGES/SpinalHDL/Data types/index.po | 37 +- .../Developers area/spinalhdl_datamodel.po | 194 +++++---- .../SpinalHDL/Developers area/types.po | 155 ++++--- .../SpinalHDL/Examples/Advanced ones/slots.po | 90 ++-- .../SpinalHDL/Examples/Advanced ones/timer.po | 247 ++++++----- .../Examples/Intermediates ones/vga.po | 33 +- .../LC_MESSAGES/SpinalHDL/Foreword/index.po | 214 +++++----- .../SpinalHDL/Formal verification/index.po | 134 +++--- .../Getting Started/Install and setup.po | 62 ++- .../Introduction/Projects using SpinalHDL.po | 81 ++-- .../Legacy/pinsec/hardware_toplevel.po | 128 +++--- .../SpinalHDL/Legacy/pinsec/introduction.po | 63 +-- .../LC_MESSAGES/SpinalHDL/Legacy/riscv.po | 66 +-- .../SpinalHDL/Libraries/Bus/amba3/ahblite3.po | 83 ++-- .../SpinalHDL/Libraries/Bus/amba3/apb3.po | 50 +-- .../SpinalHDL/Libraries/Bus/amba4/axi4.po | 54 +-- .../Libraries/Bus/avalon/avalonmm.po | 69 +-- .../Libraries/Bus/tilelink/tilelink.po | 46 +- .../Libraries/Bus/tilelink/tilelink_fabric.po | 135 +++--- .../SpinalHDL/Libraries/Com/usb_device.po | 199 ++++----- .../SpinalHDL/Libraries/Com/usb_ohci.po | 72 ++-- .../SpinalHDL/Libraries/EDA/altera/qsysify.po | 61 +-- .../Libraries/Misc/PLIC/plic_mapper.po | 102 ++--- .../Libraries/Misc/service_plugin.po | 134 +++--- .../Libraries/Pipeline/introduction.po | 399 ++++++++---------- .../LC_MESSAGES/SpinalHDL/Libraries/fiber.po | 115 +++-- .../LC_MESSAGES/SpinalHDL/Libraries/flow.po | 34 +- .../LC_MESSAGES/SpinalHDL/Libraries/fsm.po | 165 ++++---- .../LC_MESSAGES/SpinalHDL/Libraries/index.po | 47 ++- .../LC_MESSAGES/SpinalHDL/Libraries/regIf.po | 56 +-- .../LC_MESSAGES/SpinalHDL/Libraries/stream.po | 43 +- .../LC_MESSAGES/SpinalHDL/Libraries/utils.po | 50 +-- .../Other language features/scope_property.po | 57 +-- .../SpinalHDL/Other language features/stub.po | 35 +- .../SpinalHDL/Semantic/assignments.po | 211 +++++---- .../LC_MESSAGES/SpinalHDL/Semantic/rules.po | 148 ++++--- .../SpinalHDL/Simulation/bootstraps.po | 44 +- .../Simulation/install/Icarus Verilog.po | 66 +-- .../SpinalHDL/Simulation/install/VCS.po | 85 ++-- .../SpinalHDL/Simulation/install/Verilator.po | 111 +++-- .../SpinalHDL/Structuring/clock_domain.po | 42 +- .../Structuring/components_hierarchy.po | 7 +- .../SpinalHDL/Structuring/index.po | 35 +- .../SpinalHDL/Structuring/naming.po | 150 +++---- .../SpinalHDL/Structuring/parametrization.po | 179 ++++---- .../miscelenea/core/core_components.po | 203 ++++----- .../SpinalHDL/miscelenea/frequent_errors.po | 88 ++-- 101 files changed, 2716 insertions(+), 2748 deletions(-) diff --git a/source/locale/gettext/SpinalHDL/Data types/Int.pot b/source/locale/gettext/SpinalHDL/Data types/Int.pot index 5f2d7f70169..b83b662b367 100644 --- a/source/locale/gettext/SpinalHDL/Data types/Int.pot +++ b/source/locale/gettext/SpinalHDL/Data types/Int.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-07-20 14:42+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -353,7 +353,7 @@ msgid "Set all bits to the given Bool value" msgstr "" #: ../../SpinalHDL/Data types/Int.rst:142 -msgid "Notice the difference in behaviour between ``x >> 2`` (result 2 bit narrower than x) and ``x >> U(2)`` (keeping width) due to the Scala type of :code:`y`." +msgid "Notice the difference in behavior between ``x >> 2`` (result 2 bit narrower than x) and ``x >> U(2)`` (keeping width) due to the Scala type of :code:`y`." msgstr "" #: ../../SpinalHDL/Data types/Int.rst:145 diff --git a/source/locale/gettext/SpinalHDL/Data types/Vec.pot b/source/locale/gettext/SpinalHDL/Data types/Vec.pot index 34930422340..2194a75a33d 100644 --- a/source/locale/gettext/SpinalHDL/Data types/Vec.pot +++ b/source/locale/gettext/SpinalHDL/Data types/Vec.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-02-13 17:23+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -167,7 +167,7 @@ msgid "x.sCount(condition: T => Bool)" msgstr "" #: ../../SpinalHDL/Data types/Vec.rst:150 -msgid "Count the number of occurence matching a given condition in the Vec." +msgid "Count the number of occurrence matching a given condition in the Vec." msgstr "" #: ../../SpinalHDL/Data types/Vec.rst:151 @@ -180,7 +180,7 @@ msgid "x.sCount(value: T)" msgstr "" #: ../../SpinalHDL/Data types/Vec.rst:153 -msgid "Count the number of occurence of a value in the Vec." +msgid "Count the number of occurrence of a value in the Vec." msgstr "" #: ../../SpinalHDL/Data types/Vec.rst:155 diff --git a/source/locale/gettext/SpinalHDL/Data types/bool.pot b/source/locale/gettext/SpinalHDL/Data types/bool.pot index e2663ca7620..b1ba8ae7c96 100644 --- a/source/locale/gettext/SpinalHDL/Data types/bool.pot +++ b/source/locale/gettext/SpinalHDL/Data types/bool.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -57,7 +57,7 @@ msgid "The ``Bool`` type corresponds to a boolean value (True or False) or a sin msgstr "" #: ../../SpinalHDL/Data types/bool.rst:14 -msgid "An important concept and rule-of-thumb to understand is that the Scala `Boolean` type is used in places where elaboration-time HDL code-generation decision making is occuring in Scala code. Like any regular program it affects execution of the Scala program that is SpinalHDL at the time the program is being run to perform HDL code generation." +msgid "An important concept and rule-of-thumb to understand is that the Scala `Boolean` type is used in places where elaboration-time HDL code-generation decision making is occurring in Scala code. Like any regular program it affects execution of the Scala program that is SpinalHDL at the time the program is being run to perform HDL code generation." msgstr "" #: ../../SpinalHDL/Data types/bool.rst:20 diff --git a/source/locale/gettext/SpinalHDL/Data types/index.pot b/source/locale/gettext/SpinalHDL/Data types/index.pot index 0121efbf261..7378b12ac68 100644 --- a/source/locale/gettext/SpinalHDL/Data types/index.pot +++ b/source/locale/gettext/SpinalHDL/Data types/index.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-26 16:21+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -49,7 +49,7 @@ msgid ":ref:`Floating-point ` numbers (experimental support)" msgstr "" #: ../../SpinalHDL/Data types/index.rst:22 -msgid "Additionaly, if you want to assign a don't care value to some hardware, for instance, to provide a default value, you can use the assignDontCare API to do so." +msgid "Additionally, if you want to assign a don't care value to some hardware, for instance, to provide a default value, you can use the assignDontCare API to do so." msgstr "" #: ../../SpinalHDL/Data types/index.rst:31 diff --git a/source/locale/gettext/SpinalHDL/Developers area/spinalhdl_datamodel.pot b/source/locale/gettext/SpinalHDL/Developers area/spinalhdl_datamodel.pot index 70788c52252..fc16fc42f06 100644 --- a/source/locale/gettext/SpinalHDL/Developers area/spinalhdl_datamodel.pot +++ b/source/locale/gettext/SpinalHDL/Developers area/spinalhdl_datamodel.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -81,7 +81,7 @@ msgid "There are also utilities like *myExpression.remapExpressions(Expression = msgstr "" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:44 -msgid "More generaly, most of the graph checks and transformations done by SpinalHDL are located in " +msgid "More generally, most of the graph checks and transformations done by SpinalHDL are located in " msgstr "" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:47 @@ -133,7 +133,7 @@ msgid "mySignal.removeAssignments : Will remove all previous `:=` affecting the msgstr "" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:157 -msgid "mySignal.removeStatement : Will void the existance of the signal" +msgid "mySignal.removeStatement : Will void the existence of the signal" msgstr "" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:158 diff --git a/source/locale/gettext/SpinalHDL/Developers area/types.pot b/source/locale/gettext/SpinalHDL/Developers area/types.pot index b0dbb3c4eef..8238f3564cb 100644 --- a/source/locale/gettext/SpinalHDL/Developers area/types.pot +++ b/source/locale/gettext/SpinalHDL/Developers area/types.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -955,7 +955,7 @@ msgid "Then you can also incorporate a Bundle inside Bundle as deeply as you wan msgstr "" #: ../../SpinalHDL/Developers area/types.rst:494 -msgid "And finaly instantiate your Bundles inside the hardware :" +msgid "And finally instantiate your Bundles inside the hardware :" msgstr "" #: ../../SpinalHDL/Developers area/types.rst:504 diff --git a/source/locale/gettext/SpinalHDL/Examples/Advanced ones/slots.pot b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/slots.pot index fffd21cc8b9..25fad26b3c6 100644 --- a/source/locale/gettext/SpinalHDL/Examples/Advanced ones/slots.pot +++ b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/slots.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -37,7 +37,7 @@ msgid "This implementation avoid the use of Vec. Instead, it use Area which allo msgstr "" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:17 -msgid "Note that the `reader` API is for SpinalHDL version comming after 1.9.1" +msgid "Note that the `reader` API is for SpinalHDL version coming after 1.9.1" msgstr "" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:24 @@ -53,7 +53,7 @@ msgid "https://github.com/SpinalHDL/SpinalHDL/blob/008c73f1ce18e294f137efe7a1442 msgstr "" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:30 -msgid "As well in the DRAM / SDR / DDR memory controller to implement the handeling of multiple memory transactions at once (having multiple precharge / active / read / write running at the same time to improve performances) :" +msgid "As well in the DRAM / SDR / DDR memory controller to implement the handling of multiple memory transactions at once (having multiple precharge / active / read / write running at the same time to improve performances) :" msgstr "" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:32 diff --git a/source/locale/gettext/SpinalHDL/Examples/Advanced ones/timer.pot b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/timer.pot index 4ded58d7a91..a03ca5a1c7e 100644 --- a/source/locale/gettext/SpinalHDL/Examples/Advanced ones/timer.pot +++ b/source/locale/gettext/SpinalHDL/Examples/Advanced ones/timer.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -268,7 +268,7 @@ msgid "0" msgstr "" #: ../../SpinalHDL/Examples/Advanced ones/timer.rst:126 -msgid "Each ``ticks`` bool can be actived if the corresponding ``ticksEnable`` bit is high." +msgid "Each ``ticks`` bool can be activated if the corresponding ``ticksEnable`` bit is high." msgstr "" #: ../../SpinalHDL/Examples/Advanced ones/timer.rst:127 @@ -284,7 +284,7 @@ msgid "16" msgstr "" #: ../../SpinalHDL/Examples/Advanced ones/timer.rst:132 -msgid "Each ``clears`` bool can be actived if the corresponding ``clearsEnable`` bit is high." +msgid "Each ``clears`` bool can be activated if the corresponding ``clearsEnable`` bit is high." msgstr "" #: ../../SpinalHDL/Examples/Advanced ones/timer.rst:136 diff --git a/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/vga.pot b/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/vga.pot index 4556ebeb570..d6d68b64cdc 100644 --- a/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/vga.pot +++ b/source/locale/gettext/SpinalHDL/Examples/Intermediates ones/vga.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -225,11 +225,11 @@ msgid "Horizontal and vertical logic" msgstr "" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:148 -msgid "The logic that generates horizontal and vertical synchronization signals is quite the same. It kind of resembles ~PWM~. The horizontal one counts up each cycle, while the vertical one use the horizontal syncronization signal as to increment." +msgid "The logic that generates horizontal and vertical synchronization signals is quite the same. It kind of resembles ~PWM~. The horizontal one counts up each cycle, while the vertical one use the horizontal synchronization signal as to increment." msgstr "" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:150 -msgid "Let's define ``HVArea``\\ , which represents one ~PWM~ and then instantiate it two times: one for both horizontal and vertical syncronization." +msgid "Let's define ``HVArea``\\ , which represents one ~PWM~ and then instantiate it two times: one for both horizontal and vertical synchronization." msgstr "" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:160 diff --git a/source/locale/gettext/SpinalHDL/Foreword/index.pot b/source/locale/gettext/SpinalHDL/Foreword/index.pot index 3a663fc820b..0ecacb98694 100644 --- a/source/locale/gettext/SpinalHDL/Foreword/index.pot +++ b/source/locale/gettext/SpinalHDL/Foreword/index.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -33,7 +33,7 @@ msgid "For conciseness, let's assume that SystemVerilog is a recent revision of msgstr "" #: ../../SpinalHDL/Foreword/index.rst:12 -msgid "When reading this, we should not underestimate how much our attachment for our favourite HDL will bias our judgement." +msgid "When reading this, we should not underestimate how much our attachment for our favorite HDL will bias our judgement." msgstr "" #: ../../SpinalHDL/Foreword/index.rst:17 diff --git a/source/locale/gettext/SpinalHDL/Formal verification/index.pot b/source/locale/gettext/SpinalHDL/Formal verification/index.pot index fd5c57033ab..a5bb5b68f04 100644 --- a/source/locale/gettext/SpinalHDL/Formal verification/index.pot +++ b/source/locale/gettext/SpinalHDL/Formal verification/index.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -145,7 +145,7 @@ msgid "Specifying the initial value of a signal" msgstr "" #: ../../SpinalHDL/Formal verification/index.rst:226 -msgid "For instance, for the reset signal of the current clockdomain (usefull at the top)" +msgid "For instance, for the reset signal of the current clockdomain (useful at the top)" msgstr "" #: ../../SpinalHDL/Formal verification/index.rst:233 @@ -271,7 +271,7 @@ msgid "``pastValidAfterReset()``" msgstr "" #: ../../SpinalHDL/Formal verification/index.rst:309 -msgid "Simliar to ``pastValid``, where only difference is that this would take reset into account. Can be understood as ``pastValid & past(!reset)``." +msgid "Similar to ``pastValid``, where only difference is that this would take reset into account. Can be understood as ``pastValid & past(!reset)``." msgstr "" #: ../../SpinalHDL/Formal verification/index.rst:311 @@ -307,5 +307,5 @@ msgid "For interfaces implement IMasterSlave" msgstr "" #: ../../SpinalHDL/Formal verification/index.rst:337 -msgid "There could be functions in name ``formalAssertsMaster``, ``formalAssertsSlave``, ``formalAssumesMaster``, ``formalAssumesSlave`` or ``formalCovers``. Master/Slave are target interface type, so that ``formalAssertsMaster`` can be understand as \"formal verfication assertions for master interface\"." +msgid "There could be functions in name ``formalAssertsMaster``, ``formalAssertsSlave``, ``formalAssumesMaster``, ``formalAssumesSlave`` or ``formalCovers``. Master/Slave are target interface type, so that ``formalAssertsMaster`` can be understand as \"formal verification assertions for master interface\"." msgstr "" diff --git a/source/locale/gettext/SpinalHDL/Getting Started/Install and setup.pot b/source/locale/gettext/SpinalHDL/Getting Started/Install and setup.pot index c905d13fa77..380f80e9e08 100644 --- a/source/locale/gettext/SpinalHDL/Getting Started/Install and setup.pot +++ b/source/locale/gettext/SpinalHDL/Getting Started/Install and setup.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-04-19 10:29+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -117,7 +117,7 @@ msgid "Go to the oss-cad-suite `release page /environment``." +msgid "To use oss-cad-suite in a shell you need to load it's environment, e.g. via ``source /environment``." msgstr "" #: ../../SpinalHDL/Getting Started/Install and setup.rst:87 diff --git a/source/locale/gettext/SpinalHDL/Introduction/Projects using SpinalHDL.pot b/source/locale/gettext/SpinalHDL/Introduction/Projects using SpinalHDL.pot index 47baccfcf69..ea4c0152d4f 100644 --- a/source/locale/gettext/SpinalHDL/Introduction/Projects using SpinalHDL.pot +++ b/source/locale/gettext/SpinalHDL/Introduction/Projects using SpinalHDL.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -21,7 +21,7 @@ msgid "Projects using SpinalHDL" msgstr "" #: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:4 -msgid "Note that the following lists are very incompletes." +msgid "Note that the following lists are very incomplete." msgstr "" #: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:9 diff --git a/source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot b/source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot index ef4eef3fa4a..509ade8d4c8 100644 --- a/source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot +++ b/source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -319,7 +319,7 @@ msgid "This bridge will be used to connect low bandwidth peripherals to the AXI msgstr "" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:411 -msgid "The AXI4 crossbar that interconnect AXI4 masters and slaves together is generated by using an factory. The concept of this factory is to create it, then call many function on it to configure it, and finaly call the ``build`` function to ask the factory to generate the corresponding hardware :" +msgid "The AXI4 crossbar that interconnect AXI4 masters and slaves together is generated by using an factory. The concept of this factory is to create it, then call many function on it to configure it, and finally call the ``build`` function to ask the factory to generate the corresponding hardware :" msgstr "" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:421 diff --git a/source/locale/gettext/SpinalHDL/Legacy/pinsec/introduction.pot b/source/locale/gettext/SpinalHDL/Legacy/pinsec/introduction.pot index 5c6e43f8c78..a336067204c 100644 --- a/source/locale/gettext/SpinalHDL/Legacy/pinsec/introduction.pot +++ b/source/locale/gettext/SpinalHDL/Legacy/pinsec/introduction.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -22,7 +22,7 @@ msgid "Introduction" msgstr "" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:10 -msgid "This page only documents the SoC implemented with the first generation of RISC-V CPU created in SpinalHDL. This page does not document the VexRiscV CPU, which is the second generation of this SoC (and CPU) is available `here `__ and offers better perforance/area/features." +msgid "This page only documents the SoC implemented with the first generation of RISC-V CPU created in SpinalHDL. This page does not document the VexRiscV CPU, which is the second generation of this SoC (and CPU) is available `here `__ and offers better performance/area/features." msgstr "" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:17 diff --git a/source/locale/gettext/SpinalHDL/Legacy/riscv.pot b/source/locale/gettext/SpinalHDL/Legacy/riscv.pot index c14cd2ca0e1..5ec723c177f 100644 --- a/source/locale/gettext/SpinalHDL/Legacy/riscv.pot +++ b/source/locale/gettext/SpinalHDL/Legacy/riscv.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -157,7 +157,7 @@ msgid "Documentation" msgstr "" #: ../../SpinalHDL/Legacy/riscv.rst:80 -msgid "Optimise instruction/data caches FMax by moving line hit condition forward into combinatorial paths." +msgid "Optimize instruction/data caches FMax by moving line hit condition forward into combinatorial paths." msgstr "" #: ../../SpinalHDL/Legacy/riscv.rst:82 diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/ahblite3.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/ahblite3.pot index 348220f4bc5..042e49a4da0 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/ahblite3.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/ahblite3.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -21,7 +21,7 @@ msgid "AHB-Lite3" msgstr "" #: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:6 -msgid "Configuration and instanciation" +msgid "Configuration and instantiation" msgstr "" #: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:8 diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/apb3.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/apb3.pot index e994607388a..375a9c00709 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/apb3.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/apb3.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -25,7 +25,7 @@ msgid "The AMBA3-APB bus is commonly used to interface low bandwidth peripherals msgstr "" #: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:8 -msgid "Configuration and instanciation" +msgid "Configuration and instantiation" msgstr "" #: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:10 diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/amba4/axi4.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba4/axi4.pot index 1bdc04de4d3..bf8132d96b6 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Bus/amba4/axi4.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/amba4/axi4.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -25,7 +25,7 @@ msgid "The AXI4 is a high bandwidth bus defined by ARM." msgstr "" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:7 -msgid "Configuration and instanciation" +msgid "Configuration and instantiation" msgstr "" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:9 diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/avalon/avalonmm.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/avalon/avalonmm.pot index f88023131c7..ae2b95ed7fd 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Bus/avalon/avalonmm.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/avalon/avalonmm.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -37,7 +37,7 @@ msgid "Less performance than AXI but use much less area (Read and write command msgstr "" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:12 -msgid "Configuration and instanciation" +msgid "Configuration and instantiation" msgstr "" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:14 diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink.pot index ce2f14f4571..3ea89baa2de 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -21,7 +21,7 @@ msgid "Tilelink" msgstr "" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:6 -msgid "Configuration and instanciation" +msgid "Configuration and instantiation" msgstr "" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:8 @@ -33,5 +33,5 @@ msgid "Here is the same as above, but with coherency channels" msgstr "" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:43 -msgid "Those above where for the hardware instanciation, the thing is that it is the simple / easy part. When things goes into SoC / memory coherency, you kind of need an additional layer to negociate / propagate parameters all around. That's what tilelink.fabric.Node is about." +msgid "Those above where for the hardware instantiation, the thing is that it is the simple / easy part. When things goes into SoC / memory coherency, you kind of need an additional layer to negotiate / propagate parameters all around. That's what tilelink.fabric.Node is about." msgstr "" diff --git a/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.pot b/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.pot index 8d4bfb8a9ab..35cd1f319be 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -21,11 +21,11 @@ msgid "tilelink.fabric.Node" msgstr "" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:5 -msgid "tilelink.fabric.Node is an additional layer over the regular tilelink hardware instanciation which handle negociation and parameters propagation at a SoC level." +msgid "tilelink.fabric.Node is an additional layer over the regular tilelink hardware instantiation which handle negotiation and parameters propagation at a SoC level." msgstr "" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:7 -msgid "It is mostly based on the Fiber API, which allows to create elaboration time fibers (user-space threads), allowing to schedule future parameter propagation / negociation and hardware elaboration." +msgid "It is mostly based on the Fiber API, which allows to create elaboration time fibers (user-space threads), allowing to schedule future parameter propagation / negotiation and hardware elaboration." msgstr "" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:9 @@ -69,7 +69,7 @@ msgid "You can note that they all are Handles. Handle is a way in SpinalHDL to h msgstr "" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:24 -msgid "There is also a set of attribues like m2s, but reversed (named s2m) which specify the parameters for the transactions initiated by the slave side of the interconnect (ex memory coherency)." +msgid "There is also a set of attributes like m2s, but reversed (named s2m) which specify the parameters for the transactions initiated by the slave side of the interconnect (ex memory coherency)." msgstr "" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:26 @@ -145,7 +145,7 @@ msgid "\"OT\" means OffsetTransformer(offset)" msgstr "" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:240 -msgid "Note that you can also add PMA (Physical Memory Attributes) to nodes and retreives them via this getMemoryTransfers utilities." +msgid "Note that you can also add PMA (Physical Memory Attributes) to nodes and retrieves them via this getMemoryTransfers utilities." msgstr "" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:242 diff --git a/source/locale/gettext/SpinalHDL/Libraries/Com/usb_device.pot b/source/locale/gettext/SpinalHDL/Libraries/Com/usb_device.pot index 4fa7916d43e..c0473338c82 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Com/usb_device.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Com/usb_device.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -25,7 +25,7 @@ msgid "Here exists a USB device controller in the SpinalHDL library." msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:7 -msgid "A few bullet points to summarise support:" +msgid "A few bullet points to summarize support:" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:9 @@ -37,11 +37,11 @@ msgid "A internal ram which store the endpoints states and transactions descript msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:11 -msgid "Up to 16 endpoints (for virtualy no price)" +msgid "Up to 16 endpoints (for virtually no price)" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:12 -msgid "Support USB host full speed (12Mbps)" +msgid "Support USB host full speed (12 Mbps)" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:13 @@ -49,7 +49,7 @@ msgid "Test on linux using its own driver (https://github.com/SpinalHDL/linux/bl msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:14 -msgid "Bmb memory interace for the configuration" +msgid "Bmb memory interface for the configuration" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:15 @@ -222,7 +222,7 @@ msgid "6-0" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:68 -msgid "The device will only listen at tokens with the specified address This field is automaticaly cleared on usb reset events" +msgid "The device will only listen at tokens with the specified address This field is automatically cleared on usb reset events" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:71 @@ -248,11 +248,11 @@ msgid "9" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:73 -msgid "Set the enable (see above) on the next EP0 IN tocken completion Cleared by the hardware after any EP0 completion" +msgid "Set the enable (see above) on the next EP0 IN token completion Cleared by the hardware after any EP0 completion" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:77 -msgid "The idea here is to keep the whole register cleared until a USB SET_ADDRESS setup packet is received on EP0. At that moment, you can set the address and the trigger field, then provide the IN zero length descriptor to EP0 to finalise the SET_ADDRESS sequance. The controller will then automaticaly turn on the address filtering at the completion of that descriptor." +msgid "The idea here is to keep the whole register cleared until a USB SET_ADDRESS setup packet is received on EP0. At that moment, you can set the address and the trigger field, then provide the IN zero length descriptor to EP0 to finalize the SET_ADDRESS sequence. The controller will then automatically turn on the address filtering at the completion of that descriptor." msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:82 @@ -471,7 +471,7 @@ msgid "ENDPOINTS (0x0000 - 0x003F)" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:147 -msgid "The endpoints status are stored at the begining of the internal ram over one 32 bits word each." +msgid "The endpoints status are stored at the beginning of the internal ram over one 32 bits word each." msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:152 @@ -485,7 +485,7 @@ msgid "RW" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:152 -msgid "If not set, the endpoint will ignore all the trafic" +msgid "If not set, the endpoint will ignore all the traffic" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:154 @@ -654,7 +654,7 @@ msgid "Note, if the controller receives a frame where the IN/OUT does not match msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:220 -msgid "Also, to initialise a descriptor, the CPU should set the code field to 0xF" +msgid "Also, to initialize a descriptor, the CPU should set the code field to 0xF" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:223 diff --git a/source/locale/gettext/SpinalHDL/Libraries/Com/usb_ohci.pot b/source/locale/gettext/SpinalHDL/Libraries/Com/usb_ohci.pot index 68e329026df..be9f97f7afd 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Com/usb_ohci.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Com/usb_ohci.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -25,7 +25,7 @@ msgid "Here exists a USB OHCi controller (host) in the SpinalHDL library." msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:7 -msgid "A few bullet points to summarise support:" +msgid "A few bullet points to summarize support:" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:9 @@ -37,7 +37,7 @@ msgid "It is compatible with the upstream linux / uboot OHCI drivers already. (t msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:11 -msgid "This provides USB host full speed and low speed capabilities (12Mbps and 1.5Mbps)" +msgid "This provides USB host full speed and low speed capabilities (12 Mbps and 1.5 Mbps)" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:12 @@ -53,7 +53,7 @@ msgid "Bmb memory interface for DMA accesses" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:15 -msgid "Bmb memory interace for the configuration" +msgid "Bmb memory interface for the configuration" msgstr "" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:16 diff --git a/source/locale/gettext/SpinalHDL/Libraries/EDA/altera/qsysify.pot b/source/locale/gettext/SpinalHDL/Libraries/EDA/altera/qsysify.pot index ab0357ab5f5..c664cfd3381 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/EDA/altera/qsysify.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/EDA/altera/qsysify.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -21,7 +21,7 @@ msgid "QSysify" msgstr "" #: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:5 -msgid "QSysify is a tool which is able to generate a QSys IP (tcl script) from a SpinalHDL component by analysing its IO definition. It currently implement the following interfaces features :" +msgid "QSysify is a tool which is able to generate a QSys IP (tcl script) from a SpinalHDL component by analyzing its IO definition. It currently implement the following interfaces features :" msgstr "" #: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:7 diff --git a/source/locale/gettext/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.pot b/source/locale/gettext/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.pot index 34156f1642e..c8ba72f661f 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -77,15 +77,15 @@ msgid "This mapping generates a lighter PLIC, at the cost of some missing option msgstr "" #: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:36 -msgid "no reading the intrerrupt's priority" +msgid "not reading the interrupt's priority" msgstr "" #: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:37 -msgid "no reading the interrupts's pending bit (must use the claim/complete mechanism)" +msgid "not reading the interrupt's pending bit (must use the claim/complete mechanism)" msgstr "" #: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:38 -msgid "no reading the target's threshold" +msgid "not reading the target's threshold" msgstr "" #: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:40 diff --git a/source/locale/gettext/SpinalHDL/Libraries/Misc/service_plugin.pot b/source/locale/gettext/SpinalHDL/Libraries/Misc/service_plugin.pot index fc9582d3dae..2a15336a842 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Misc/service_plugin.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Misc/service_plugin.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-22 03:53+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -37,7 +37,7 @@ msgid "You can swap various implementations of the same functionality just by us msgstr "" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:15 -msgid "It avoid the very very very large hand written toplevel syndrom where everything has to be connected manualy. Instead plugins can discover their neighborhood by looking/using the software interface of other plugins." +msgid "It avoid the very very very large hand written toplevel syndrome where everything has to be connected manually. Instead plugins can discover their neighborhood by looking/using the software interface of other plugins." msgstr "" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:17 @@ -69,7 +69,7 @@ msgid "..." msgstr "" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:27 -msgid "And those plugins will then negociate/propagate/interconnect to each others via their pool of services." +msgid "And those plugins will then negotiate/propagate/interconnect to each others via their pool of services." msgstr "" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:29 @@ -89,11 +89,11 @@ msgid "The main idea is that you have multiple 2 executions phases :" msgstr "" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:38 -msgid "Setup phase, in which plugins can lock/retain each others. The idea is not to start negociation / elaboration yet." +msgid "Setup phase, in which plugins can lock/retain each others. The idea is not to start negotiation / elaboration yet." msgstr "" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:39 -msgid "Build phase, in which plugins can negociation / elaboration hardware." +msgid "Build phase, in which plugins can negotiation / elaboration hardware." msgstr "" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:41 @@ -137,7 +137,7 @@ msgid "Clearly, those examples are overkilled for what they do, the idea in gene msgstr "" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:238 -msgid "Negociate / create interfaces between plugins (ex jump / flush ports)" +msgid "Negotiate / create interfaces between plugins (ex jump / flush ports)" msgstr "" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:239 diff --git a/source/locale/gettext/SpinalHDL/Libraries/Pipeline/introduction.pot b/source/locale/gettext/SpinalHDL/Libraries/Pipeline/introduction.pot index b6f64c977d1..fe8734da9cb 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/Pipeline/introduction.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/Pipeline/introduction.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-02-20 09:54+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -33,7 +33,7 @@ msgid "Signals of the pipeline can utilize the powerful parametrization capabili msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:9 -msgid "Manual retiming is much easier, as you don't have to handle the registers / arbitration manualy" +msgid "Manual retiming is much easier, as you don't have to handle the registers / arbitration manually" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:10 @@ -101,7 +101,7 @@ msgid "Payload" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:150 -msgid "Payload objects are used to refer to data which can go through the pipeline. Technicaly speaking, Payload is a HardType which has a name and is used as a \"key\" to retrieve the signals in a certain pipeline stage." +msgid "Payload objects are used to refer to data which can go through the pipeline. Technically speaking, Payload is a HardType which has a name and is used as a \"key\" to retrieve the signals in a certain pipeline stage." msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:163 @@ -160,7 +160,7 @@ msgid "node.ready" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:185 -msgid "Is the signal which specifies if the node's transaction can proceed downstream. It is driven by the downstream to create backpresure. The signal has no meaning when there is no transaction (node.valid being deasserted)" +msgid "Is the signal which specifies if the node's transaction can proceed downstream. It is driven by the downstream to create backpressure. The signal has no meaning when there is no transaction (node.valid being deasserted)" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:186 @@ -209,7 +209,7 @@ msgid "node.isFiring" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:200 -msgid "True when the node transaction is successfuly moving futher (valid && ready && !cancel). Useful to commit state changes." +msgid "True when the node transaction is successfully moving further (valid && ready && !cancel). Useful to commit state changes." msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:201 @@ -233,7 +233,7 @@ msgid "Note that the node.valid/node.ready signals follows the same conventions msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:212 -msgid "The Node controls (valid/ready/cancel) and status (isValid, isReady, isCancel, isFiring, ...) signals are created on demande. So for instance you can create pipeline with no backpresure by never refering to the ready signal. That's why it is important to use status signals when you want to read the status of something and only use control signals when you to drive something." +msgid "The Node controls (valid/ready/cancel) and status (isValid, isReady, isCancel, isFiring, ...) signals are created on demand. So for instance you can create pipeline with no backpressure by never referring to the ready signal. That's why it is important to use status signals when you want to read the status of something and only use control signals when you to drive something." msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:215 @@ -327,7 +327,7 @@ msgid "Return a new Payload instance which is connected to the given Data hardwa msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:261 -msgid "While you can manualy drive/read the arbitration/data of the first/last stage of your pipeline, there is a few utilities to connect its boundaries." +msgid "While you can manually drive/read the arbitration/data of the first/last stage of your pipeline, there is a few utilities to connect its boundaries." msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:270 @@ -400,7 +400,7 @@ msgid "You can also use those implicit conversions by importing them :" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:327 -msgid "There is also an API which alows you to create new Area which provide the whole API of a given node instance (including implicit convertion) without import :" +msgid "There is also an API which allows you to create new Area which provide the whole API of a given node instance (including implicit conversion) without import :" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:338 @@ -436,7 +436,7 @@ msgid "S2mLink" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:373 -msgid "This connect two nodes using registers on the ready signal, which can be useful to improve backpresure combinatorial timings." +msgid "This connect two nodes using registers on the ready signal, which can be useful to improve backpressure combinatorial timings." msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:380 @@ -544,7 +544,7 @@ msgid "link.bypass(Payload)" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:436 -msgid "Allows to conditionaly override a Payload value between link.up -> link.down. This can be used to fix data hazard in CPU pipelines for instance." +msgid "Allows to conditionally override a Payload value between link.up -> link.down. This can be used to fix data hazard in CPU pipelines for instance." msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:455 @@ -580,7 +580,7 @@ msgid "To generate the hardware of your pipeline, you need to give a list of all msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:506 -msgid "There is also a set of \"all in one\" builders that you can instanciate to help yourself." +msgid "There is also a set of \"all in one\" builders that you can instantiate to help yourself." msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:508 @@ -604,11 +604,11 @@ msgid "The example below show a pattern which composes a pipeline with multiple msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:571 -msgid "This will produce the following data path (assuming lanesCount = 2), abitration not being shown :" +msgid "This will produce the following data path (assuming lanesCount = 2), arbitration not being shown :" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:578 -msgid "Retiming / Variable lenth" +msgid "Retiming / Variable length" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:580 @@ -648,7 +648,7 @@ msgid "One thing about this example is the necessity intermediate val as `addNod msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:817 -msgid "Unfortunatly, scala doesn't allow to replace `new addNode.Area` with `new nodes(addAt).Area`. One workaround is to define a class as :" +msgid "Unfortunately, scala doesn't allow to replace `new addNode.Area` with `new nodes(addAt).Area`. One workaround is to define a class as :" msgstr "" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:827 diff --git a/source/locale/gettext/SpinalHDL/Libraries/fiber.pot b/source/locale/gettext/SpinalHDL/Libraries/fiber.pot index 2befcd4098c..cd9a4a29f23 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/fiber.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/fiber.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -25,7 +25,7 @@ msgid "This framework is not expected to be used for general RTL generation and msgstr "" #: ../../SpinalHDL/Libraries/fiber.rst:13 -msgid "Currently in developpement." +msgid "Currently in development." msgstr "" #: ../../SpinalHDL/Libraries/fiber.rst:15 @@ -41,7 +41,7 @@ msgid "You can define things before even knowing all their requirements, ex : in msgstr "" #: ../../SpinalHDL/Libraries/fiber.rst:21 -msgid "Abstract/lazy/partial SoC architecture definition allowing the creation of SoC template for further specialisations" +msgid "Abstract/lazy/partial SoC architecture definition allowing the creation of SoC template for further specializations" msgstr "" #: ../../SpinalHDL/Libraries/fiber.rst:22 diff --git a/source/locale/gettext/SpinalHDL/Libraries/flow.pot b/source/locale/gettext/SpinalHDL/Libraries/flow.pot index 5f3a138304a..4d5789ef75e 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/flow.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/flow.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-03-30 15:02+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -129,7 +129,7 @@ msgid "x.m2sPipe()" msgstr "" #: ../../SpinalHDL/Libraries/flow.rst:0 -msgid "Return a Flow drived by x" +msgid "Return a Flow driven by x" msgstr "" #: ../../SpinalHDL/Libraries/flow.rst:0 diff --git a/source/locale/gettext/SpinalHDL/Libraries/fsm.pot b/source/locale/gettext/SpinalHDL/Libraries/fsm.pot index f840ba1a2fd..706ab3aa659 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/fsm.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/fsm.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -120,7 +120,7 @@ msgid "State encoding" msgstr "" #: ../../SpinalHDL/Libraries/fsm.rst:146 -msgid "By default the FSM state vector will be encoded using the native encoding of the language/tools the RTL is generated for (Verilog or VHDL). This default can be overriden by using the ``setEncoding(...)`` method which either takes a ``SpinalEnumEncoding`` or varargs of type ``(State, BigInt)`` for a custom encoding." +msgid "By default the FSM state vector will be encoded using the native encoding of the language/tools the RTL is generated for (Verilog or VHDL). This default can be overridden by using the ``setEncoding(...)`` method which either takes a ``SpinalEnumEncoding`` or varargs of type ``(State, BigInt)`` for a custom encoding." msgstr "" #: ../../SpinalHDL/Libraries/fsm.rst:150 @@ -233,7 +233,7 @@ msgid "The way the entry state has been defined above makes it so that between t msgstr "" #: ../../SpinalHDL/Libraries/fsm.rst:312 -msgid "While it is usefull, it is also possible to bypass that feature and directly having a state machine booting into a user state." +msgid "While it is useful, it is also possible to bypass that feature and directly having a state machine booting into a user state." msgstr "" #: ../../SpinalHDL/Libraries/fsm.rst:314 diff --git a/source/locale/gettext/SpinalHDL/Libraries/index.pot b/source/locale/gettext/SpinalHDL/Libraries/index.pot index e81561f594d..130114e98ae 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/index.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/index.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -45,7 +45,7 @@ msgid "Provide some example to get the spirit of spinal" msgstr "" #: ../../SpinalHDL/Libraries/index.rst:14 -msgid "Provide some tools and facilities (latency analyser, QSys converter, ...)" +msgid "Provide some tools and facilities (latency analyzer, QSys converter, ...)" msgstr "" #: ../../SpinalHDL/Libraries/index.rst:16 diff --git a/source/locale/gettext/SpinalHDL/Libraries/regIf.pot b/source/locale/gettext/SpinalHDL/Libraries/regIf.pot index cea492fef84..44800dfc721 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/regIf.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/regIf.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-02-26 12:25+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -46,7 +46,7 @@ msgid "Automatic address allocation" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:39 -msgid "Automatic fileds allocation" +msgid "Automatic filed allocation" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:54 @@ -512,7 +512,7 @@ msgid "example1: clock gate software enable" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:262 -msgid "example2: interrupt raw reg with foce interface for software" +msgid "example2: interrupt raw reg with force interface for software" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:272 @@ -591,7 +591,7 @@ msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:414 #: ../../SpinalHDL/Libraries/regIf.rst:433 -msgid "int mask register, 1: off; 0: open; defualt 1 int off" +msgid "int mask register, 1: off; 0: open; default 1 int off" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:415 @@ -674,7 +674,7 @@ msgid "``interrupt_W1SCmask_FactoryAt(addrOffset: BigInt, regNamePre: String, tr msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:457 -msgid "creat RAW/FORCE/MASK(SET/CLR)/STATUS for pulse event at addrOffset" +msgid "create RAW/FORCE/MASK(SET/CLR)/STATUS for pulse event at addrOffset" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:458 @@ -682,7 +682,7 @@ msgid "``interruptLevel_W1SCmask_FactoryAt(addrOffset: BigInt, regNamePre: Strin msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:458 -msgid "creat RAW/FORCE/MASK(SET/CLR)/STATUS for leveel event at addrOffset" +msgid "create RAW/FORCE/MASK(SET/CLR)/STATUS for level event at addrOffset" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:462 @@ -702,7 +702,7 @@ msgid "Developers Area" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:516 -msgid "You can add your document Type by extending the `BusIfVistor` Trait" +msgid "You can add your document Type by extending the `BusIfVisitor` Trait" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:518 @@ -710,5 +710,5 @@ msgid "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``" msgstr "" #: ../../SpinalHDL/Libraries/regIf.rst:520 -msgid "BusIfVistor give access BusIf.RegInsts to do what you want" +msgid "BusIfVisitor give access BusIf.RegInsts to do what you want" msgstr "" diff --git a/source/locale/gettext/SpinalHDL/Libraries/stream.pot b/source/locale/gettext/SpinalHDL/Libraries/stream.pot index ed254109b7f..ad37303fa12 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/stream.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/stream.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-06-14 13:17+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -145,7 +145,7 @@ msgid "When manually reading/driving the signals of a Stream keep in mind that:" msgstr "" #: ../../SpinalHDL/Libraries/stream.rst:82 -msgid "After being asserted, ``valid`` may only be deasserted once the current payload was acknowleged. This means ``valid`` can only toggle to 0 the cycle after a the slave did a read by asserting ``ready``." +msgid "After being asserted, ``valid`` may only be deasserted once the current payload was acknowledged. This means ``valid`` can only toggle to 0 the cycle after a the slave did a read by asserting ``ready``." msgstr "" #: ../../SpinalHDL/Libraries/stream.rst:83 @@ -254,7 +254,7 @@ msgid "x.stage()" msgstr "" #: ../../SpinalHDL/Libraries/stream.rst:0 -msgid "Return a Stream drived by x" +msgid "Return a Stream driven by x" msgstr "" #: ../../SpinalHDL/Libraries/stream.rst:0 @@ -644,7 +644,7 @@ msgid "sequentialOrder" msgstr "" #: ../../SpinalHDL/Libraries/stream.rst:0 -msgid "Could be used to retrieve transaction in a sequancial order" +msgid "Could be used to retrieve transaction in a sequential order" msgstr "" #: ../../SpinalHDL/Libraries/stream.rst:0 @@ -792,7 +792,7 @@ msgid "Testbench master side, drives values by calling function to apply value ( msgstr "" #: ../../SpinalHDL/Libraries/stream.rst:599 -msgid "StreamReadyRandmizer" +msgid "StreamReadyRandomizer" msgstr "" #: ../../SpinalHDL/Libraries/stream.rst:600 diff --git a/source/locale/gettext/SpinalHDL/Libraries/utils.pot b/source/locale/gettext/SpinalHDL/Libraries/utils.pot index 934bdc1badd..1a7b501f440 100644 --- a/source/locale/gettext/SpinalHDL/Libraries/utils.pot +++ b/source/locale/gettext/SpinalHDL/Libraries/utils.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-04-19 10:29+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -311,6 +311,7 @@ msgid "The Counter tool can be used to easily instantiate a hardware counter." msgstr "" #: ../../SpinalHDL/Libraries/utils.rst:123 +#: ../../SpinalHDL/Libraries/utils.rst:166 msgid "Instantiation syntax" msgstr "" @@ -371,10 +372,6 @@ msgstr "" msgid "The Timeout tool can be used to easily instantiate an hardware timeout." msgstr "" -#: ../../SpinalHDL/Libraries/utils.rst:166 -msgid "Instanciation syntax" -msgstr "" - #: ../../SpinalHDL/Libraries/utils.rst:168 msgid "Timeout(cycles : BigInt)" msgstr "" @@ -420,7 +417,7 @@ msgid "asyncAssertSyncDeassert" msgstr "" #: ../../SpinalHDL/Libraries/utils.rst:196 -msgid "You can filter an asynchronous reset by using an asynchronously asserted synchronously deaserted logic. To do it you can use the ``ResetCtrl.asyncAssertSyncDeassert`` function which will return you the filtered value." +msgid "You can filter an asynchronous reset by using an asynchronously asserted synchronously deasserted logic. To do it you can use the ``ResetCtrl.asyncAssertSyncDeassert`` function which will return you the filtered value." msgstr "" #: ../../SpinalHDL/Libraries/utils.rst:202 diff --git a/source/locale/gettext/SpinalHDL/Other language features/scope_property.pot b/source/locale/gettext/SpinalHDL/Other language features/scope_property.pot index 91c531a03d7..717c23f8dd5 100644 --- a/source/locale/gettext/SpinalHDL/Other language features/scope_property.pot +++ b/source/locale/gettext/SpinalHDL/Other language features/scope_property.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -29,7 +29,7 @@ msgid "In other words it is a alternative to global variable, scala implicit, Th msgstr "" #: ../../SpinalHDL/Other language features/scope_property.rst:10 -msgid "To compare with global variable, It allow to run multiple thread running the same code indepedently" +msgid "To compare with global variable, It allow to run multiple thread running the same code independently" msgstr "" #: ../../SpinalHDL/Other language features/scope_property.rst:11 diff --git a/source/locale/gettext/SpinalHDL/Other language features/stub.pot b/source/locale/gettext/SpinalHDL/Other language features/stub.pot index f2283b9be49..74cd572d455 100644 --- a/source/locale/gettext/SpinalHDL/Other language features/stub.pot +++ b/source/locale/gettext/SpinalHDL/Other language features/stub.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -45,7 +45,7 @@ msgid "then remove all children component" msgstr "" #: ../../SpinalHDL/Other language features/stub.rst:53 -msgid "then remove all assignment and logic we dont want" +msgid "then remove all assignment and logic we don't want" msgstr "" #: ../../SpinalHDL/Other language features/stub.rst:54 diff --git a/source/locale/gettext/SpinalHDL/Semantic/assignments.pot b/source/locale/gettext/SpinalHDL/Semantic/assignments.pot index 47f94f092b9..94c34bfbe53 100644 --- a/source/locale/gettext/SpinalHDL/Semantic/assignments.pot +++ b/source/locale/gettext/SpinalHDL/Semantic/assignments.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -58,7 +58,7 @@ msgid "Automatic connection between 2 signals or two bundles of the same type. D msgstr "" #: ../../SpinalHDL/Semantic/assignments.rst:19 -msgid "When muxing (for instance using ``when``, see :doc:`when_switch`.), the last valid standard assignment ``:=`` wins. Else, assigning twice to the same assignee from the same scope results in an assignment overlap. SpinalHDL will assume this is a unintentional design error by default and halt elaboration with error. For special use-cases assignment overlap can be programatically permitted on a case by case basis. (see :doc:`../Design errors/assignment_overlap`)." +msgid "When muxing (for instance using ``when``, see :doc:`when_switch`.), the last valid standard assignment ``:=`` wins. Else, assigning twice to the same assignee from the same scope results in an assignment overlap. SpinalHDL will assume this is a unintentional design error by default and halt elaboration with error. For special use-cases assignment overlap can be programmatically permitted on a case by case basis. (see :doc:`../Design errors/assignment_overlap`)." msgstr "" #: ../../SpinalHDL/Semantic/assignments.rst:45 @@ -150,5 +150,5 @@ msgid "``CombInit`` is particularly helpful in helper functions to ensure that t msgstr "" #: ../../SpinalHDL/Semantic/assignments.rst:181 -msgid "Without ``CombInit``, if ``c`` == false (but not if ``c`` == true), ``a1`` and ``a2`` reference the same signal and the zero assignment is also applied to ``a1``. With ``CombInit`` we have a coherent behaviour whatever the ``c`` value." +msgid "Without ``CombInit``, if ``c`` == false (but not if ``c`` == true), ``a1`` and ``a2`` reference the same signal and the zero assignment is also applied to ``a1``. With ``CombInit`` we have a coherent behavior whatever the ``c`` value." msgstr "" diff --git a/source/locale/gettext/SpinalHDL/Semantic/rules.pot b/source/locale/gettext/SpinalHDL/Semantic/rules.pot index d090beb885a..4627bccae5e 100644 --- a/source/locale/gettext/SpinalHDL/Semantic/rules.pot +++ b/source/locale/gettext/SpinalHDL/Semantic/rules.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -77,7 +77,7 @@ msgid "If a combinational signal or register is assigned multiple times through msgstr "" #: ../../SpinalHDL/Semantic/rules.rst:46 -msgid "It could be said that top to bottom evaluation occurs based on the state that exists at that time. If your upstream signal inputs are driven from registers and so have synchronous behaviour, then it could be said that at each clock cycle the assignments are re-evaluated based on the new state at the time." +msgid "It could be said that top to bottom evaluation occurs based on the state that exists at that time. If your upstream signal inputs are driven from registers and so have synchronous behavior, then it could be said that at each clock cycle the assignments are re-evaluated based on the new state at the time." msgstr "" #: ../../SpinalHDL/Semantic/rules.rst:51 @@ -85,7 +85,7 @@ msgid "Some reasons why an assignment statement may not get to execute in hardwa msgstr "" #: ../../SpinalHDL/Semantic/rules.rst:54 -msgid "Another reason maybe that the SpinalHDL code never made it through elaboration because the feature was paramaterized and disabled during HDL code-generation, see ``paramIsFalse`` use below." +msgid "Another reason maybe that the SpinalHDL code never made it through elaboration because the feature was parameterized and disabled during HDL code-generation, see ``paramIsFalse`` use below." msgstr "" #: ../../SpinalHDL/Semantic/rules.rst:58 diff --git a/source/locale/gettext/SpinalHDL/Simulation/bootstraps.pot b/source/locale/gettext/SpinalHDL/Simulation/bootstraps.pot index e72c635e720..f1143efe15e 100644 --- a/source/locale/gettext/SpinalHDL/Simulation/bootstraps.pot +++ b/source/locale/gettext/SpinalHDL/Simulation/bootstraps.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-02-01 10:15+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -189,7 +189,7 @@ msgid "For the verilator backend, you can override the location of the test fold msgstr "" #: ../../SpinalHDL/Simulation/bootstraps.rst:165 -msgid "You can retrieve the location of the test path durring simulation by calling the currentTestPath() function." +msgid "You can retrieve the location of the test path during simulation by calling the currentTestPath() function." msgstr "" #: ../../SpinalHDL/Simulation/bootstraps.rst:169 diff --git a/source/locale/gettext/SpinalHDL/Simulation/clock.pot b/source/locale/gettext/SpinalHDL/Simulation/clock.pot index 8c0b46f0c63..c337823e3a3 100644 --- a/source/locale/gettext/SpinalHDL/Simulation/clock.pot +++ b/source/locale/gettext/SpinalHDL/Simulation/clock.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -273,26 +273,26 @@ msgstr "" msgid "Same as onSampling, but you can stop it (forever) by letting the callback returning false" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:103 +#: ../../SpinalHDL/Simulation/clock.rst:102 msgid "Default ClockDomain" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:105 +#: ../../SpinalHDL/Simulation/clock.rst:104 msgid "You can access the default ``ClockDomain`` of your toplevel as shown below:" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:121 +#: ../../SpinalHDL/Simulation/clock.rst:120 msgid "Note that you can also directly fork a standard reset/clock process:" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:127 +#: ../../SpinalHDL/Simulation/clock.rst:126 msgid "An example of how to wait for a rising edge on the clock:" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:135 +#: ../../SpinalHDL/Simulation/clock.rst:134 msgid "New ClockDomain" msgstr "" -#: ../../SpinalHDL/Simulation/clock.rst:137 +#: ../../SpinalHDL/Simulation/clock.rst:136 msgid "If your toplevel defines some clock and reset inputs which aren't directly integrated into their ``ClockDomain``, you can define their corresponding ``ClockDomain`` directly in the testbench:" msgstr "" diff --git a/source/locale/gettext/SpinalHDL/Simulation/install/Icarus Verilog.pot b/source/locale/gettext/SpinalHDL/Simulation/install/Icarus Verilog.pot index d844d4cad62..9a477c31113 100644 --- a/source/locale/gettext/SpinalHDL/Simulation/install/Icarus Verilog.pot +++ b/source/locale/gettext/SpinalHDL/Simulation/install/Icarus Verilog.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -33,5 +33,5 @@ msgid "Linux" msgstr "" #: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:20 -msgid "Also the openjdk package that corresponds to your Java version has to be installed. Refer to ``_ for more informations about Windows and installation from source." +msgid "Also the openjdk package that corresponds to your Java version has to be installed. Refer to ``_ for more information about Windows and installation from source." msgstr "" diff --git a/source/locale/gettext/SpinalHDL/Simulation/install/VCS.pot b/source/locale/gettext/SpinalHDL/Simulation/install/VCS.pot index 36756691648..73b8da08ca2 100644 --- a/source/locale/gettext/SpinalHDL/Simulation/install/VCS.pot +++ b/source/locale/gettext/SpinalHDL/Simulation/install/VCS.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -184,7 +184,7 @@ msgid "Simulation with ``Blackbox``" msgstr "" #: ../../SpinalHDL/Simulation/install/VCS.rst:125 -msgid "Sometimes, IP vendors will provide you with some design entites in Verilog/VHDL format and you want to integrate them into your SpinalHDL design. The integration can done by following two ways:" +msgid "Sometimes, IP vendors will provide you with some design entities in Verilog/VHDL format and you want to integrate them into your SpinalHDL design. The integration can done by following two ways:" msgstr "" #: ../../SpinalHDL/Simulation/install/VCS.rst:128 diff --git a/source/locale/gettext/SpinalHDL/Simulation/install/Verilator.pot b/source/locale/gettext/SpinalHDL/Simulation/install/Verilator.pot index 86743d09720..a211edaec73 100644 --- a/source/locale/gettext/SpinalHDL/Simulation/install/Verilator.pot +++ b/source/locale/gettext/SpinalHDL/Simulation/install/Verilator.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -101,5 +101,5 @@ msgid "Be sure that your ``PATH`` environnement variable is pointing to the JDK msgstr "" #: ../../SpinalHDL/Simulation/install/Verilator.rst:117 -msgid "Adding the MSYS2 ``bin`` folders into your windows ``PATH`` could potentialy have some side effects. This is why it is safer to add them as the last elements of the ``PATH`` to reduce their priority." +msgid "Adding the MSYS2 ``bin`` folders into your windows ``PATH`` could potentially have some side effects. This is why it is safer to add them as the last elements of the ``PATH`` to reduce their priority." msgstr "" diff --git a/source/locale/gettext/SpinalHDL/Structuring/clock_domain.pot b/source/locale/gettext/SpinalHDL/Structuring/clock_domain.pot index c65fc2eefa3..6a4f2dec2a2 100644 --- a/source/locale/gettext/SpinalHDL/Structuring/clock_domain.pot +++ b/source/locale/gettext/SpinalHDL/Structuring/clock_domain.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-26 16:21+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -302,7 +302,7 @@ msgid "In the current version, reset and clock enable signals have different pri msgstr "" #: ../../SpinalHDL/Structuring/clock_domain.rst:300 -msgid "Please be careful that clockEnable has a higher priority than syncReset. If you do a sync reset when the clockEnable is disabled (especially at the beginning of a simulation), the gated registers will not be reseted." +msgid "Please be careful that clockEnable has a higher priority than syncReset. If you do a sync reset when the clockEnable is disabled (especially at the beginning of a simulation), the gated registers will not be reset." msgstr "" #: ../../SpinalHDL/Structuring/clock_domain.rst:302 @@ -314,7 +314,7 @@ msgid "It will generate VerilogHDL codes like:" msgstr "" #: ../../SpinalHDL/Structuring/clock_domain.rst:324 -msgid "If that behaviour is problematic, one workaround is to use a when statement as a clock enable instead of using the ClockDomain.enable feature. This is open for future improvements." +msgid "If that behavior is problematic, one workaround is to use a when statement as a clock enable instead of using the ClockDomain.enable feature. This is open for future improvements." msgstr "" #: ../../SpinalHDL/Structuring/clock_domain.rst:327 diff --git a/source/locale/gettext/SpinalHDL/Structuring/components_hierarchy.pot b/source/locale/gettext/SpinalHDL/Structuring/components_hierarchy.pot index 508cb11fa3e..490ec6cc2f8 100644 --- a/source/locale/gettext/SpinalHDL/Structuring/components_hierarchy.pot +++ b/source/locale/gettext/SpinalHDL/Structuring/components_hierarchy.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-07-29 08:01+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -146,7 +146,7 @@ msgid "Pruned signals" msgstr "" #: ../../SpinalHDL/Structuring/components_hierarchy.rst:92 -msgid "SpinalHDL will generate all the named signals and their depedencies, while all the useless anonymous / zero width ones are removed from the RTL generation." +msgid "SpinalHDL will generate all the named signals and their dependencies, while all the useless anonymous / zero width ones are removed from the RTL generation." msgstr "" #: ../../SpinalHDL/Structuring/components_hierarchy.rst:95 diff --git a/source/locale/gettext/SpinalHDL/Structuring/index.pot b/source/locale/gettext/SpinalHDL/Structuring/index.pot index 48a005da9e8..77eca9d325d 100644 --- a/source/locale/gettext/SpinalHDL/Structuring/index.pot +++ b/source/locale/gettext/SpinalHDL/Structuring/index.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -37,7 +37,7 @@ msgid "handling of clock/reset domains" msgstr "" #: ../../SpinalHDL/Structuring/index.rst:10 -msgid "instantitation of existing VHDL and Verilog IP" +msgid "instantiation of existing VHDL and Verilog IP" msgstr "" #: ../../SpinalHDL/Structuring/index.rst:11 diff --git a/source/locale/gettext/SpinalHDL/Structuring/naming.pot b/source/locale/gettext/SpinalHDL/Structuring/naming.pot index 0e812a74261..519668e077e 100644 --- a/source/locale/gettext/SpinalHDL/Structuring/naming.pot +++ b/source/locale/gettext/SpinalHDL/Structuring/naming.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -57,7 +57,7 @@ msgid "Will generation :" msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:41 -msgid "In general, you don't realy need to access that API, unless you want to do tricky stuff for debug reasons or for elaboration purposes." +msgid "In general, you don't really need to access that API, unless you want to do tricky stuff for debug reasons or for elaboration purposes." msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:44 @@ -144,7 +144,7 @@ msgid "Composite in a Bundle's function" msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:255 -msgid "This behaviour can be very useful when implementing Bundle utilities. For instance in the spinal.lib.Stream class is defined the following :" +msgid "This behavior can be very useful when implementing Bundle utilities. For instance in the spinal.lib.Stream class is defined the following :" msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:288 @@ -152,15 +152,15 @@ msgid "Which allow nested calls while preserving the names :" msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:363 -msgid "Unamed signal handling" +msgid "Unnamed signal handling" msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:365 -msgid "Since 1.5.0, for signal which end up without name, SpinalHDL will find a signal which is driven by that unamed signal and propagate its name. This can produce useful results as long you don't have too large island of unamed stuff." +msgid "Since 1.5.0, for signal which end up without name, SpinalHDL will find a signal which is driven by that unnamed signal and propagate its name. This can produce useful results as long you don't have too large island of unnamed stuff." msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:367 -msgid "The name attributed to such unamed signal is : _zz_ + drivenSignal.getName()" +msgid "The name attributed to such unnamed signal is : _zz_ + drivenSignal.getName()" msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:369 @@ -172,7 +172,7 @@ msgid "Verilog expression splitting" msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:374 -msgid "There is an instance of expressions (ex : the + operator) that SpinalHDL need to express in dedicated signals to match the behaviour with the Scala API :" +msgid "There is an instance of expressions (ex : the + operator) that SpinalHDL need to express in dedicated signals to match the behavior with the Scala API :" msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:404 @@ -180,7 +180,7 @@ msgid "Verilog long expression splitting" msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:406 -msgid "There is a instance of how a very long expression chain will be splited up by SpinalHDL :" +msgid "There is a instance of how a very long expression chain will be split up by SpinalHDL :" msgstr "" #: ../../SpinalHDL/Structuring/naming.rst:448 diff --git a/source/locale/gettext/SpinalHDL/Structuring/parametrization.pot b/source/locale/gettext/SpinalHDL/Structuring/parametrization.pot index c4b000becc2..d8c854052ba 100644 --- a/source/locale/gettext/SpinalHDL/Structuring/parametrization.pot +++ b/source/locale/gettext/SpinalHDL/Structuring/parametrization.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -65,7 +65,7 @@ msgid "Here are some examples and ideas of the possibilities:" msgstr "" #: ../../SpinalHDL/Structuring/parametrization.rst:46 -msgid "Hardwired code and constants (not strictly parameter management at all but serves to hilight the most basic mechanism, a code change, not a parameter data change)" +msgid "Hardwired code and constants (not strictly parameter management at all but serves to highlight the most basic mechanism, a code change, not a parameter data change)" msgstr "" #: ../../SpinalHDL/Structuring/parametrization.rst:49 @@ -133,11 +133,11 @@ msgid "The ``generate`` method is a mechanism to evaluate the expression that fo msgstr "" #: ../../SpinalHDL/Structuring/parametrization.rst:111 -msgid "This may be used in cases to help parameterize the SpinalHDL hardware description using an elaboration-time conditional expression. Causing HDL constructs to be emitted or not-emitted in the resulting HDL. The generate method can be seen as SpinalHDL syntatic sugar reducing language clutter." +msgid "This may be used in cases to help parameterize the SpinalHDL hardware description using an elaboration-time conditional expression. Causing HDL constructs to be emitted or not-emitted in the resulting HDL. The generate method can be seen as SpinalHDL syntactic sugar reducing language clutter." msgstr "" #: ../../SpinalHDL/Structuring/parametrization.rst:116 -msgid "Project SpinalHDL code referencing ``mySignal`` would need to ensure it handles the possiblity of null gracefully. This is usually not a problem as those parts of the design can also be omitted dependant on the ``flag`` value. Thus the feature of parameterizing this component is demonstrated." +msgid "Project SpinalHDL code referencing ``mySignal`` would need to ensure it handles the possibility of null gracefully. This is usually not a problem as those parts of the design can also be omitted dependant on the ``flag`` value. Thus the feature of parameterizing this component is demonstrated." msgstr "" #: ../../SpinalHDL/Structuring/parametrization.rst:122 diff --git a/source/locale/gettext/SpinalHDL/miscelenea/core/core_components.pot b/source/locale/gettext/SpinalHDL/miscelenea/core/core_components.pot index 101348356ab..dbfd8327e2b 100644 --- a/source/locale/gettext/SpinalHDL/miscelenea/core/core_components.pot +++ b/source/locale/gettext/SpinalHDL/miscelenea/core/core_components.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -197,7 +197,7 @@ msgid "There are multiple assignment operator :" msgstr "" #: ../../SpinalHDL/miscelenea/core/core_components.rst:168 -msgid "Symbole" +msgid "Symbol" msgstr "" #: ../../SpinalHDL/miscelenea/core/core_components.rst:169 @@ -240,7 +240,7 @@ msgid "Automatic connection between 2 signals. Direction is inferred by using si msgstr "" #: ../../SpinalHDL/miscelenea/core/core_components.rst:0 -msgid "Similar behavioural than :=" +msgid "Similar behavioral than :=" msgstr "" #: ../../SpinalHDL/miscelenea/core/core_components.rst:197 @@ -268,11 +268,11 @@ msgid "Assign x with a resized copy of y, size is manually calculated" msgstr "" #: ../../SpinalHDL/miscelenea/core/core_components.rst:211 -msgid "There are 2 cases where spinal automaticly resize things :" +msgid "There are 2 cases where spinal automatically resize things :" msgstr "" #: ../../SpinalHDL/miscelenea/core/core_components.rst:217 -msgid "Assignement" +msgid "Assignment" msgstr "" #: ../../SpinalHDL/miscelenea/core/core_components.rst:218 @@ -414,7 +414,7 @@ msgid "Everything work by reference, which allow many manipulation." msgstr "" #: ../../SpinalHDL/miscelenea/core/core_components.rst:0 -msgid "For example you can give to a function an bus as argument, then the function can internaly read/write it." +msgid "For example you can give to a function an bus as argument, then the function can internally read/write it." msgstr "" #: ../../SpinalHDL/miscelenea/core/core_components.rst:0 diff --git a/source/locale/gettext/SpinalHDL/miscelenea/frequent_errors.pot b/source/locale/gettext/SpinalHDL/miscelenea/frequent_errors.pot index 207963dd32c..394dd4b05c3 100644 --- a/source/locale/gettext/SpinalHDL/miscelenea/frequent_errors.pot +++ b/source/locale/gettext/SpinalHDL/miscelenea/frequent_errors.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -66,7 +66,7 @@ msgid "Signal X can't be assigned by Y" msgstr "" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:82 -msgid "You can only assign input signals of subcomponents, else there is an hierarchy violation. If this issue happend, you probably forgot to specify the X signal's direction." +msgid "You can only assign input signals of subcomponents, else there is an hierarchy violation. If this issue happened, you probably forgot to specify the X signal's direction." msgstr "" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:85 @@ -74,7 +74,7 @@ msgid "Input signal X can't be assigned by Y" msgstr "" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:109 -msgid "You can only assign an input signals from the parent component, else there is an hierarchy violation. If this issue happend, you probably mixed signals direction declaration." +msgid "You can only assign an input signals from the parent component, else there is an hierarchy violation. If this issue happened, you probably mixed signals direction declaration." msgstr "" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:112 @@ -82,5 +82,5 @@ msgid "Output signal X can't be assigned by Y" msgstr "" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:141 -msgid "You can only assign output signals of a component from the inside of it, else there is an hierarchy violation. If this issue happend, you probably mixed signals direction declaration." +msgid "You can only assign output signals of a component from the inside of it, else there is an hierarchy violation. If this issue happened, you probably mixed signals direction declaration." msgstr "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po index 4162b312624..c128824211a 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po @@ -10,7 +10,7 @@ msgstr "" "+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" -"POT-Creation-Date: 2024-07-20 14:42+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-13 05:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" "Language: zh_CN\n" @@ -20,7 +20,7 @@ msgstr "" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Generated-By: Babel 2.15.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Data types/Int.rst:4 types/Int.rst:620 msgid "UInt/SInt" @@ -330,8 +330,9 @@ msgid "Set all bits to the given Bool value" msgstr "将所有位设置为给定的布尔值（Spinal Bool）" #: ../../SpinalHDL/Data types/Int.rst:142 +#, fuzzy msgid "" -"Notice the difference in behaviour between ``x >> 2`` (result 2 bit " +"Notice the difference in behavior between ``x >> 2`` (result 2 bit " "narrower than x) and ``x >> U(2)`` (keeping width) due to the Scala type " "of :code:`y`." msgstr "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po index 8098820c1ce..e0a5b8e95a2 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po @@ -1,26 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"POT-Creation-Date: 2024-02-13 17:23+0000\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-02-18 15:28+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Data types/Vec.rst:7 msgid "Vec" @@ -166,7 +166,8 @@ msgid "x.sCount(condition: T => Bool)" msgstr "x.sCount(condition: T => Bool)" #: ../../SpinalHDL/Data types/Vec.rst:150 -msgid "Count the number of occurence matching a given condition in the Vec." +#, fuzzy +msgid "Count the number of occurrence matching a given condition in the Vec." msgstr "计算 Vec 中与给定条件匹配的次数。" #: ../../SpinalHDL/Data types/Vec.rst:151 types/Vec.rst:154 @@ -178,7 +179,8 @@ msgid "x.sCount(value: T)" msgstr "x.sCount(value: T)" #: ../../SpinalHDL/Data types/Vec.rst:153 -msgid "Count the number of occurence of a value in the Vec." +#, fuzzy +msgid "Count the number of occurrence of a value in the Vec." msgstr "计算 Vec 中某个值出现的次数。" #: ../../SpinalHDL/Data types/Vec.rst:155 @@ -245,3 +247,4 @@ msgstr "sXXX 前缀用于消除使用 lambda 函数作为参数的同名 Scala #~ msgid "Vec(type: Data, size: Int)" #~ msgstr "Vec（类型：数据，大小：Int）" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po index 02c8029c36b..8d6a2a30290 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-13 05:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Data types/bool.rst:4 types/bool.rst:70 types/bool.rst:73 #: types/bool.rst:76 types/bool.rst:80 types/bool.rst:112 types/bool.rst:116 @@ -35,46 +38,44 @@ msgstr "描述" #: ../../SpinalHDL/Data types/bool.rst:9 msgid "" -"The ``Bool`` type corresponds to a boolean value (True or False) or a single" -" bit/wire used in a hardware design. While named similarly it should not be" -" confused with Scala `Boolean` type which does not describe hardware but " -"truth values in the Scala generator code." +"The ``Bool`` type corresponds to a boolean value (True or False) or a " +"single bit/wire used in a hardware design. While named similarly it " +"should not be confused with Scala `Boolean` type which does not describe " +"hardware but truth values in the Scala generator code." msgstr "" -"``Bool`` 类型对应于硬件设计中使用的布尔值（True 或 " -"False）或单个位/线。虽然名称类似，但不应与 Scala `Boolean` " -"类型混淆，后者不描述硬件，而是描述 Scala 生成器代码中的真值。" +"``Bool`` 类型对应于硬件设计中使用的布尔值（True 或 False）或单个位/线。虽然名称类似，但不应与 Scala `Boolean`" +" 类型混淆，后者不描述硬件，而是描述 Scala 生成器代码中的真值。" #: ../../SpinalHDL/Data types/bool.rst:14 +#, fuzzy msgid "" "An important concept and rule-of-thumb to understand is that the Scala " -"`Boolean` type is used in places where elaboration-time HDL code-generation " -"decision making is occuring in Scala code. Like any regular program it " -"affects execution of the Scala program that is SpinalHDL at the time the " -"program is being run to perform HDL code generation." +"`Boolean` type is used in places where elaboration-time HDL code-" +"generation decision making is occurring in Scala code. Like any regular " +"program it affects execution of the Scala program that is SpinalHDL at " +"the time the program is being run to perform HDL code generation." msgstr "" -"需要理解的一个重要概念和经验是，Scala `Boolean` " -"类型用于在实例细化时决定如何生成 HDL 代码。与任何常规程序一样，在运行 " +"需要理解的一个重要概念和经验是，Scala `Boolean` 类型用于在实例细化时决定如何生成 HDL 代码。与任何常规程序一样，在运行 " "SpinalHDL 程序以执行 HDL 代码生成时，它会影响 Scala 程序的执行。" #: ../../SpinalHDL/Data types/bool.rst:20 msgid "" -"Therefore the value of a Scala `Boolean` can not be observed from hardware, " -"because it only exists ahead-of-time in the SpinalHDL program at the time of" -" HDL code-gen." +"Therefore the value of a Scala `Boolean` can not be observed from " +"hardware, because it only exists ahead-of-time in the SpinalHDL program " +"at the time of HDL code-gen." msgstr "" -"因此，Scala `Boolean` 的值无法从硬件中观察到，因为它仅在 HDL " -"代码生成时存在于 SpinalHDL 程序中，这在硬件仿真/运行之前。" +"因此，Scala `Boolean` 的值无法从硬件中观察到，因为它仅在 HDL 代码生成时存在于 SpinalHDL " +"程序中，这在硬件仿真/运行之前。" #: ../../SpinalHDL/Data types/bool.rst:24 msgid "" -"In scenarios where you might need this for your design, for example to pass " -"a value (that maybe acting as a parameterized constant input) from Scala " -"into your hardware design, you can type convert it to Bool with the " -"constructor `Bool(value: Boolean)`." +"In scenarios where you might need this for your design, for example to " +"pass a value (that maybe acting as a parameterized constant input) from " +"Scala into your hardware design, you can type convert it to Bool with the" +" constructor `Bool(value: Boolean)`." msgstr "" -"在您的设计中可能需要这样做，例如从 Scala " -"向硬件设计中传递一个值（该值可能作为参数化常量输入），您可以使用构造函数 " -"`Bool(value: Boolean)` 将其类型转换为 `Bool` 。" +"在您的设计中可能需要这样做，例如从 Scala 向硬件设计中传递一个值（该值可能作为参数化常量输入），您可以使用构造函数 `Bool(value:" +" Boolean)` 将其类型转换为 `Bool` 。" #: ../../SpinalHDL/Data types/bool.rst:28 msgid "" @@ -83,59 +84,52 @@ msgid "" "concerning a `wire` and how it is routed (through modules/Components), " "driven (sourced) and connected (sunk)." msgstr "" -"同样，SpinalHDL `Bool` 的值在代码生成时无法看到，" -"所有可以看到和操作的都是有关 `wire` 的 HDL " +"同样，SpinalHDL `Bool` 的值在代码生成时无法看到，所有可以看到和操作的都是有关 `wire` 的 HDL " "构造以及它如何路由（通过模块/组件）、驱动（源）并连接（汇据点）。" #: ../../SpinalHDL/Data types/bool.rst:32 msgid "" -"The signal direction of assignment operators `:=` is managed by SpinalHDL. " -"The use of the Bool instance on the left-hand-side or the right-hand-side of" -" the assignment operator `:=` dictates if it is a source (provides state) or" -" sink (captures state) for a given assignment." +"The signal direction of assignment operators `:=` is managed by " +"SpinalHDL. The use of the Bool instance on the left-hand-side or the " +"right-hand-side of the assignment operator `:=` dictates if it is a " +"source (provides state) or sink (captures state) for a given assignment." msgstr "" -"赋值运算符 `:=` 的信号方向由 SpinalHDL 管理。在赋值运算符 `:=` " -"左侧或右侧使用 `Bool` " +"赋值运算符 `:=` 的信号方向由 SpinalHDL 管理。在赋值运算符 `:=` 左侧或右侧使用 `Bool` " "实例指示它是给定赋值的源（提供状态）还是接收器（捕获状态）。" #: ../../SpinalHDL/Data types/bool.rst:37 msgid "" -"Multiple uses of the assignment operator are allowed, such that it is normal" -" for a signal wire to act as a source (provides a value to drive HDL state) " -"to be able to connect and drive multiple inputs of other HDL constructs. " -"When a Bool instance used as a source the order the assignment statements " -"appear or are executed in Scala does not matter, unlike when it is used as a" -" sink (captures state)." +"Multiple uses of the assignment operator are allowed, such that it is " +"normal for a signal wire to act as a source (provides a value to drive " +"HDL state) to be able to connect and drive multiple inputs of other HDL " +"constructs. When a Bool instance used as a source the order the " +"assignment statements appear or are executed in Scala does not matter, " +"unlike when it is used as a sink (captures state)." msgstr "" -"允许多次使用赋值运算符，因此信号线作为源（提供值以驱动 HDL 状态）" -"连接并驱动其他 HDL 结构的多个输入是很正常的。 当 Bool 实例用作源时，" -"赋值语句在 Scala " -"中出现或执行的顺序并不重要，而当它用作汇（捕获状态）时则不同。" +"允许多次使用赋值运算符，因此信号线作为源（提供值以驱动 HDL 状态）连接并驱动其他 HDL 结构的多个输入是很正常的。 当 Bool " +"实例用作源时，赋值语句在 Scala 中出现或执行的顺序并不重要，而当它用作汇（捕获状态）时则不同。" #: ../../SpinalHDL/Data types/bool.rst:44 msgid "" -"When multiple assignment operators drive the Bool (the Bool is on the left-" -"hand-side of the assignment expression), the last assignment statement wins " -"rule; take effect. The last would be the last to execute in Scala code. " -"This matter can affect the layout and ordering of your SpinalHDL Scala code " -"to ensure the correct precedence order is archived in the hardware design " -"for assigning a new state to the Bool in hardware." +"When multiple assignment operators drive the Bool (the Bool is on the " +"left-hand-side of the assignment expression), the last assignment " +"statement wins rule; take effect. The last would be the last to execute " +"in Scala code. This matter can affect the layout and ordering of your " +"SpinalHDL Scala code to ensure the correct precedence order is archived " +"in the hardware design for assigning a new state to the Bool in hardware." msgstr "" -"当多个赋值操作符驱动 Bool（Bool " -"位于赋值表达式的左侧）时，最后一个赋值语句将赢得胜利；并开始生效。 " -"最后一个将在 Scala 代码中最后执行。 此事会影响 SpinalHDL Scala " -"代码的布局和排序，以确保在硬件设计中获得正确的优先顺序，以便在硬件中为 Bool " +"当多个赋值操作符驱动 Bool（Bool 位于赋值表达式的左侧）时，最后一个赋值语句将赢得胜利；并开始生效。 最后一个将在 Scala " +"代码中最后执行。 此事会影响 SpinalHDL Scala 代码的布局和排序，以确保在硬件设计中获得正确的优先顺序，以便在硬件中为 Bool " "赋值新状态。" #: ../../SpinalHDL/Data types/bool.rst:51 msgid "" "It may help to understand the concept with relating the Scala/SpinalHDL " -"`Bool` instance as a reference to a HDL `net` in the net-list. Which the " -"assignment `:=` operator is attaching HDL constructs into the same net." +"`Bool` instance as a reference to a HDL `net` in the net-list. Which the" +" assignment `:=` operator is attaching HDL constructs into the same net." msgstr "" -"将 Scala/SpinalHDL `Bool` 实例作为对 net-list 中 HDL `net` " -"的引用，可能有助于理解这一概念。 其中，赋值 `:=` 操作符将 HDL " -"结构加入到同一个网中。" +"将 Scala/SpinalHDL `Bool` 实例作为对 net-list 中 HDL `net` 的引用，可能有助于理解这一概念。 " +"其中，赋值 `:=` 操作符将 HDL 结构加入到同一个网中。" #: ../../SpinalHDL/Data types/bool.rst:57 msgid "Declaration" @@ -143,16 +137,15 @@ msgstr "声明" #: ../../SpinalHDL/Data types/bool.rst:59 msgid "" -"The syntax to declare a boolean value is as follows: (everything between [] " -"is optional)" +"The syntax to declare a boolean value is as follows: (everything between " +"[] is optional)" msgstr "声明布尔值的语法如下：（[]之间的所有内容都是可选的）" #: ../../SpinalHDL/Data types/bool.rst:65 msgid "Syntax" msgstr "语法" -#: ../../SpinalHDL/Data types/bool.rst:67 types/bool.rst:272 -#: types/bool.rst:306 +#: ../../SpinalHDL/Data types/bool.rst:67 types/bool.rst:272 types/bool.rst:306 msgid "Return" msgstr "返回类型" @@ -186,10 +179,9 @@ msgstr "Bool(value: Boolean)" #: ../../SpinalHDL/Data types/bool.rst:78 msgid "" -"Create a Bool assigned with a value from a Scala Boolean type (true, false)." -" This explicitly converts to ``True`` or ``False``." -msgstr "创建一个 Bool，并分配一个 Scala 布尔类型（true、false）的值。这显式地转换为 " -"``True`` 或 ``False`` 。" +"Create a Bool assigned with a value from a Scala Boolean type (true, " +"false). This explicitly converts to ``True`` or ``False``." +msgstr "创建一个 Bool，并分配一个 Scala 布尔类型（true、false）的值。这显式地转换为 ``True`` 或 ``False`` 。" #: ../../SpinalHDL/Data types/bool.rst:93 msgid "Operators" @@ -316,21 +308,20 @@ msgstr "边缘检测" #: ../../SpinalHDL/Data types/bool.rst:175 msgid "" "All edge detection functions will instantiate an additional register via " -":ref:`RegNext ` to get a delayed value of the ``Bool`` in question." -msgstr "" -"所有边缘检测函数都将通过 :ref:`RegNext ` 实例化一个附加寄存器，" -"以获取相关 ``Bool`` 的延迟值（一拍）。" +":ref:`RegNext ` to get a delayed value of the ``Bool`` in " +"question." +msgstr "所有边缘检测函数都将通过 :ref:`RegNext ` 实例化一个附加寄存器，以获取相关 ``Bool`` 的延迟值（一拍）。" #: ../../SpinalHDL/Data types/bool.rst:178 msgid "" -"This feature does not reconfigure a D-type Flip-Flop to use an alternative " -"CLK source, it uses two D-type Flip-Flop in series chain (with both CLK pins" -" inheriting the default ClockDomain). It has combinational logic to perform" -" edge detection based on the output Q states." +"This feature does not reconfigure a D-type Flip-Flop to use an " +"alternative CLK source, it uses two D-type Flip-Flop in series chain " +"(with both CLK pins inheriting the default ClockDomain). It has " +"combinational logic to perform edge detection based on the output Q " +"states." msgstr "" -"此功能不会重新配置 D 型触发器以使用其他 CLK 时钟，它使用串联链中的两个 D " -"型触发器（两个 CLK 引脚都继承默认的 ClockDomain）。它具有组合逻辑，" -"可根据输出 Q 状态进行边缘检测。" +"此功能不会重新配置 D 型触发器以使用其他 CLK 时钟，它使用串联链中的两个 D 型触发器（两个 CLK 引脚都继承默认的 " +"ClockDomain）。它具有组合逻辑，可根据输出 Q 状态进行边缘检测。" #: ../../SpinalHDL/Data types/bool.rst:190 msgid "x.edge[()]" @@ -474,8 +465,8 @@ msgstr "x.asUInt(bitCount)" #: ../../SpinalHDL/Data types/bool.rst:283 msgid "" -"Binary cast to UInt and resize, putting Bool value in LSB and padding with " -"zeros." +"Binary cast to UInt and resize, putting Bool value in LSB and padding " +"with zeros." msgstr "二进制转换为 UInt 并调整大小，将 Bool 值放入 LSB 并用零填充。" #: ../../SpinalHDL/Data types/bool.rst:285 @@ -488,8 +479,8 @@ msgstr "x.asBits(bitCount)" #: ../../SpinalHDL/Data types/bool.rst:287 msgid "" -"Binary cast to Bits and resize, putting Bool value in LSB and padding with " -"zeros." +"Binary cast to Bits and resize, putting Bool value in LSB and padding " +"with zeros." msgstr "二进制转换为位并调整大小，将布尔值放入 LSB 并用零填充。" #: ../../SpinalHDL/Data types/bool.rst:289 @@ -533,8 +524,8 @@ msgid "" "A masked boolean allows don’t care values. They are usually not used on " "their own but through :ref:`MaskedLiteral `." msgstr "" -"具有掩码的布尔型允许任意值（don't care）。它们通常不单独使用，而是通过 :ref:`" -"MaskedLiteral ` 使用。" +"具有掩码的布尔型允许任意值（don't care）。它们通常不单独使用，而是通过 :ref:`MaskedLiteral " +"` 使用。" #~ msgid "The ``Bool`` type corresponds to a boolean value (True or False)." #~ msgstr "“Bool” 类型对应于布尔值（True 或 False）。" @@ -544,3 +535,4 @@ msgstr "" #~ msgid "Binary cast to Bits and resize" #~ msgstr "二进制转换为位并调整大小" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po index 65d5126113a..494434705d8 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po @@ -1,26 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"POT-Creation-Date: 2024-01-26 16:21+0000\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-26 17:04+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Data types/index.rst:5 msgid "Data types" @@ -62,12 +62,12 @@ msgid ":ref:`Floating-point ` numbers (experimental support)" msgstr ":ref:`Floating-point ` 浮点小数（实验性支持）" #: ../../SpinalHDL/Data types/index.rst:22 +#, fuzzy msgid "" -"Additionaly, if you want to assign a don't care value to some hardware, " +"Additionally, if you want to assign a don't care value to some hardware, " "for instance, to provide a default value, you can use the assignDontCare " "API to do so." -msgstr "此外，如果您想为某些硬件分配一个 \"不关心 \"值，例如提供一个默认值，可以使用 " -"assignDontCare API 来实现。" +msgstr "此外，如果您想为某些硬件分配一个 \"不关心 \"值，例如提供一个默认值，可以使用 assignDontCare API 来实现。" #: ../../SpinalHDL/Data types/index.rst:31 msgid "" @@ -84,3 +84,4 @@ msgstr "下面是一个示例，展示如何实现此目的（注意使用“M #~ msgid "Introduction" #~ msgstr "介绍" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po index b79f9487e95..0c32551dad5 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-18 07:38+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.3\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:3 msgid "SpinalHDL internal datamodel" @@ -29,11 +32,10 @@ msgstr "简介" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:12 msgid "" -"This page provides documentation on the internal data structure utilized by " -"SpinalHDL for storing and modifying the netlist described by users via the " -"SpinalHDL API." -msgstr "本页面提供有关 SpinalHDL 使用的内部数据结构的文档，用于存储和修改用户通过 " -"SpinalHDL API 描述的网表。" +"This page provides documentation on the internal data structure utilized " +"by SpinalHDL for storing and modifying the netlist described by users via" +" the SpinalHDL API." +msgstr "本页面提供有关 SpinalHDL 使用的内部数据结构的文档，用于存储和修改用户通过 SpinalHDL API 描述的网表。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:15 msgid "General structure" @@ -61,8 +63,8 @@ msgstr "``* `` 符号表示“多个”" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:24 msgid "" -"The majority of the data structures are stored using double-linked lists, " -"which facilitate the insertion and removal of elements." +"The majority of the data structures are stored using double-linked lists," +" which facilitate the insertion and removal of elements." msgstr "大多数数据结构都是使用双向链表存储，这方便了元素的插入和删除。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:26 @@ -75,13 +77,13 @@ msgstr "这里是关于 `Statement` 类的更多细节：" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:36 msgid "" -"In general, when an element within the data model utilizes other expressions" -" or statements, that element typically includes functions for iterating over" -" these usages. For example, each Expression is equipped with a " -"*foreachExpression* function." +"In general, when an element within the data model utilizes other " +"expressions or statements, that element typically includes functions for " +"iterating over these usages. For example, each Expression is equipped " +"with a *foreachExpression* function." msgstr "" -"一般来说，当数据模型内的元素使用其他表达式或语句时，该元素通常包括迭代这些用" -"法的函数。例如，每个表达式都配有一个 *foreachExpression* 函数。" +"一般来说，当数据模型内的元素使用其他表达式或语句时，该元素通常包括迭代这些用法的函数。例如，每个表达式都配有一个 " +"*foreachExpression* 函数。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:38 msgid "" @@ -91,35 +93,34 @@ msgstr "使用这些迭代函数时，您也可以从树中删除当前元素。 #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:40 msgid "" -"Additionally, as a side note, while the *foreachXXX* functions iterate only " -"one level deep, there are often corresponding *walkXXX* functions that " -"perform recursive iteration. For instance, using " -"*myExpression.walkExpression* on *((a+b)+c)+d* will traverse the entire tree" -" of addition operations." +"Additionally, as a side note, while the *foreachXXX* functions iterate " +"only one level deep, there are often corresponding *walkXXX* functions " +"that perform recursive iteration. For instance, using " +"*myExpression.walkExpression* on *((a+b)+c)+d* will traverse the entire " +"tree of addition operations." msgstr "" -"此外，作为旁注，虽然 *foreachXXX* 函数仅迭代一层深度，但通常有相应的 " -"*walkXXX* 函数执行递归迭代。例如，在 *((a+b)+c)+d* 表达式上使用 *myExpression" -".walkExpression* ，这将遍历整个加法运算树。" +"此外，作为旁注，虽然 *foreachXXX* 函数仅迭代一层深度，但通常有相应的 *walkXXX* 函数执行递归迭代。例如，在 " +"*((a+b)+c)+d* 表达式上使用 *myExpression.walkExpression* ，这将遍历整个加法运算树。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:42 msgid "" -"There are also utilities like *myExpression.remapExpressions(Expression => " -"Expression),* which iterate through all the expressions used within " +"There are also utilities like *myExpression.remapExpressions(Expression " +"=> Expression),* which iterate through all the expressions used within " "*myExpression* and replace them with the one you provide." msgstr "" "还有像 *myExpression.remapExpressions(Expression => Expression),* " -"这样的实用工具，它会迭代 *myExpression* " -"中使用的所有表达式，并将它们替换为您提供的表达式。" +"这样的实用工具，它会迭代 *myExpression* 中使用的所有表达式，并将它们替换为您提供的表达式。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:44 +#, fuzzy msgid "" -"More generaly, most of the graph checks and transformations done by " +"More generally, most of the graph checks and transformations done by " "SpinalHDL are located in " "" msgstr "" -"通常来说，SpinalHDL 完成的大多数图(graph)关系检查和转换都位于 " +"通常来说，SpinalHDL 完成的大多数图(graph)关系检查和转换都位于 " +"" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:47 msgid "Exploring the datamodel" @@ -137,10 +138,10 @@ msgstr "这将生成：" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:127 msgid "" -"Please note that in many cases, shortcuts are available. All the recursive " -"processes mentioned earlier could have been replaced by a single one. :" -msgstr "请注意，在许多情况下，都可以使用快捷方式。前面提到的所有递归过程，都可以用一" -"个递归过程代替。 ：" +"Please note that in many cases, shortcuts are available. All the " +"recursive processes mentioned earlier could have been replaced by a " +"single one. :" +msgstr "请注意，在许多情况下，都可以使用快捷方式。前面提到的所有递归过程，都可以用一个递归过程代替。 ：" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:141 msgid "Compilation Phases" @@ -151,41 +152,36 @@ msgid "" "Here is the complete list of default phases, arranged in order, that are " "employed to modify, check, and generate Verilog code from a top-level " "component. :" -msgstr "以下是按顺序排列的默认环节的完整列表，用于从顶级组件修改、检查和生成 Verilog " -"代码。 ：" +msgstr "以下是按顺序排列的默认环节的完整列表，用于从顶级组件修改、检查和生成 Verilog 代码。 ：" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:145 -msgid "" -"" -msgstr "" -"" +msgid "" +msgstr "" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:147 msgid "" "If you, as a user, add a new compilation phase by using " "*SpinalConfig.addTransformationPhase(new MyPhase())*, this phase will be " -"inserted immediately after the user component elaboration process, which is " -"relatively early in the compilation sequence. During this phase, you can " -"still make use of the complete SpinalHDL user API to introduce elements into" -" the netlist." +"inserted immediately after the user component elaboration process, which " +"is relatively early in the compilation sequence. During this phase, you " +"can still make use of the complete SpinalHDL user API to introduce " +"elements into the netlist." msgstr "" -"如果您作为用户使用 *SpinalConfig.addTransformationPhase(new MyPhase())* 添加" -"新的编译环节，则该环节将在用户组件实例细化后立即插入，这在编译序列中相对较早" -"。在此环节，您仍然可以使用完整的 SpinalHDL 用户 API 将元素引入网表。" +"如果您作为用户使用 *SpinalConfig.addTransformationPhase(new MyPhase())* " +"添加新的编译环节，则该环节将在用户组件实例细化后立即插入，这在编译序列中相对较早。在此环节，您仍然可以使用完整的 SpinalHDL 用户 API" +" 将元素引入网表。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:149 msgid "" -"If you choose to use the SpinalConfig.phasesInserters API, it's essential to" -" exercise caution and ensure that any modifications made to the netlist " -"align with the phases that have already been executed. For instance, if you " -"insert your phase after the *PhaseInferWidth*, you must specify the width of" -" each node you introduce." +"If you choose to use the SpinalConfig.phasesInserters API, it's essential" +" to exercise caution and ensure that any modifications made to the " +"netlist align with the phases that have already been executed. For " +"instance, if you insert your phase after the *PhaseInferWidth*, you must " +"specify the width of each node you introduce." msgstr "" "如果您选择使用 SpinalConfig.phasesInserters " -"API，则必须谨慎行事并确保对网表所做的任何修改与已执行的阶段保持一致。例如，" -"如果您在 *PhaseInferWidth* 之后插入环节，则必须指定引入的每个节点的位宽。" +"API，则必须谨慎行事并确保对网表所做的任何修改与已执行的阶段保持一致。例如，如果您在 *PhaseInferWidth* " +"之后插入环节，则必须指定引入的每个节点的位宽。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:152 msgid "Modifying a netlist as a user without plugins" @@ -193,8 +189,8 @@ msgstr "在不使用插件的情况下，以用户身份修改网表" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:154 msgid "" -"There are several user APIs that enable you to make modifications during the" -" user elaboration phase. :" +"There are several user APIs that enable you to make modifications during " +"the user elaboration phase. :" msgstr "有多个用户 API 使您能够在用户实例细化环节进行修改。 ：" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:156 @@ -204,13 +200,14 @@ msgid "" msgstr "mySignal.removeAssignments ：将删除所有先前对给定信号的赋值 `:=`" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:157 -msgid "mySignal.removeStatement : Will void the existance of the signal" +#, fuzzy +msgid "mySignal.removeStatement : Will void the existence of the signal" msgstr "mySignal.removeStatement：将消除存在的信号" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:158 msgid "" -"mySignal.setAsDirectionLess : Will turn a in / out signal into a internal " -"signal" +"mySignal.setAsDirectionLess : Will turn a in / out signal into a internal" +" signal" msgstr "mySignal.setAsDirectionLess ：将输入/输出信号转换为内部信号（无方向）" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:159 @@ -221,26 +218,24 @@ msgstr "mySignal.setName ：在信号上强制指定名称（还有许多其他 #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:160 msgid "" -"mySubComponent.mySignal.pull() : Will provide a readable copy of the given " -"signal, even if that signal is somewhere else in the hierarchy" -msgstr "mySubComponent.mySignal.pull() " -"：将提供给定信号的可读副本，即使该信号位于层次结构中的其他位置" +"mySubComponent.mySignal.pull() : Will provide a readable copy of the " +"given signal, even if that signal is somewhere else in the hierarchy" +msgstr "mySubComponent.mySignal.pull() ：将提供给定信号的可读副本，即使该信号位于层次结构中的其他位置" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:161 msgid "" "myComponent.rework\\{ myCode \\} : Execute `myCode` in the context of " "`myComponent`, allowing modifying it with the user API" msgstr "" -"myComponent.rework\\{ myCode \\} ：在 `myComponent` 上下文中执行 `myCode`，" -"允许使用用户 API 修改它" +"myComponent.rework\\{ myCode \\} ：在 `myComponent` 上下文中执行 `myCode`，允许使用用户 " +"API 修改它" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:163 msgid "" -"For example, the following code can be used to modify a top-level component " -"by adding a three-stage shift register to each input and output of the " -"component. This is particularly useful for synthesis testing." -msgstr "例如，以下代码可用于修改顶级组件，向组件的每个输入和输出添加三级移位寄存器。" -"这对于综合器测试特别有用。" +"For example, the following code can be used to modify a top-level " +"component by adding a three-stage shift register to each input and output" +" of the component. This is particularly useful for synthesis testing." +msgstr "例如，以下代码可用于修改顶级组件，向组件的每个输入和输出添加三级移位寄存器。这对于综合器测试特别有用。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:187 msgid "You can use the code in the following manner: :" @@ -249,12 +244,10 @@ msgstr "您可以通过以下方式使用该代码：" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:193 msgid "" "Here is a function that enables you to execute the body code as if the " -"current component's context did not exist. This can be particularly useful " -"for defining new signals without the influence of the current conditional " -"scope (such as when or switch)." -msgstr "" -"这是一个函数，使您能够执行主体代码，就好像当前组件的上下文不存在一样。这对于" -"定义新信号特别有用，这样信号不受当前条件范围（例如when或switch）的影响。" +"current component's context did not exist. This can be particularly " +"useful for defining new signals without the influence of the current " +"conditional scope (such as when or switch)." +msgstr "这是一个函数，使您能够执行主体代码，就好像当前组件的上下文不存在一样。这对于定义新信号特别有用，这样信号不受当前条件范围（例如when或switch）的影响。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:223 msgid "" @@ -268,13 +261,14 @@ msgstr "用户空间网表分析" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:228 msgid "" -"The SpinalHDL data model is also accessible and can be read during user-time" -" elaboration. Here's an example that can help find the shortest logical path" -" (in terms of clock cycles) to traverse a list of signals. In this specific " -"case, it is being used to analyze the latency of the VexRiscv FPU design." +"The SpinalHDL data model is also accessible and can be read during user-" +"time elaboration. Here's an example that can help find the shortest " +"logical path (in terms of clock cycles) to traverse a list of signals. In" +" this specific case, it is being used to analyze the latency of the " +"VexRiscv FPU design." msgstr "" -"SpinalHDL 的数据模型也是可访问的，并且可以在用户实力细化时读取。下面的示例可" -"以帮助找到遍历信号列表的最短逻辑路径（就时钟周期而言）。在本例中，它用于分析 " +"SpinalHDL " +"的数据模型也是可访问的，并且可以在用户实力细化时读取。下面的示例可以帮助找到遍历信号列表的最短逻辑路径（就时钟周期而言）。在本例中，它用于分析 " "VexRiscv FPU 设计的延迟。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:242 @@ -282,9 +276,8 @@ msgid "" "Here you can find the implementation of that LatencyAnalysis tool : " "" msgstr "" -"在这里您可以找到该 LatencyAnalysis 工具的实现：" +"在这里您可以找到该 LatencyAnalysis " +"工具的实现：" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:247 msgid "Enumerating every ClockDomain in use" @@ -299,3 +292,4 @@ msgstr "在本例中，这是在实例细化完成之后利用 SpinalHDL 报告 #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:285 msgid "Will print out" msgstr "打印信息是" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po index d3ab607d47b..82916260fa9 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Developers area/types.rst:3 msgid "Types" @@ -28,16 +31,14 @@ msgid "Introduction" msgstr "简介" #: ../../SpinalHDL/Developers area/types.rst:12 -msgid "" -"The language provides 5 base types and 2 composite types that can be used." +msgid "The language provides 5 base types and 2 composite types that can be used." msgstr "该语言提供了 5 种基本类型和 2 种复合类型。" #: ../../SpinalHDL/Developers area/types.rst:15 msgid "" -"Base types : ``Bool``, ``Bits``, ``UInt`` for unsigned integers, ``SInt`` " -"for signed integers, ``Enum``." -msgstr "基本类型： ``Bool``、``Bits``、 ``UInt`` " -"（无符号整数）、``SInt``（有符号整数）、 ``Enum``。" +"Base types : ``Bool``, ``Bits``, ``UInt`` for unsigned integers, ``SInt``" +" for signed integers, ``Enum``." +msgstr "基本类型： ``Bool``、``Bits``、 ``UInt`` （无符号整数）、``SInt``（有符号整数）、 ``Enum``。" #: ../../SpinalHDL/Developers area/types.rst:16 msgid "Composite types : Bundle, Vec." @@ -255,17 +256,17 @@ msgstr "BitVector 系列 - (``Bits``, ``UInt``, ``SInt``)" #: ../../SpinalHDL/Developers area/types.rst:120 msgid "" -"``BitVector`` is a family of types for storing multiple bits of information " -"in a single value. This type has three subtypes that can be used to model " -"different behaviours:" -msgstr "``BitVector`` 是一个系列的类型，用于在单个值中存储多位信息。该类型具有三个子" -"类型，可用于描述不同的行为：" +"``BitVector`` is a family of types for storing multiple bits of " +"information in a single value. This type has three subtypes that can be " +"used to model different behaviours:" +msgstr "``BitVector`` 是一个系列的类型，用于在单个值中存储多位信息。该类型具有三个子类型，可用于描述不同的行为：" #: ../../SpinalHDL/Developers area/types.rst:121 msgid "" -"``Bits`` do not convey any sign information whereas the ``UInt`` (unsigned " -"integer) and ``SInt`` (signed integer) provide the required operations to " -"compute correct results if signed / unsigned arithmetic is used." +"``Bits`` do not convey any sign information whereas the ``UInt`` " +"(unsigned integer) and ``SInt`` (signed integer) provide the required " +"operations to compute correct results if signed / unsigned arithmetic is " +"used." msgstr "" "``Bits`` 不传达任何符号信息，而 ``UInt`` （无符号整数）和 ``SInt`` " "（有符号整数）提供了计算正确结果所需的操作（如果使用有符号/无符号算术）。" @@ -313,8 +314,8 @@ msgstr "B/U/S([x bits], element, ...)" #: ../../SpinalHDL/Developers area/types.rst:146 msgid "" -"Create a BitVector assigned with the value specified by elements (see the " -"table below)" +"Create a BitVector assigned with the value specified by elements (see the" +" table below)" msgstr "创建一个 BitVector信号，并为各元素赋值（见下表）" #: ../../SpinalHDL/Developers area/types.rst:150 @@ -367,8 +368,7 @@ msgid "Set all unconnected bits with the y value." msgstr "使用 y 值设置所有未连接的位。" #: ../../SpinalHDL/Developers area/types.rst -msgid "" -"This feature can only be used to do assignments without the U/B/S prefix" +msgid "This feature can only be used to do assignments without the U/B/S prefix" msgstr "此功能只能用于对没有 U/B/S 前缀信号的赋值" #: ../../SpinalHDL/Developers area/types.rst:174 @@ -627,10 +627,9 @@ msgstr "掩码过滤结果比较" #: ../../SpinalHDL/Developers area/types.rst:297 msgid "" "Sometimes you need to check equality between a ``BitVector`` and a bits " -"constant that contain holes defined as a bitmask (bit positions not to be " -"compared by the equality expression)." -msgstr "有时候，你需要检查一个 ``BitVector`` " -"和一个包含空位（不需要进行相等性表达式比较的位）的位掩码之间的相等性。" +"constant that contain holes defined as a bitmask (bit positions not to be" +" compared by the equality expression)." +msgstr "有时候，你需要检查一个 ``BitVector`` 和一个包含空位（不需要进行相等性表达式比较的位）的位掩码之间的相等性。" #: ../../SpinalHDL/Developers area/types.rst:300 msgid "An example demonstrating how to do that (note the use of 'M' prefix) :" @@ -696,10 +695,9 @@ msgstr "x.resize(y)" #: ../../SpinalHDL/Developers area/types.rst:333 msgid "" -"Return a resized copy of x, filled with zero bits as necessary at the MSB to" -" widen, may also truncate width retaining at the LSB side, y : Int" -msgstr "返回调整位宽后的 x，根据需要在 MSB 处填充零位以加大位宽，也可以截断保留在 " -"LSB 侧的宽度，y : Int" +"Return a resized copy of x, filled with zero bits as necessary at the MSB" +" to widen, may also truncate width retaining at the LSB side, y : Int" +msgstr "返回调整位宽后的 x，根据需要在 MSB 处填充零位以加大位宽，也可以截断保留在 LSB 侧的宽度，y : Int" #: ../../SpinalHDL/Developers area/types.rst:335 area/types.rst:339 #: area/types.rst:387 @@ -712,10 +710,9 @@ msgstr "x.resizeLeft(y)" #: ../../SpinalHDL/Developers area/types.rst:337 msgid "" -"Return a resized copy of x, filled with zero bits as necessary at the LSB to" -" widen, may also truncate width retraining at the MSB side, y : Int" -msgstr "返回调整位宽的 x，根据需要在 LSB 处填充零位以加大位宽，也可以在 MSB " -"端截断宽度，y : Int" +"Return a resized copy of x, filled with zero bits as necessary at the LSB" +" to widen, may also truncate width retraining at the MSB side, y : Int" +msgstr "返回调整位宽的 x，根据需要在 LSB 处填充零位以加大位宽，也可以在 MSB 端截断宽度，y : Int" #: ../../SpinalHDL/Developers area/types.rst:343 msgid "UInt, SInt" @@ -890,14 +887,13 @@ msgid "Bundle" msgstr "Bundle" #: ../../SpinalHDL/Developers area/types.rst:462 -msgid "" -"Bundles could be used to model data structure line buses and interfaces." +msgid "Bundles could be used to model data structure line buses and interfaces." msgstr "线束可用于对数据结构信号总线和接口进行建模。" #: ../../SpinalHDL/Developers area/types.rst:463 msgid "" -"All attributes that extends Data (Bool, Bits, UInt, ...) that are defined " -"inside the bundle are considered as part of the bundle." +"All attributes that extends Data (Bool, Bits, UInt, ...) that are defined" +" inside the bundle are considered as part of the bundle." msgstr "线束内定义的所有数据属性（Bool、Bits、UInt...）都被视为线束的一部分。" #: ../../SpinalHDL/Developers area/types.rst:466 @@ -912,17 +908,19 @@ msgstr "以下示例显示了具有某些内部函数的 RGB 线束的定义。" #: ../../SpinalHDL/Developers area/types.rst:484 msgid "" -"Then you can also incorporate a Bundle inside Bundle as deeply as you want:" +"Then you can also incorporate a Bundle inside Bundle as deeply as you " +"want:" msgstr "然后，您还可以根据需要将一个线束实例放置在另一个线束中（没有深度限制）：" #: ../../SpinalHDL/Developers area/types.rst:494 -msgid "And finaly instantiate your Bundles inside the hardware :" +#, fuzzy +msgid "And finally instantiate your Bundles inside the hardware :" msgstr "最后在硬件中实例化您的线束：" #: ../../SpinalHDL/Developers area/types.rst:504 msgid "" -"If you want to specify your bundle as an input or an output of a Component, " -"you have to do it by the following way :" +"If you want to specify your bundle as an input or an output of a " +"Component, you have to do it by the following way :" msgstr "如果想将你的线束指定为组件的输入或输出，你必须通过以下方式来完成：" #: ../../SpinalHDL/Developers area/types.rst:518 @@ -931,41 +929,36 @@ msgstr "接口示例（APB）" #: ../../SpinalHDL/Developers area/types.rst:520 msgid "" -"If you want to define an interface, let's imagine an APB interface, you can " -"also use bundles :" +"If you want to define an interface, let's imagine an APB interface, you " +"can also use bundles :" msgstr "如果你想定义一个接口，比如一个APB接口，就可以使用线束：" #: ../../SpinalHDL/Developers area/types.rst:546 msgid "" "One good practice is to group all construction parameters inside a " -"configuration class. This could make the parametrization much easier later " -"in your components, especially if you have to reuse the same configuration " -"at multiple places. Also if one time you need to add another construction " -"parameter, you will only have to add it into the configuration class and " -"everywhere this one is instantiated:" -msgstr "" -"一种好的做法是将所有构造参数分组到一个配置类中。这可以使组件中的参数化变得更" -"加容易，特别是当您必须在多个位置重用相同的配置时。另外，如果您需要添加另一个" -"构造参数，您只需将其添加到配置类中，并且在任何地方都可以实例化该参数：" +"configuration class. This could make the parametrization much easier " +"later in your components, especially if you have to reuse the same " +"configuration at multiple places. Also if one time you need to add " +"another construction parameter, you will only have to add it into the " +"configuration class and everywhere this one is instantiated:" +msgstr "一种好的做法是将所有构造参数分组到一个配置类中。这可以使组件中的参数化变得更加容易，特别是当您必须在多个位置重用相同的配置时。另外，如果您需要添加另一个构造参数，您只需将其添加到配置类中，并且在任何地方都可以实例化该参数：" #: ../../SpinalHDL/Developers area/types.rst:573 msgid "" -"Then at some points, you will probably need to use the APB bus as master or " -"as slave interface of some components. To do that you can define some " +"Then at some points, you will probably need to use the APB bus as master " +"or as slave interface of some components. To do that you can define some " "functions :" -msgstr "然后在某些时候，您可能需要使用 APB " -"总线作为某些组件的主端接口或从端接口。为此，您可以定义一些函数：" +msgstr "然后在某些时候，您可能需要使用 APB 总线作为某些组件的主端接口或从端接口。为此，您可以定义一些函数：" #: ../../SpinalHDL/Developers area/types.rst:611 msgid "" "Then to make that better, the spinal.lib integrates a small master slave " -"utility named IMasterSlave. When a bundle extends IMasterSlave, it should " -"implement/override the asMaster function. It give you the ability to setup a" -" master or a slave interface in a smoother way :" +"utility named IMasterSlave. When a bundle extends IMasterSlave, it should" +" implement/override the asMaster function. It give you the ability to " +"setup a master or a slave interface in a smoother way :" msgstr "" -"更进一步优化，spine.lib 中集成了一个名为 IMasterSlave 的小型主、从端口定义工" -"具。当线束扩展IMasterSlave时，它应该实现/覆盖asMaster函数，以便设置主端接口或" -"从端接口中的信号方向：" +"更进一步优化，spine.lib 中集成了一个名为 IMasterSlave " +"的小型主、从端口定义工具。当线束扩展IMasterSlave时，它应该实现/覆盖asMaster函数，以便设置主端接口或从端接口中的信号方向：" #: ../../SpinalHDL/Developers area/types.rst:622 msgid "An example of an APB bus that implement this IMasterSlave :" @@ -1017,8 +1010,8 @@ msgstr "stateCount" #: ../../SpinalHDL/Developers area/types.rst:673 msgid "" -"Use Bits to store state. Each bit position corresponds to one state, only " -"one bit is active at a time when encoded." +"Use Bits to store state. Each bit position corresponds to one state, only" +" one bit is active at a time when encoded." msgstr "使用位来存储状态。每个位对应一种状态，编码时一次只有一位有效。" #: ../../SpinalHDL/Developers area/types.rst:677 @@ -1027,8 +1020,8 @@ msgstr "定义一个枚举类型：" #: ../../SpinalHDL/Developers area/types.rst:685 msgid "" -"Instantiate a signal to store the enumeration encoded value and assign it a " -"value :" +"Instantiate a signal to store the enumeration encoded value and assign it" +" a value :" msgstr "实例化一个信号来存储枚举编码值并为其赋值：" #: ../../SpinalHDL/Developers area/types.rst:697 @@ -1135,8 +1128,8 @@ msgstr "使用字面量声明信号" #: ../../SpinalHDL/Developers area/types.rst:745 msgid "" -"Literals are generally use as a constant value. But you can also use them to" -" do two things in a single one :" +"Literals are generally use as a constant value. But you can also use them" +" to do two things in a single one :" msgstr "字面量通常用作常量值。但您也可以使用它们一次完成两件事：" #: ../../SpinalHDL/Developers area/types.rst:748 @@ -1157,8 +1150,7 @@ msgstr "当条件 `cond =/= True` 满足的时钟周期，将信号重新设置 msgid "" "Clock cycles where `cond === True` will result in the signal having the " "value of `red` due to the last statement wins rule." -msgstr "由于最后一条语句获胜规则，满足 `cond === True` " -"条件的时钟周期将导致信号具有“red”值。" +msgstr "由于最后一条语句获胜规则，满足 `cond === True` 条件的时钟周期将导致信号具有“red”值。" #: ../../SpinalHDL/Developers area/types.rst:754 msgid "An example :" @@ -1197,3 +1189,4 @@ msgstr "这里是一个例子：" #~ msgid "Return a resized copy of x, filled with zero, y : Int" #~ msgstr "返回 x 的调整大小副本，用零填充，y : Int" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po index d347b465169..d37d998f0d3 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po @@ -1,19 +1,23 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-31 10:03+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:4 msgid "Slots" @@ -25,14 +29,13 @@ msgstr "简介" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:9 msgid "" -"Let's say you have some hardware which has to keep track of multiple similar" -" ongoing activities, you may want to implement an array of \"slots\" to do " -"so. This example show how to do it using Area, OHMasking.first, onMask and " -"reader." +"Let's say you have some hardware which has to keep track of multiple " +"similar ongoing activities, you may want to implement an array of " +"\"slots\" to do so. This example show how to do it using Area, " +"OHMasking.first, onMask and reader." msgstr "" -"假设您有一些硬件必须跟踪多个相似的正在进行的活动，您可能需要实现一组“插槽”来" -"执行此操作。此示例展示如何使用 Area、OHMasking." -"first、onMask和reader来完成此操作。" +"假设您有一些硬件必须跟踪多个相似的正在进行的活动，您可能需要实现一组“插槽”来执行此操作。此示例展示如何使用 " +"Area、OHMasking.first、onMask和reader来完成此操作。" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:13 msgid "Implementation" @@ -40,14 +43,13 @@ msgstr "实现" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:15 msgid "" -"This implementation avoid the use of Vec. Instead, it use Area which allow " -"to mix signal, registers and logic definitions in each slot." -msgstr "此实现避免使用Vec。相反，它使用允许在每个插槽中混合信号、寄存器和逻辑定义的逻" -"辑区。" +"This implementation avoid the use of Vec. Instead, it use Area which " +"allow to mix signal, registers and logic definitions in each slot." +msgstr "此实现避免使用Vec。相反，它使用允许在每个插槽中混合信号、寄存器和逻辑定义的逻辑区。" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:17 -msgid "" -"Note that the `reader` API is for SpinalHDL version comming after 1.9.1" +#, fuzzy +msgid "Note that the `reader` API is for SpinalHDL version coming after 1.9.1" msgstr "请注意， `reader` API 适用于1.9.1之后推出的SpinalHDL版本" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:24 @@ -56,39 +58,31 @@ msgstr "应用" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:26 msgid "" -"For instance, this kind of slot pattern is used in Tilelink coherency hub to" -" keep track of all ongoing memory probes in flight:" -msgstr "例如，在Tilelink总线（具有一致性机制）hub中，这种插槽模式用于跟踪所有正在进行" -"的内存操作：" +"For instance, this kind of slot pattern is used in Tilelink coherency hub" +" to keep track of all ongoing memory probes in flight:" +msgstr "例如，在Tilelink总线（具有一致性机制）hub中，这种插槽模式用于跟踪所有正在进行的内存操作：" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:28 -msgid "" -"https://github.com/SpinalHDL/SpinalHDL/blob/008c73f1ce18e294f137efe7a1442bd3f8fa2ee0/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Hub.scala#L376" -msgstr "" -"https://github.com/SpinalHDL/SpinalHDL/blob/" -"008c73f1ce18e294f137efe7a1442bd3f8fa2ee0/lib/src/main/scala/spinal/lib/bus/" -"tilelink/coherent/Hub.scala#L376" +msgid "https://github.com/SpinalHDL/SpinalHDL/blob/008c73f1ce18e294f137efe7a1442bd3f8fa2ee0/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Hub.scala#L376" +msgstr "https://github.com/SpinalHDL/SpinalHDL/blob/008c73f1ce18e294f137efe7a1442bd3f8fa2ee0/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Hub.scala#L376" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:30 +#, fuzzy msgid "" -"As well in the DRAM / SDR / DDR memory controller to implement the handeling" -" of multiple memory transactions at once (having multiple precharge / active" -" / read / write running at the same time to improve performances) :" -msgstr "以及在 DRAM / SDR / DDR 内存控制器中实现同时处理多个内存事务（同时运行多个预" -"充电/激活/读/写以提高性能）：" +"As well in the DRAM / SDR / DDR memory controller to implement the " +"handling of multiple memory transactions at once (having multiple " +"precharge / active / read / write running at the same time to improve " +"performances) :" +msgstr "以及在 DRAM / SDR / DDR 内存控制器中实现同时处理多个内存事务（同时运行多个预充电/激活/读/写以提高性能）：" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:32 -msgid "" -"https://github.com/SpinalHDL/SpinalHDL/blob/1edba1890b5f629b28e5171b3c449155337d2548/lib/src/main/scala/spinal/lib/memory/sdram/xdr/Tasker.scala#L202" -msgstr "" -"https://github.com/SpinalHDL/SpinalHDL/blob/" -"1edba1890b5f629b28e5171b3c449155337d2548/lib/src/main/scala/spinal/lib/" -"memory/sdram/xdr/Tasker.scala#L202" +msgid "https://github.com/SpinalHDL/SpinalHDL/blob/1edba1890b5f629b28e5171b3c449155337d2548/lib/src/main/scala/spinal/lib/memory/sdram/xdr/Tasker.scala#L202" +msgstr "https://github.com/SpinalHDL/SpinalHDL/blob/1edba1890b5f629b28e5171b3c449155337d2548/lib/src/main/scala/spinal/lib/memory/sdram/xdr/Tasker.scala#L202" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:34 msgid "" "As well in the NaxRiscv (out of order CPU) load-store-unit to handle the " -"store-queue / load-queue hardware (a bit too scary to show here in the doc " -"XD)" -msgstr "以及在NaxRiscv（乱序 CPU）的加载存储单元中处理存储队列/加载队列的硬件（难度有" -"些可怕，不宜在文档中展示XD）" +"store-queue / load-queue hardware (a bit too scary to show here in the " +"doc XD)" +msgstr "以及在NaxRiscv（乱序 CPU）的加载存储单元中处理存储队列/加载队列的硬件（难度有些可怕，不宜在文档中展示XD）" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po index 1921e7e8aab..ab9690ce2a5 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po @@ -1,368 +1,360 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-23 07:01+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:4 ones/timer.rst:12 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:4 ones/timer.rst:12 msgid "Timer" msgstr "计时器" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:7 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:7 msgid "Introduction" msgstr "简介" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:9 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:9 msgid "" "A timer module is probably one of the most basic pieces of hardware. But " "even for a timer, there are some interesting things that you can do with " "SpinalHDL. This example will define a simple timer component which " "integrates a bus bridging utile." -msgstr "" -"计时器模块可能是最基本的硬件模块之一。但即使对于计时器，您也可以使用SpinalHDL" -"做一些有趣的事情。这个示例将定义一个简单的计时器组件，其中集成了一个总线桥接" -"实用工具。" +msgstr "计时器模块可能是最基本的硬件模块之一。但即使对于计时器，您也可以使用SpinalHDL做一些有趣的事情。这个示例将定义一个简单的计时器组件，其中集成了一个总线桥接实用工具。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:14 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:14 msgid "So let's start with the ``Timer`` component." msgstr "那么让我们从 ``Timer`` 组件开始。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:17 -#: ones/timer.rst:84 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:17 ones/timer.rst:84 msgid "Specification" msgstr "规范" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:19 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:19 msgid "The ``Timer`` component will have a single construction parameter:" msgstr "``Timer`` 组件将具有一个构造参数：" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:25 -#: ones/timer.rst:92 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:25 ones/timer.rst:92 msgid "Parameter Name" msgstr "参数名称" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:26 -#: ones/timer.rst:41 ones/timer.rst:93 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:26 ones/timer.rst:41 +#: ones/timer.rst:93 msgid "Type" msgstr "类型" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:27 -#: ones/timer.rst:42 ones/timer.rst:94 ones/timer.rst:120 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:27 ones/timer.rst:42 +#: ones/timer.rst:94 ones/timer.rst:120 msgid "Description" msgstr "描述" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:28 -#: ones/timer.rst:135 ones/timer.rst:142 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:28 ones/timer.rst:135 +#: ones/timer.rst:142 msgid "width" msgstr "width" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:29 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:29 msgid "Int" msgstr "Int" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:30 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:30 msgid "Specify the bit width of the timer counter" msgstr "指定计时器计数器的位宽" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:33 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:33 msgid "And also some inputs/outputs:" msgstr "还有一些输入/输出：" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:39 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:39 msgid "IO Name" msgstr "IO名称" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:40 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:40 msgid "Direction" msgstr "方向" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:43 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:43 msgid "tick" msgstr "tick" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:44 -#: ones/timer.rst:48 ones/timer.rst:52 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:44 ones/timer.rst:48 +#: ones/timer.rst:52 msgid "in" msgstr "in" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:45 -#: ones/timer.rst:49 ones/timer.rst:57 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:45 ones/timer.rst:49 +#: ones/timer.rst:57 msgid "Bool" msgstr "Bool" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:46 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:46 msgid "When ``tick`` is True, the timer count up until ``limit``." msgstr "当 ``tick`` 为 True 时，计时器计数到 ``limit`` 。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:47 -#: ones/timer.rst:146 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:47 ones/timer.rst:146 msgid "clear" msgstr "clear" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:50 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:50 msgid "" -"When ``tick`` is True, the timer is set to zero. ``clear`` has priority over" -" ``tick``." +"When ``tick`` is True, the timer is set to zero. ``clear`` has priority " +"over ``tick``." msgstr "当 ``tick`` 为 True 时，计时器设为零。 ``clear`` 优先于 ``tick`` 。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:51 -#: ones/timer.rst:133 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:51 ones/timer.rst:133 msgid "limit" msgstr "limit" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:53 -#: ones/timer.rst:61 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:53 ones/timer.rst:61 msgid "UInt(width bits)" msgstr "UInt(width bits)" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:54 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:54 msgid "" "When the timer value is equal to ``limit``\\ , the ``tick`` input is " "inhibited." msgstr "当计时器值等于 ``limit`` 时，禁止 ``tick`` 输入。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:55 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:55 msgid "full" msgstr "full" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:56 -#: ones/timer.rst:60 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:56 ones/timer.rst:60 msgid "out" msgstr "out" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:58 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:58 msgid "" -"``full`` is high when the timer value is equal to ``limit`` and ``tick`` is " -"high." +"``full`` is high when the timer value is equal to ``limit`` and ``tick`` " +"is high." msgstr "当计时器值等于 ``limit`` 并且 ``tick`` 为高时，``full`` 为高。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:59 -#: ones/timer.rst:140 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:59 ones/timer.rst:140 msgid "value" msgstr "value" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:62 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:62 msgid "Wire out the timer counter value." msgstr "引出计时器的计数器值。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:66 -#: ones/timer.rst:155 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:66 ones/timer.rst:155 msgid "Implementation" msgstr "实现" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:75 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:75 msgid "Bridging function" msgstr "桥接函数" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:77 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:77 msgid "" "Now we can start with the main purpose of this example: defining a bus " "bridging function. To do that we will use two techniques:" -msgstr "现在我们可以从这个例子的主要目的开始：定义总线桥接功能。为此，我们将使用两种" -"技术：" +msgstr "现在我们可以从这个例子的主要目的开始：定义总线桥接功能。为此，我们将使用两种技术：" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:80 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:80 msgid "" "Using the ``BusSlaveFactory`` tool documented :ref:`here " "`" msgstr "使用在文档 :ref:`此处 ` 的 ``BusSlaveFactory`` 工具" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:81 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:81 msgid "" -"Defining a function inside the ``Timer`` component which can be called from " -"the parent component to drive the ``Timer``\\ 's IO in an abstract way." -msgstr "在 ``Timer`` 组件内定义一个函数，这个函数可以从父组件调用该函数，" -"并以抽象方式驱动 ``Timer`` 的 IO。" +"Defining a function inside the ``Timer`` component which can be called " +"from the parent component to drive the ``Timer``\\ 's IO in an abstract " +"way." +msgstr "在 ``Timer`` 组件内定义一个函数，这个函数可以从父组件调用该函数，并以抽象方式驱动 ``Timer`` 的 IO。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:86 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:86 msgid "This bridging function will take the following parameters:" msgstr "该桥接函数将使用以下参数：" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:95 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:95 msgid "busCtrl" msgstr "busCtrl" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:96 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:96 msgid "BusSlaveFactory" msgstr "BusSlaveFactory" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:97 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:97 msgid "" -"The ``BusSlaveFactory`` instance that will be used by the function to create" -" the bridging logic." +"The ``BusSlaveFactory`` instance that will be used by the function to " +"create the bridging logic." msgstr "函数将使用 ``BusSlaveFactory`` 实例来创建桥接逻辑。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:98 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:98 msgid "baseAddress" msgstr "baseAddress" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:99 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:99 msgid "BigInt" msgstr "BigInt" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:100 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:100 msgid "The base address where the bridging logic should be mapped." msgstr "桥接逻辑应映射到的基地址。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:101 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:101 msgid "ticks" msgstr "ticks" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:102 -#: ones/timer.rst:105 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:102 ones/timer.rst:105 msgid "Seq[Bool]" msgstr "Seq[Bool]" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:103 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:103 msgid "A list of Bool sources that can be used as a tick signal." msgstr "可用作tick信号的Bool源序列。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:104 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:104 msgid "clears" msgstr "clears" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:106 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:106 msgid "A list of Bool sources that can be used as a clear signal." msgstr "可用作clear信号的Bool源序列。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:109 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:109 msgid "The register mapping assumes that the bus system is 32 bits wide:" msgstr "假设寄存器映射的总线系统位宽是32位：" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:115 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:115 msgid "Name" msgstr "名称" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:116 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:116 msgid "Access" msgstr "访问" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:117 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:117 msgid "Width" msgstr "位宽" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:118 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:118 msgid "Address offset" msgstr "地址偏移" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:119 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:119 msgid "Bit offset" msgstr "位偏移" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:121 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:121 msgid "ticksEnable" msgstr "ticksEnable" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:122 -#: ones/timer.rst:128 ones/timer.rst:134 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:122 ones/timer.rst:128 +#: ones/timer.rst:134 msgid "RW" msgstr "RW" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:123 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:123 msgid "len(ticks)" msgstr "len(ticks)" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:124 -#: ones/timer.rst:125 ones/timer.rst:130 ones/timer.rst:137 ones/timer.rst:144 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:124 ones/timer.rst:125 +#: ones/timer.rst:130 ones/timer.rst:137 ones/timer.rst:144 msgid "0" msgstr "0" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:126 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:126 +#, fuzzy msgid "" -"Each ``ticks`` bool can be actived if the corresponding ``ticksEnable`` bit " -"is high." +"Each ``ticks`` bool can be activated if the corresponding ``ticksEnable``" +" bit is high." msgstr "每个 ``ticks`` 逻辑值都可以被相应的 ``ticksEnable`` 位取高激活。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:127 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:127 msgid "clearsEnable" msgstr "clearsEnable" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:129 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:129 msgid "len(clears)" msgstr "len(clears)" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:131 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:131 msgid "16" msgstr "16" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:132 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:132 +#, fuzzy msgid "" -"Each ``clears`` bool can be actived if the corresponding ``clearsEnable`` " -"bit is high." +"Each ``clears`` bool can be activated if the corresponding " +"``clearsEnable`` bit is high." msgstr "每个 ``clears`` 逻辑值都可以被相应的 ``clearsEnable`` 位取高激活。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:136 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:136 msgid "4" msgstr "4" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst msgid "Access the limit value of the timer component." msgstr "访问计时器组件的limit值。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst msgid "When this register is written to, the timer is cleared." msgstr "当写入该寄存器时，计时器清零。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:141 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:141 msgid "R" msgstr "R" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:143 -#: ones/timer.rst:149 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:143 ones/timer.rst:149 msgid "8" msgstr "8" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:145 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:145 msgid "Access the value of the timer." msgstr "访问计时器的值。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:147 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:147 msgid "W" msgstr "W" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:151 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:151 msgid "When this register is written to, it clears the timer." msgstr "当写入该寄存器时，计时器清零。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:157 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:157 msgid "Let's add this bridging function inside the ``Timer`` component." msgstr "让我们在 ``Timer`` 组件中添加这个桥接函数。" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:167 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:167 msgid "Usage" msgstr "用法" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:169 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:169 msgid "" -"Here is some demonstration code which is very close to the one used in the " -"Pinsec SoC timer module. Basically it instantiates following elements:" -msgstr "下面是一些演示代码，它与Pinsec " -"SoC计时器模块中使用的代码非常接近。基本上，它实例化了以下元素：" +"Here is some demonstration code which is very close to the one used in " +"the Pinsec SoC timer module. Basically it instantiates following " +"elements:" +msgstr "下面是一些演示代码，它与Pinsec SoC计时器模块中使用的代码非常接近。基本上，它实例化了以下元素：" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:171 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:171 msgid "One 16 bit prescaler" msgstr "1个16位预分频器" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:172 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:172 msgid "One 32 bit timer" msgstr "1个32位计时器" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:173 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:173 msgid "Three 16 bit timers" msgstr "3个16位计时器" -#: ../../source/SpinalHDL/Examples/Advanced ones/timer.rst:175 +#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:175 msgid "" "Then by using an ``Apb3SlaveFactory`` and functions defined inside the " "``Timer``\\ s, it creates bridging logic between the APB3 bus and all " @@ -370,3 +362,4 @@ msgid "" msgstr "" "然后，通过使用 ``Apb3SlaveFactory`` 和 ``Timer`` 内定义的函数，它在 APB3 " "总线和所有实例化组件之间创建桥接逻辑。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po index 0110cbe2b40..dfc72994613 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po @@ -1,23 +1,23 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" "Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" -"POT-Creation-Date: 2024-01-02 16:09+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-23 07:01+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:2 msgid "VGA" @@ -38,8 +38,8 @@ msgid "" "An explanation about the VGA protocol can be found `here " "`_." msgstr "" -"有关 VGA 协议的说明可以在 `此处 `_ 找到。" +"有关 VGA 协议的说明可以在 `此处 " +"`_ 找到。" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:11 msgid "" @@ -257,18 +257,20 @@ msgid "Horizontal and vertical logic" msgstr "水平和垂直逻辑" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:148 +#, fuzzy msgid "" "The logic that generates horizontal and vertical synchronization signals " "is quite the same. It kind of resembles ~PWM~. The horizontal one counts " -"up each cycle, while the vertical one use the horizontal syncronization " +"up each cycle, while the vertical one use the horizontal synchronization " "signal as to increment." msgstr "产生水平和垂直同步信号的逻辑完全相同，它有点类似于〜PWM〜。水平同步每周期计数一次，垂直同步则利用水平同步信号递增。" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:150 +#, fuzzy msgid "" "Let's define ``HVArea``\\ , which represents one ~PWM~ and then " "instantiate it two times: one for both horizontal and vertical " -"syncronization." +"synchronization." msgstr "让我们定义 ``HVArea`` ，它代表一个~PWM~，然后实例化它两次：一次用于水平同步，一次用于垂直同步。" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:160 @@ -318,3 +320,4 @@ msgid "" msgstr "" "让我们向 ``VgaCtrl`` 添加一个函数，可以从父组件调用该函数，以通过使用RGB的 ``Fragment`` 流 ``Stream`` " "来提供数据给 ``VgaCtrl`` 。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po index 3e46f3cd22d..c6ff136eebd 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-07 15:47+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.3-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Foreword/index.rst:4 msgid "Foreword" @@ -40,9 +43,10 @@ msgid "" msgstr "为了简洁，我们假设SystemVerilog是Verilog的最新版本。" #: ../../SpinalHDL/Foreword/index.rst:12 +#, fuzzy msgid "" -"When reading this, we should not underestimate how much our attachment for " -"our favourite HDL will bias our judgement." +"When reading this, we should not underestimate how much our attachment " +"for our favorite HDL will bias our judgement." msgstr "当我们阅读这段话时，我们不应低估最喜欢的硬件描述语言对我们判断的影响。" #: ../../SpinalHDL/Foreword/index.rst:17 @@ -56,11 +60,10 @@ msgstr "VHDL/Verilog 不是硬件描述语言" #: ../../SpinalHDL/Foreword/index.rst:22 msgid "" "Those languages are event driven languages created initially for " -"simulation/documentation purposes. Only in a second time they were used as " -"inputs languages for synthesis tools. Which explain the roots of a lot of " -"the following points." -msgstr "这些语言最初是为了模拟/文档目的而创建的事件驱动语言。只有在后来，它们才被用作" -"综合工具的输入语言。这就解释了以下许多观点的根源。" +"simulation/documentation purposes. Only in a second time they were used " +"as inputs languages for synthesis tools. Which explain the roots of a lot" +" of the following points." +msgstr "这些语言最初是为了模拟/文档目的而创建的事件驱动语言。只有在后来，它们才被用作综合工具的输入语言。这就解释了以下许多观点的根源。" #: ../../SpinalHDL/Foreword/index.rst:29 msgid "Event driven paradigm doesn't make any sense for RTL" @@ -69,14 +72,13 @@ msgstr "事件驱动范式对于 RTL 没有任何意义" #: ../../SpinalHDL/Foreword/index.rst:31 msgid "" "When you think about it, describing digital hardware (RTL) by using " -"process/always blocks doesn't make any practical senses. Why do we have to " -"worry about a sensitivity list? Why do we have to split our design between " -"processes/always blocks of different natures (combinatorial logic / register" -" without reset / register with async reset)?" +"process/always blocks doesn't make any practical senses. Why do we have " +"to worry about a sensitivity list? Why do we have to split our design " +"between processes/always blocks of different natures (combinatorial logic" +" / register without reset / register with async reset)?" msgstr "" -"仔细想想，使用 process/always 块描述数字硬件 (RTL) 没有任何实际意义。为什么我" -"们必须担心敏感列表？为什么我们必须在不同性质的进程(process)/always块之间分割" -"我们的设计（组合逻辑/不带复位的寄存器/带异步复位的寄存器）？" +"仔细想想，使用 process/always 块描述数字硬件 (RTL) " +"没有任何实际意义。为什么我们必须担心敏感列表？为什么我们必须在不同性质的进程(process)/always块之间分割我们的设计（组合逻辑/不带复位的寄存器/带异步复位的寄存器）？" #: ../../SpinalHDL/Foreword/index.rst:37 msgid "For instance, to implement this:" @@ -92,8 +94,8 @@ msgstr "使用 SpinalHDL 你可以这样写：" #: ../../SpinalHDL/Foreword/index.rst:93 msgid "" -"As for everything, you can get used to this event driven semantic, until you" -" taste something better." +"As for everything, you can get used to this event driven semantic, until " +"you taste something better." msgstr "所有事情都是这样，您可以习惯这种事件驱动的语义，直到您尝试更好的事物。" #: ../../SpinalHDL/Foreword/index.rst:98 @@ -104,13 +106,12 @@ msgstr "VHDL 和 Verilog 的最新版本不可用" msgid "" "The EDA industry is really slow to implement VHDL 2008 and SystemVerilog " "synthesis capabilities in their tools. Additionally, when it's done, it " -"appear that only a constraining subset of the language is implemented (not " -"talking about simulation features). It result that using any interesting " -"feature of those language revision isn't safe as:" +"appear that only a constraining subset of the language is implemented " +"(not talking about simulation features). It result that using any " +"interesting feature of those language revision isn't safe as:" msgstr "" -"EDA 行业在其工具中实现 VHDL 2008 和 SystemVerilog 综合功能的速度确实很慢。此" -"外，当它完成时，似乎只实现了该语言的一个约束子集（不谈论仿真功能）。结果是使" -"用这些语言修订版的任何有趣功能都不安全，因为：" +"EDA 行业在其工具中实现 VHDL 2008 和 SystemVerilog " +"综合功能的速度确实很慢。此外，当它完成时，似乎只实现了该语言的一个约束子集（不谈论仿真功能）。结果是使用这些语言修订版的任何有趣功能都不安全，因为：" #: ../../SpinalHDL/Foreword/index.rst:106 msgid "It will probably make your code incompatible with many EDA tools." @@ -118,43 +119,39 @@ msgstr "它可能会使您的代码与许多 EDA 工具不兼容。" #: ../../SpinalHDL/Foreword/index.rst:107 msgid "" -"Other companies will likely not accept your IP as their flow isn't ready for" -" it." +"Other companies will likely not accept your IP as their flow isn't ready " +"for it." msgstr "其他公司可能不会接受您的 IP，因为他们的流程尚未准备好。" #: ../../SpinalHDL/Foreword/index.rst:110 msgid "" -"Anyway, those revisions don't change the heart of those HDL issues: they are" -" based on a event driven paradigm which doesn't make sense to describe " -"digital hardware." -msgstr "无论如何，这些修订并没有改变 HDL " -"问题的核心：它们基于事件驱动范的范式，这对于描述数字硬件没有意义。" +"Anyway, those revisions don't change the heart of those HDL issues: they " +"are based on a event driven paradigm which doesn't make sense to describe" +" digital hardware." +msgstr "无论如何，这些修订并没有改变 HDL 问题的核心：它们基于事件驱动范的范式，这对于描述数字硬件没有意义。" #: ../../SpinalHDL/Foreword/index.rst:116 msgid "" -"VHDL records, Verilog struct are broken (SystemVerilog is good on this, if " -"you can use it)" -msgstr "VHDL 结构记录（record），Verilog 结构（struct）已经破碎（SystemVerilog " -"在这方面很好，如果您可以使用它）" +"VHDL records, Verilog struct are broken (SystemVerilog is good on this, " +"if you can use it)" +msgstr "VHDL 结构记录（record），Verilog 结构（struct）已经破碎（SystemVerilog 在这方面很好，如果您可以使用它）" #: ../../SpinalHDL/Foreword/index.rst:118 msgid "" -"You can't use them to define an interface, because you can't define their " -"internal signal directions. Even worst, you can't give them construction " -"parameters! So, define your RGB record/struct once, and hope you never have " -"to use it with bigger/smaller color channels..." +"You can't use them to define an interface, because you can't define their" +" internal signal directions. Even worst, you can't give them construction" +" parameters! So, define your RGB record/struct once, and hope you never " +"have to use it with bigger/smaller color channels..." msgstr "" -"您不能使用它们来定义接口，因为您无法定义它们的内部信号方向。更糟糕的是，您无" -"法向他们提供构造参数！因此，只能一次性定义好 RGB " +"您不能使用它们来定义接口，因为您无法定义它们的内部信号方向。更糟糕的是，您无法向他们提供构造参数！因此，只能一次性定义好 RGB " "记录/结构，但愿您永远不必将其与不同大小的颜色通道一起使用......" #: ../../SpinalHDL/Foreword/index.rst:123 msgid "" -"Also a fancy thing with VHDL is the fact that if you want to add an array of" -" something into a component entity, you have to define the type of this " -"array into a package... Which can't be parameterized..." -msgstr "VHDL 的另一个奇特之处是，如果您想将某个数组添加到组件实体中，则必须将该数组的" -"类型定义到包中...这就不能参数化了..." +"Also a fancy thing with VHDL is the fact that if you want to add an array" +" of something into a component entity, you have to define the type of " +"this array into a package... Which can't be parameterized..." +msgstr "VHDL 的另一个奇特之处是，如果您想将某个数组添加到组件实体中，则必须将该数组的类型定义到包中...这就不能参数化了..." #: ../../SpinalHDL/Foreword/index.rst:127 msgid "For instance, below is a SpinalHDL APB3 bus definition:" @@ -163,11 +160,11 @@ msgstr "例如，下面是 SpinalHDL APB3 总线定义：" #: ../../SpinalHDL/Foreword/index.rst:159 msgid "" "Then about the VHDL 2008 partial solution and the SystemVerilog " -"interface/modport, lucky you are if your EDA tools / company flow / company " -"policy allow you to use them." +"interface/modport, lucky you are if your EDA tools / company flow / " +"company policy allow you to use them." msgstr "" -"然后VHDL 2008有部分的解决方案和SystemVerilog接口/modport也能有所帮助，如果您" -"的EDA工具/公司流程/公司政策允许您使用它们，那么您很幸运。" +"然后VHDL " +"2008有部分的解决方案和SystemVerilog接口/modport也能有所帮助，如果您的EDA工具/公司流程/公司政策允许您使用它们，那么您很幸运。" #: ../../SpinalHDL/Foreword/index.rst:165 msgid "VHDL and Verilog are so verbose" @@ -181,28 +178,24 @@ msgstr "对于VHDL和Verilog，当它开始涉及组件实例化互连时，必 #: ../../SpinalHDL/Foreword/index.rst:170 msgid "" -"To understand it more deeply, below is a SpinalHDL example performing some " -"peripherals instantiation and adding the APB3 decoder required to access " -"them." -msgstr "要更深入地理解它，下面是一个使用SpinalHDL实例化一些外设并添加用于访问它们所需" -"的APB3解码器的示例。" +"To understand it more deeply, below is a SpinalHDL example performing " +"some peripherals instantiation and adding the APB3 decoder required to " +"access them." +msgstr "要更深入地理解它，下面是一个使用SpinalHDL实例化一些外设并添加用于访问它们所需的APB3解码器的示例。" #: ../../SpinalHDL/Foreword/index.rst:203 msgid "" "Done. That's all. You don't have to bind each signal one by one when you " -"instantiate a module/component because you can access their interfaces in a " -"object-oriented manner." -msgstr "完成。这就是所有内容。在实例化模块/组件时，你不必一个接一个地绑定信号，因为你" -"可以以面向对象的方式访问它们的接口。" +"instantiate a module/component because you can access their interfaces in" +" a object-oriented manner." +msgstr "完成。这就是所有内容。在实例化模块/组件时，你不必一个接一个地绑定信号，因为你可以以面向对象的方式访问它们的接口。" #: ../../SpinalHDL/Foreword/index.rst:207 msgid "" "Also about VHDL/Verilog struct/records, we can say that they are really " -"dirty tricks, without true parameterization and reusability capabilities, " -"trying to hide the fact that those languages were poorly designed." -msgstr "" -"另外，关于 VHDL/Verilog 结构/记录，可以说它们确实是无用的，没有真正的参数化和" -"可重用性功能，仅仅是试图掩盖这些语言设计不佳的事实。" +"dirty tricks, without true parameterization and reusability capabilities," +" trying to hide the fact that those languages were poorly designed." +msgstr "另外，关于 VHDL/Verilog 结构/记录，可以说它们确实是无用的，没有真正的参数化和可重用性功能，仅仅是试图掩盖这些语言设计不佳的事实。" #: ../../SpinalHDL/Foreword/index.rst:213 msgid "Meta Hardware Description capabilities" @@ -213,49 +206,40 @@ msgid "" "Basically VHDL and Verilog provide some elaboration tools which aren't " "directly mapped into hardware as loops / generate statements / macro / " "function / procedure / task. But that's all." -msgstr "VHDL 和 Verilog 提供了一些实例细化工具，这些工具不会直接映射到硬件中，如循环/" -"生成语句/宏/函数/过程/任务。但仅此而已。" +msgstr "VHDL 和 Verilog 提供了一些实例细化工具，这些工具不会直接映射到硬件中，如循环/生成语句/宏/函数/过程/任务。但仅此而已。" #: ../../SpinalHDL/Foreword/index.rst:219 msgid "" "And even then, they are really limited. For instance, one can't define " -"process/always/component/module blocks into a task/procedure. It is really a" -" bottleneck for many fancy things." -msgstr "即便如此，它们的作用也确实有限。例如，不能将进程/always块/组件/模块块定义到任" -"务/过程中。这确实是许多高级功能的瓶颈。" +"process/always/component/module blocks into a task/procedure. It is " +"really a bottleneck for many fancy things." +msgstr "即便如此，它们的作用也确实有限。例如，不能将进程/always块/组件/模块块定义到任务/过程中。这确实是许多高级功能的瓶颈。" #: ../../SpinalHDL/Foreword/index.rst:223 msgid "" "With SpinalHDL you can call a user-defined task/procedure on a bus like " -"that: ``myHandshakeBus.queue(depth=64)``. Below is some code including the " -"definition." +"that: ``myHandshakeBus.queue(depth=64)``. Below is some code including " +"the definition." msgstr "" "使用 " -"SpinalHDL，您可以在总线上调用用户定义的任务/过程，如下所示：``myHandshakeBus." -"queue(depth=64)``。下面是一些包含定义的代码。" +"SpinalHDL，您可以在总线上调用用户定义的任务/过程，如下所示：``myHandshakeBus.queue(depth=64)``。下面是一些包含定义的代码。" #: ../../SpinalHDL/Foreword/index.rst:249 msgid "" "Let's see further, imagine you want to define a state machine. With " -"VHDL/Verilog you have to write a lot of raw code with some switch statements" -" to do it. You can't define the notion of \"StateMachine\", which would give" -" you a nice syntax to define each state. Else you can use a third-party tool" -" to draw your state machine and then generate your VHDL/Verilog equivalent " -"code..." -msgstr "" -"让我们进一步想象，假设你想定义一个有限状态机。使用VHDL/" -"Verilog，你需要编写大量原始代码，并使用一些switch语句来实现它。" -"你不能定义\"StateMachine\"的概念，这将为你提供一个很好的语法来定义每个状态。" -"否则，你可以使用第三方工具来绘制你的有限状态机，然后生成等价的VHDL/" -"Verilog代码..." +"VHDL/Verilog you have to write a lot of raw code with some switch " +"statements to do it. You can't define the notion of \"StateMachine\", " +"which would give you a nice syntax to define each state. Else you can use" +" a third-party tool to draw your state machine and then generate your " +"VHDL/Verilog equivalent code..." +msgstr "让我们进一步想象，假设你想定义一个有限状态机。使用VHDL/Verilog，你需要编写大量原始代码，并使用一些switch语句来实现它。你不能定义\"StateMachine\"的概念，这将为你提供一个很好的语法来定义每个状态。否则，你可以使用第三方工具来绘制你的有限状态机，然后生成等价的VHDL/Verilog代码..." #: ../../SpinalHDL/Foreword/index.rst:255 msgid "" "Meta-hardware description capabilities of SpinalHDL enable you to define " -"your own tools which then allow you to define things in abstracts ways, as " -"for state machines." -msgstr "SpinalHDL 的元硬件描述能力使您能够定义自己的工具，然后允许您以抽象方式定义事" -"物，例如有限状态机。" +"your own tools which then allow you to define things in abstracts ways, " +"as for state machines." +msgstr "SpinalHDL 的元硬件描述能力使您能够定义自己的工具，然后允许您以抽象方式定义事物，例如有限状态机。" #: ../../SpinalHDL/Foreword/index.rst:259 msgid "" @@ -265,22 +249,20 @@ msgstr "下面是SpinalHDL上有限状态机的一个简单的用法示例：" #: ../../SpinalHDL/Foreword/index.rst:290 msgid "" -"Imagine you want to generate the instruction decoding of your CPU. It could " -"require some fancy elaboration time algorithms to generate the less logic " -"possible. But in VHDL/Verilog, your only option to do these kind of things " -"is to write a script which generates the ``.vhd`` and ``.v`` that you want." +"Imagine you want to generate the instruction decoding of your CPU. It " +"could require some fancy elaboration time algorithms to generate the less" +" logic possible. But in VHDL/Verilog, your only option to do these kind " +"of things is to write a script which generates the ``.vhd`` and ``.v`` " +"that you want." msgstr "" -"假设你想生成CPU的指令解码逻辑。这可能需要一些复杂的实例细化时算法来生成尽可能" -"少的逻辑。但是，在VHDL/Verilog中，你唯一的选择是用脚本生成你想要的 ``.vhd`` " -"和 ``.v`` 文件。" +"假设你想生成CPU的指令解码逻辑。这可能需要一些复杂的实例细化时算法来生成尽可能少的逻辑。但是，在VHDL/Verilog中，你唯一的选择是用脚本生成你想要的" +" ``.vhd`` 和 ``.v`` 文件。" #: ../../SpinalHDL/Foreword/index.rst:295 msgid "" -"There is really much to say about meta-hardware description, but the only " -"true way to understand it and get its real taste is to experiment it. The " -"goal with it is to stop playing with wires and gates, to start taking some " -"distance with that low level stuff, to think reusable." -msgstr "" -"关于元硬件描述确实有很多话要说，但理解它并得其真味的唯一方法就是进行实验。它" -"的目标是停止直接使用电线和门，与那些抽象层级较低的东西保持一定的距离，并思考" -"可重用的方法。" +"There is really much to say about meta-hardware description, but the only" +" true way to understand it and get its real taste is to experiment it. " +"The goal with it is to stop playing with wires and gates, to start taking" +" some distance with that low level stuff, to think reusable." +msgstr "关于元硬件描述确实有很多话要说，但理解它并得其真味的唯一方法就是进行实验。它的目标是停止直接使用电线和门，与那些抽象层级较低的东西保持一定的距离，并思考可重用的方法。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po index 696bb48df7a..55d074757f6 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-15 01:17+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.3\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Formal verification/index.rst:3 msgid "Formal verification" @@ -29,8 +32,8 @@ msgstr "介绍" #: ../../SpinalHDL/Formal verification/index.rst:9 msgid "" -"SpinalHDL allows to generate a subset of the SystemVerilog Assertions (SVA)." -" Mostly assert, assume, cover and a few others." +"SpinalHDL allows to generate a subset of the SystemVerilog Assertions " +"(SVA). Mostly assert, assume, cover and a few others." msgstr "" "SpinalHDL 允许生成 SystemVerilog 断言 (SVA) " "的子集。主要是断言（assert）、假设（assume）、覆盖（cover）和其他一些内容。" @@ -40,8 +43,7 @@ msgid "" "In addition it provide a formal verification backend which allows to " "directly run the formal verification in the open-source Symbi-Yosys " "toolchain." -msgstr "此外，它还提供了形式化验证后端，允许直接在开源 Symbi-Yosys " -"工具链中运行形式化验证。" +msgstr "此外，它还提供了形式化验证后端，允许直接在开源 Symbi-Yosys 工具链中运行形式化验证。" #: ../../SpinalHDL/Formal verification/index.rst:16 msgid "Formal backend" @@ -83,8 +85,8 @@ msgstr "https://github.com/YosysHQ/oss-cad-suite-build/releases" #: ../../SpinalHDL/Formal verification/index.rst:40 msgid "" -"https://github.com/YosysHQ/fpga-toolchain/releases (EOL - superseded by oss-" -"cad-suite)" +"https://github.com/YosysHQ/fpga-toolchain/releases (EOL - superseded by " +"oss-cad-suite)" msgstr "" "https://github.com/YosysHQ/fpga-toolchain/releases（EOL - 由 oss-cad-suite " "取代）" @@ -125,14 +127,12 @@ msgstr "外部激励" #: ../../SpinalHDL/Formal verification/index.rst:122 msgid "" -"If your DUT has inputs, you need to drive them from the testbench. You can " -"use all the regular hardware statements to do it, but you can also use the " -"formal `anyseq`, `anyconst`, `allseq`, `allconst` statement:" +"If your DUT has inputs, you need to drive them from the testbench. You " +"can use all the regular hardware statements to do it, but you can also " +"use the formal `anyseq`, `anyconst`, `allseq`, `allconst` statement:" msgstr "" -"如果您的 DUT " -"有输入，您需要从测试代码中驱动它们。您可以使用所有常规硬件语句来执行此操作，" -"但您也可以使用形式化验证中的 `anyseq`、`anyconst`、`allseq`、`allconst` " -"语句：" +"如果您的 DUT 有输入，您需要从测试代码中驱动它们。您可以使用所有常规硬件语句来执行此操作，但您也可以使用形式化验证中的 " +"`anyseq`、`anyconst`、`allseq`、`allconst` 语句：" #: ../../SpinalHDL/Formal verification/index.rst:151 msgid "More assertions / past" @@ -140,8 +140,8 @@ msgstr "更多关于断言/past（以前某个时钟内的状态）的例子" #: ../../SpinalHDL/Formal verification/index.rst:153 msgid "" -"For instance we can check that the value is counting up (if not already at " -"10):" +"For instance we can check that the value is counting up (if not already " +"at 10):" msgstr "例如，我们可以检查该值是否在正向计数（如果尚未达到 10）：" #: ../../SpinalHDL/Formal verification/index.rst:169 @@ -150,8 +150,8 @@ msgstr "假设内存中的内容" #: ../../SpinalHDL/Formal verification/index.rst:171 msgid "" -"Here is an example where we want to prevent the value ``1`` from ever being " -"present in a memory :" +"Here is an example where we want to prevent the value ``1`` from ever " +"being present in a memory :" msgstr "这是一个示例，我们希望防止值 ``1`` 出现在内存中：" #: ../../SpinalHDL/Formal verification/index.rst:207 @@ -164,10 +164,9 @@ msgstr "断言/时钟/复位" #: ../../SpinalHDL/Formal verification/index.rst:212 msgid "" -"Assertions are always clocked and disabled during resets. This also apply " -"for assumes and covers." -msgstr "断言（assert）是一直被时钟驱动的，但在复位期间被禁用。这也适用于假设（assume" -"）和覆盖（cover）。" +"Assertions are always clocked and disabled during resets. This also apply" +" for assumes and covers." +msgstr "断言（assert）是一直被时钟驱动的，但在复位期间被禁用。这也适用于假设（assume）和覆盖（cover）。" #: ../../SpinalHDL/Formal verification/index.rst:214 msgid "If you want to keep your assertion enabled during reset you can do:" @@ -178,8 +177,9 @@ msgid "Specifying the initial value of a signal" msgstr "指定信号的初始值" #: ../../SpinalHDL/Formal verification/index.rst:226 +#, fuzzy msgid "" -"For instance, for the reset signal of the current clockdomain (usefull at " +"For instance, for the reset signal of the current clockdomain (useful at " "the top)" msgstr "例如，对于当前时钟域的复位信号（在顶部有用）" @@ -193,8 +193,8 @@ msgstr "内存内容（Mem）检查" #: ../../SpinalHDL/Formal verification/index.rst:242 msgid "" -"If you have a Mem in your design, and you want to check its content, you can" -" do it the following ways :" +"If you have a Mem in your design, and you want to check its content, you " +"can do it the following ways :" msgstr "如果您的设计中有 Mem，并且想要检查其内容，可以通过以下方式进行：" #: ../../SpinalHDL/Formal verification/index.rst:257 @@ -249,10 +249,10 @@ msgstr "返回 ``delay`` 周期以前的 ``that``值 。 （默认1个周期）" msgid "``rose(that : Bool)``" msgstr "``rose(that : Bool)``" -#: ../../SpinalHDL/Formal verification/index.rst:290 -#: verification/index.rst:293 verification/index.rst:296 -#: verification/index.rst:299 verification/index.rst:302 -#: verification/index.rst:305 verification/index.rst:308 +#: ../../SpinalHDL/Formal verification/index.rst:290 verification/index.rst:293 +#: verification/index.rst:296 verification/index.rst:299 +#: verification/index.rst:302 verification/index.rst:305 +#: verification/index.rst:308 msgid "Bool" msgstr "Bool" @@ -274,8 +274,8 @@ msgstr "``changed(that : Bool)``" #: ../../SpinalHDL/Formal verification/index.rst:297 msgid "" -"Return True when ``that`` current value changed between compared to the last" -" cycle" +"Return True when ``that`` current value changed between compared to the " +"last cycle" msgstr "当 ``that`` 当前值与上一个周期相比发生变化时返回 True" #: ../../SpinalHDL/Formal verification/index.rst:298 @@ -284,8 +284,8 @@ msgstr "``stable(that : Bool)``" #: ../../SpinalHDL/Formal verification/index.rst:300 msgid "" -"Return True when ``that`` current value didn't changed between compared to " -"the last cycle" +"Return True when ``that`` current value didn't changed between compared " +"to the last cycle" msgstr "当 ``that`` 当前值与上一个周期相比没有改变时返回 True" #: ../../SpinalHDL/Formal verification/index.rst:301 @@ -306,20 +306,19 @@ msgid "" "Recommended to be used with each application of ``past``, ``rose``, " "``fell``, ``changed`` and ``stable``." msgstr "" -"当过去的值有效时返回 True（第一个周期为 False）。建议在 ``past``, ``rose``, " -"``fell``, ``changed`` 和 ``stable`` 每次使用的地方均使用它。" +"当过去的值有效时返回 True（第一个周期为 False）。建议在 ``past``, ``rose``, ``fell``, " +"``changed`` 和 ``stable`` 每次使用的地方均使用它。" #: ../../SpinalHDL/Formal verification/index.rst:307 msgid "``pastValidAfterReset()``" msgstr "``pastValidAfterReset()``" #: ../../SpinalHDL/Formal verification/index.rst:309 +#, fuzzy msgid "" -"Simliar to ``pastValid``, where only difference is that this would take " +"Similar to ``pastValid``, where only difference is that this would take " "reset into account. Can be understood as ``pastValid & past(!reset)``." -msgstr "" -"与“pastValid”类似，唯一的区别是这会考虑重置。可以理解为 ``pastValid & " -"past(!reset)``，同步逻辑中建议使用。" +msgstr "与“pastValid”类似，唯一的区别是这会考虑重置。可以理解为 ``pastValid & past(!reset)``，同步逻辑中建议使用。" #: ../../SpinalHDL/Formal verification/index.rst:311 msgid "Note that you can use the init statement on past:" @@ -331,10 +330,9 @@ msgstr "局限性" #: ../../SpinalHDL/Formal verification/index.rst:322 msgid "" -"There is no support for unclocked assertions. But their usage in third party" -" formal verification examples seems mostly code style related." -msgstr "不支持非时钟驱动的断言。但它们在第三方形式化验证示例中有这样使用，似乎主要与" -"代码风格相关。" +"There is no support for unclocked assertions. But their usage in third " +"party formal verification examples seems mostly code style related." +msgstr "不支持非时钟驱动的断言。但它们在第三方形式化验证示例中有这样使用，似乎主要与代码风格相关。" #: ../../SpinalHDL/Formal verification/index.rst:326 msgid "Naming polices" @@ -347,10 +345,9 @@ msgid "" "create formal related logic, there could be ``formalAsserts``, " "``formalAssumes`` and ``formalCovers`` in it." msgstr "" -"所有与形式验证相关的函数都返回 Area 或 " -"Composite（首选），并命名为formalXXXX。 ``formalContext`` " -"可用于创建形式相关逻辑，还有可能是 ``formalAsserts``、 ``formalAssumes`` 和 " -"``formalCovers`` 。" +"所有与形式验证相关的函数都返回 Area 或 Composite（首选），并命名为formalXXXX。 ``formalContext`` " +"可用于创建形式相关逻辑，还有可能是 ``formalAsserts``、 ``formalAssumes`` 和 ``formalCovers``" +" 。" #: ../../SpinalHDL/Formal verification/index.rst:332 msgid "For Component" @@ -358,24 +355,25 @@ msgstr "对于组件" #: ../../SpinalHDL/Formal verification/index.rst:333 msgid "" -"The minimum required assertions internally in a ``Component`` for \"prove\" " -"can be named as ``formalAsserts``." -msgstr "证明模式中需要的， ``Component`` 内部所需的最少断言可以命名为 " -"``formalAsserts``。" +"The minimum required assertions internally in a ``Component`` for " +"\"prove\" can be named as ``formalAsserts``." +msgstr "证明模式中需要的， ``Component`` 内部所需的最少断言可以命名为 ``formalAsserts``。" #: ../../SpinalHDL/Formal verification/index.rst:336 msgid "For interfaces implement IMasterSlave" msgstr "对于实现 IMasterSlave的接口" #: ../../SpinalHDL/Formal verification/index.rst:337 +#, fuzzy msgid "" "There could be functions in name ``formalAssertsMaster``, " -"``formalAssertsSlave``, ``formalAssumesMaster``, ``formalAssumesSlave`` or " -"``formalCovers``. Master/Slave are target interface type, so that " -"``formalAssertsMaster`` can be understand as \"formal verfication assertions" -" for master interface\"." +"``formalAssertsSlave``, ``formalAssumesMaster``, ``formalAssumesSlave`` " +"or ``formalCovers``. Master/Slave are target interface type, so that " +"``formalAssertsMaster`` can be understand as \"formal verification " +"assertions for master interface\"." msgstr "" "可能存在以 ``formalAssertsMaster``, ``formalAssertsSlave``, " "``formalAssumesMaster``, ``formalAssumesSlave`` or ``formalCovers`` " "命名的函数。 Master/Slave 是目标接口类型，因此，``formalAssertsMaster`` " "可以理解为“主接口的形式化验证断言”。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Install and setup.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Install and setup.po index 737b4217240..d539308c29e 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Install and setup.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Install and setup.po @@ -1,26 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"POT-Creation-Date: 2024-04-19 10:29+0000\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-04-26 02:33+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.5.1-dev\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Getting Started/Install and setup.rst:4 msgid "Install and setup" @@ -187,9 +187,10 @@ msgstr "" "（oss-cad-suite 的最后测试版本是 `2023-10-22`，但最新的版本可能也可以工作）" #: ../../SpinalHDL/Getting Started/Install and setup.rst:83 +#, fuzzy msgid "" "To use oss-cad-suite in a shell you need to load it's environment, e.g. " -"via ``souce /environment``." +"via ``source /environment``." msgstr "" "要在 shell 中使用 oss-cad-suite，您需要加载它的环境，例如通过 ``souce /environment`` 实现。" @@ -261,12 +262,10 @@ msgid "" "download the Linux version to WSL, if you want to use VSCode then the " "Windows version can be used to remotely edit in WSL." msgstr "" -"虽然可以进行本机安装，但更简单且目前推荐的方法是在 Windows 上使用 WSL。" -"如果您想使用 WSL，请安装您选择的 `发行版 `__ ，并按照 Linux 安装说明进行操作。WSL " -"实例中的数据可以从Windows访问，在 ``\\\\wsl$`` 路径下。如果您想使用 " -"IntelliJ，则必须将 Linux 版本下载到 WSL，如果您想使用 VSCode，则可以使用 " -"Windows 版本远程编辑WSL中的数据。" +"虽然可以进行本机安装，但更简单且目前推荐的方法是在 Windows 上使用 WSL。如果您想使用 WSL，请安装您选择的 `发行版 " +"`__ ，并按照 Linux " +"安装说明进行操作。WSL 实例中的数据可以从Windows访问，在 ``\\\\wsl$`` 路径下。如果您想使用 IntelliJ，则必须将 " +"Linux 版本下载到 WSL，如果您想使用 VSCode，则可以使用 Windows 版本远程编辑WSL中的数据。" #: ../../SpinalHDL/Getting Started/Install and setup.rst:136 msgid "" @@ -322,16 +321,14 @@ msgid "" " to download the packages manually. See the README for the repos for more" " details." msgstr "" -"SpinalHDL 维护者 `Readon ` " -"提供的一体化解决方案可用于安装和运行 SpinalHDL，并通过 Verilator 仿真、通过 " -"SymbiYosys 进行形式化验证。下载 `安装程序 `__ 并将该环境安装在磁盘上的任何位置。单击“开始”" -"菜单中的 MSYS2-MINGW64 图标启动构建环境，并使用 MSYS2 " -"默认控制台。另一种方法是使用“Windows Terminal”或类似 Tabby 的应用程序，" -"并使用启动命令 ``%MSYS2_ROOT%\\msys2_shell.cmd -defterm -here -no-start " -"-mingw64``，其中 ``%MSYS2_ROOT%`` 是 msys2 安装的位置。值得注意的是，如果要离" -"线使用，要仔细选择项目所依赖的库，否则需要手动下载安装包。有关更多详细信息，" -"请参阅对应仓库的自述文件。" +"SpinalHDL 维护者 `Readon ` 提供的一体化解决方案可用于安装和运行 " +"SpinalHDL，并通过 Verilator 仿真、通过 SymbiYosys 进行形式化验证。下载 `安装程序 " +"`__ " +"并将该环境安装在磁盘上的任何位置。单击“开始”菜单中的 MSYS2-MINGW64 图标启动构建环境，并使用 MSYS2 " +"默认控制台。另一种方法是使用“Windows Terminal”或类似 Tabby 的应用程序，并使用启动命令 " +"``%MSYS2_ROOT%\\msys2_shell.cmd -defterm -here -no-start -mingw64``，其中 " +"``%MSYS2_ROOT%`` 是 msys2 " +"安装的位置。值得注意的是，如果要离线使用，要仔细选择项目所依赖的库，否则需要手动下载安装包。有关更多详细信息，请参阅对应仓库的自述文件。" #: ../../SpinalHDL/Getting Started/Install and setup.rst:158 msgid "MSYS2 verilator for simulation" @@ -688,3 +685,4 @@ msgstr ":ref:`Using IntelliJ`" #~ msgid "Recommended requirements" #~ msgstr "推荐要求" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po index ec97811ccef..845177f43b4 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po @@ -1,30 +1,34 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-13 05:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:2 using msgid "Projects using SpinalHDL" msgstr "使用 SpinalHDL 的项目" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:4 using -msgid "Note that the following lists are very incompletes." +#, fuzzy +msgid "Note that the following lists are very incomplete." msgstr "请注意，以下列表非常不完整。" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:9 using @@ -48,8 +52,8 @@ msgid "" "`SaxonSoc " "`_" msgstr "" -"`SaxonSoc `_" +"`SaxonSoc " +"`_" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:15 using msgid "`open-rdma `_" @@ -74,17 +78,18 @@ msgstr "`达坦科技，中国 `_" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:25 using msgid "" -"`RoCE v2 hardware implementation `_" +"`RoCE v2 hardware implementation `_" msgstr "`RoCE v2 硬件实现 `_" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:26 using msgid "" "`WaveBPF `_ (wBPF): a \"tightly-" -"coupled multi-core\" eBPF CPU, designed to be a high-throughput coprocessor " -"for processing in-memory data (e.g. network packets)." +"coupled multi-core\" eBPF CPU, designed to be a high-throughput " +"coprocessor for processing in-memory data (e.g. network packets)." msgstr "" -"`WaveBPF `_ (wBPF)：一个“紧耦合多核”" -"eBPF CPU，设计为用于处理内存数据的高吞吐量协处理器（例如网络数据包）。" +"`WaveBPF `_ (wBPF)：一个“紧耦合多核”eBPF " +"CPU，设计为用于处理内存数据的高吞吐量协处理器（例如网络数据包）。" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:30 using msgid "`Elitestek (FPGA Vendor), China `_" @@ -105,8 +110,8 @@ msgid "" "`SpinalHDL To Accelerate Neuroscience (PDF slideshow) " "`_" msgstr "" -"`SpinalHDL 加速神经科学（PDF 幻灯片） `_" +"`SpinalHDL 加速神经科学（PDF 幻灯片） " +"`_" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:40 using msgid "QsPin, Belgium" @@ -121,8 +126,8 @@ msgid "" "`SpinalHDL for ASIC (PDF slideshow) " "`_" msgstr "" -"`适用于 ASIC 的 SpinalHDL（PDF 幻灯片） `_" +"`适用于 ASIC 的 SpinalHDL（PDF 幻灯片） " +"`_" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:49 using msgid "Universities" @@ -133,23 +138,23 @@ msgid "" "`Universität Bremen - Fachbereich 3 - Informatik, Germany " "`_" msgstr "" -"`不来梅大学 - 数学与计算机科学学院，德国 `_" +"`不来梅大学 - 数学与计算机科学学院，德国 `_" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:54 using msgid "" -"`SpinalHDL in Computer Architecture Research and Education (PDF slideshow) " +"`SpinalHDL in Computer Architecture Research and Education (PDF " +"slideshow) " "`_" msgstr "" -"`计算机体系结构研究和教育中的 SpinalHDL（PDF 幻灯片） `_" +"`计算机体系结构研究和教育中的 SpinalHDL（PDF 幻灯片） " +"`_" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:57 using msgid "" -"`Universität Potsdam - Embedded Systems Architectures for Signalprocessing, " -"Germany `_" -msgstr "`波茨坦大学 - 用于信号处理的嵌入式系统架构，德国 `_" +"`Universität Potsdam - Embedded Systems Architectures for " +"Signalprocessing, Germany `_" +msgstr "`波茨坦大学 - 用于信号处理的嵌入式系统架构，德国 `_" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:60 using msgid "" @@ -157,6 +162,6 @@ msgid "" "slideshow) " "`_" msgstr "" -"`用于 FPGA 集群的网络附加深度学习加速器（PDF 幻灯片） `_" +"`用于 FPGA 集群的网络附加深度学习加速器（PDF 幻灯片） " +"`_" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po index d5c26774bf0..e7eb1fe6c51 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:7 msgid "SoC toplevel (Pinsec)" @@ -33,16 +36,16 @@ msgid "" "SpinalHDL library and some documentation could be find :ref:`there " "`" msgstr "" -"``Pinsec`` 是一个专为FPGA设计的小型 SoC。它可以在SpinalHDL库中找到，" -"并且可以在 :ref:`这里 ` 找到一些文档" +"``Pinsec`` 是一个专为FPGA设计的小型 SoC。它可以在SpinalHDL库中找到，并且可以在 :ref:`这里 " +"` 找到一些文档" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:14 msgid "" -"Its toplevel implementation is an interesting example, because it is a mix " -"some design patterns that make it very easy to modify. Adding a new master " -"or a new peripheral to the bus fabric could be done with little effort." -msgstr "它的顶层实现是一个有趣的例子，因为它混合了一些设计模式，使其非常容易修改。可" -"以轻松实现向总线结构添加新的主设备或新的外设。" +"Its toplevel implementation is an interesting example, because it is a " +"mix some design patterns that make it very easy to modify. Adding a new " +"master or a new peripheral to the bus fabric could be done with little " +"effort." +msgstr "它的顶层实现是一个有趣的例子，因为它混合了一些设计模式，使其非常容易修改。可以轻松实现向总线结构添加新的主设备或新的外设。" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:16 msgid "" @@ -51,10 +54,9 @@ msgid "" " " "`_" msgstr "" -"可以在以下链接中查阅顶层实现：`https://github.com/SpinalHDL/SpinalHDL/blob/" -"master/lib/src/main/scala/spinal/lib/soc/pinsec/Pinsec.scala `_" +"可以在以下链接中查阅顶层实现：`https://github.com/SpinalHDL/SpinalHDL/blob/master/lib/src/main/scala/spinal/lib/soc/pinsec/Pinsec.scala" +" " +"`_" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:19 msgid "This is the Pinsec toplevel hardware diagram :" @@ -119,8 +121,8 @@ msgstr "resetCtrlClockDomain" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:71 msgid "" -"Used by the reset controller, Flops of this clock domain are initialized by " -"the FPGA bitstream" +"Used by the reset controller, Flops of this clock domain are initialized " +"by the FPGA bitstream" msgstr "由复位控制器使用，该时钟域的触发器由FPGA比特流初始化" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:72 @@ -165,8 +167,7 @@ msgstr "复位控制器" msgid "" "First we need to define the reset controller clock domain, which has no " "reset wire, but use the FPGA bitstream loading to setup flipflops." -msgstr "首先我们需要定义复位控制器时钟域，它没有复位线，而是使用FPGA比特流加载来设置" -"触发器。" +msgstr "首先我们需要定义复位控制器时钟域，它没有复位线，而是使用FPGA比特流加载来设置触发器。" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:100 msgid "Then we can define a simple reset controller under this clock domain." @@ -178,14 +179,14 @@ msgstr "每个系统的时钟域设置" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:133 msgid "" -"Now that the reset controller is implemented, we can define clock domain for" -" all sub-systems of Pinsec :" +"Now that the reset controller is implemented, we can define clock domain " +"for all sub-systems of Pinsec :" msgstr "现在复位控制器已经实现，我们可以为Pinsec的所有子系统定义时钟域：" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:157 msgid "" -"Also all the core system of Pinsec will be defined into a ``axi`` clocked " -"area :" +"Also all the core system of Pinsec will be defined into a ``axi`` clocked" +" area :" msgstr "此外，Pinsec的所有核心系统都将在一个 ``axi`` 时钟域里定义：" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:166 @@ -230,12 +231,10 @@ msgstr "AXI4片上RAM的实例化非常简单。" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:230 msgid "" -"In fact it's not an AXI4 but an Axi4Shared, which mean that a ARW channel " -"replace the AR and AW ones. This solution uses less area while being fully " -"interoperable with full AXI4." -msgstr "" -"事实上，它不是AXI4，而是Axi4Shared，这意味着ARW通道取代了AR和AW通道。该解决方" -"案占用的面积更少，同时可与完整的AXI4实现完全互操作。" +"In fact it's not an AXI4 but an Axi4Shared, which mean that a ARW channel" +" replace the AR and AW ones. This solution uses less area while being " +"fully interoperable with full AXI4." +msgstr "事实上，它不是AXI4，而是Axi4Shared，这意味着ARW通道取代了AR和AW通道。该解决方案占用的面积更少，同时可与完整的AXI4实现完全互操作。" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:242 msgid "SDRAM controller" @@ -243,8 +242,8 @@ msgstr "SDRAM控制器" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:244 msgid "" -"First you need to define the layout and timings of your SDRAM device. On the" -" DE1-SOC, the SDRAM device is an IS42x320D one." +"First you need to define the layout and timings of your SDRAM device. On " +"the DE1-SOC, the SDRAM device is an IS42x320D one." msgstr "首先，您需要定义SDRAM设备的布局和时序。在DE1-SOC上，SDRAM型号是IS42x320D。" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:271 @@ -259,8 +258,8 @@ msgstr "JTAG控制器" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:286 msgid "" -"The JTAG controller could be used to access memories and debug the CPU from " -"an PC." +"The JTAG controller could be used to access memories and debug the CPU " +"from an PC." msgstr "JTAG控制器可用于在PC访问存储器并调试CPU。" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:298 @@ -363,15 +362,16 @@ msgid "" msgstr "该桥将用于将低带宽外设连接到AXI交叉开关。" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:411 +#, fuzzy msgid "" "The AXI4 crossbar that interconnect AXI4 masters and slaves together is " -"generated by using an factory. The concept of this factory is to create it, " -"then call many function on it to configure it, and finaly call the ``build``" -" function to ask the factory to generate the corresponding hardware :" +"generated by using an factory. The concept of this factory is to create " +"it, then call many function on it to configure it, and finally call the " +"``build`` function to ask the factory to generate the corresponding " +"hardware :" msgstr "" -"将AXI4主端和从端互连在一起的AXI4交叉开关是使用生成器(factory)生成的。这个生成" -"器的概念是先创建它，然后调用它的许多函数来配置，最后调用 ``build`` " -"函数来使生成器生成相应的硬件：" +"将AXI4主端和从端互连在一起的AXI4交叉开关是使用生成器(factory)生成的。这个生成器的概念是先创建它，然后调用它的许多函数来配置，最后调用" +" ``build`` 函数来使生成器生成相应的硬件：" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:421 msgid "First you need to populate slaves interfaces :" @@ -379,17 +379,16 @@ msgstr "首先，您需要添加从端接口：" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:433 msgid "" -"Then you need to populate a matrix of interconnections between slaves and " -"masters (this sets up visibility) :" +"Then you need to populate a matrix of interconnections between slaves and" +" masters (this sets up visibility) :" msgstr "然后，您需要添加从端和主端之间的互连矩阵（这展现可见性）：" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:446 msgid "" -"Then to reduce combinatorial path length and have a good design FMax, you " -"can ask the factory to insert pipelining stages between itself a given " +"Then to reduce combinatorial path length and have a good design FMax, you" +" can ask the factory to insert pipelining stages between itself a given " "master or slave :" -msgstr "然后，为了减少组合路径长度并拥有良好的设计FMax，您可以要求生成器在给定的主端" -"或从端之间插入流水线级：" +msgstr "然后，为了减少组合路径长度并拥有良好的设计FMax，您可以要求生成器在给定的主端或从端之间插入流水线级：" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst msgid "" @@ -399,15 +398,14 @@ msgstr "以下代码中的 ``halfPipe`` / >> / << / >/-> 由反压流(Stream)总 #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst msgid "" -"Some documentation could be find :ref:`there `. In short, it's just " -"some pipelining and interconnection stuff." -msgstr "可以在 :ref:`这里 ` " -"找到一些文档。简而言之，这只是一些流水线和互连的东西。" +"Some documentation could be find :ref:`there `. In short, it's " +"just some pipelining and interconnection stuff." +msgstr "可以在 :ref:`这里 ` 找到一些文档。简而言之，这只是一些流水线和互连的东西。" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:473 msgid "" -"The interconnection between the APB3 bridge and all peripherals is done via " -"an APB3Decoder :" +"The interconnection between the APB3 bridge and all peripherals is done " +"via an APB3Decoder :" msgstr "APB3桥和所有外设之间的互连是通过APB3Decoder完成的：" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:490 @@ -415,15 +413,15 @@ msgid "Misc" msgstr "杂项" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:492 -msgid "" -"To connect all toplevel IO to components, the following code is required :" +msgid "To connect all toplevel IO to components, the following code is required :" msgstr "要将所有顶层IO连接到组件，需要以下代码：" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:503 msgid "" -"And finally some connections between components are required like interrupts" -" and core debug module resets" +"And finally some connections between components are required like " +"interrupts and core debug module resets" msgstr "最后需要组件之间的一些连接，例如中断和核心调试模块复位" #~ msgid "Systems clock domains" #~ msgstr "系统时钟域" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po index 5f24e57df42..42c9494d8df 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-13 05:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:7 #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:15 @@ -25,26 +28,26 @@ msgid "Introduction" msgstr "简介" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:10 +#, fuzzy msgid "" -"This page only documents the SoC implemented with the first generation of " -"RISC-V CPU created in SpinalHDL. This page does not document the VexRiscV " -"CPU, which is the second generation of this SoC (and CPU) is available `here" -" `__ and offers better " -"perforance/area/features." +"This page only documents the SoC implemented with the first generation of" +" RISC-V CPU created in SpinalHDL. This page does not document the " +"VexRiscV CPU, which is the second generation of this SoC (and CPU) is " +"available `here `__ and offers " +"better performance/area/features." msgstr "" -"本页仅记录使用SpinalHDL创造的第一代用RISC-V CPU实现的SoC。" -"本页面未记录VexRiscV CPU，这是该 SoC（和 CPU）的第二代，可在 `这里 " -"`__ 获得，并提供更好的性能/面积/功能。" +"本页仅记录使用SpinalHDL创造的第一代用RISC-V CPU实现的SoC。本页面未记录VexRiscV CPU，这是该 SoC（和 " +"CPU）的第二代，可在 `这里 `__ " +"获得，并提供更好的性能/面积/功能。" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:17 msgid "" -"Pinsec is the name of a little FPGA SoC fully written in SpinalHDL. Goals of" -" this project are multiple :" +"Pinsec is the name of a little FPGA SoC fully written in SpinalHDL. Goals" +" of this project are multiple :" msgstr "Pinsec是完全用SpinalHDL编写的一个小型FPGA SoC的名称。该项目有多个目的：" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:20 -msgid "" -"Prove that SpinalHDL is a viable HDL alternative in non-trivial projects." +msgid "Prove that SpinalHDL is a viable HDL alternative in non-trivial projects." msgstr "证明SpinalHDL是重要项目中可行的HDL替代方案。" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:21 @@ -71,7 +74,8 @@ msgstr "用于外设的APB3互连" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:30 msgid "" -"RISCV CPU with instruction cache, MUL/DIV extension and interrupt controller" +"RISCV CPU with instruction cache, MUL/DIV extension and interrupt " +"controller" msgstr "具有指令缓存、MUL/DIV扩展和中断控制器的RISCV CPU" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:31 @@ -115,8 +119,9 @@ msgstr "板级支持" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:44 msgid "" "A DE1-SOC FPGA project can be find `here " -"`__" -" with some demo binaries." +"`__ with some demo binaries." msgstr "" "DE1-SOC FPGA项目可以在 `这里 `__ 找到，其中包含一些二进制文件demo。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/riscv.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/riscv.po index ed71d1c9733..5fba8008406 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/riscv.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/riscv.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-13 05:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Legacy/riscv.rst:3 msgid "RiscV" @@ -26,14 +29,13 @@ msgstr "RiscV" #: ../../SpinalHDL/Legacy/riscv.rst:6 msgid "" "This page only documents the first generation of RISC-V CPU created in " -"SpinalHDL. This page does not document the VexRiscV CPU, which is the second" -" generation of this CPU and is available `here " +"SpinalHDL. This page does not document the VexRiscV CPU, which is the " +"second generation of this CPU and is available `here " "`_ and offers better " "performance/area/features." msgstr "" -"本页仅记录在SpinalHDL中创造的第一代RISC-V CPU。本页面未记录VexRiscV " -"CPU，它是该CPU的第二代，可在 `此处 ` " -"获取，并提供更好的性能/面积/特性。" +"本页仅记录在SpinalHDL中创造的第一代RISC-V CPU。本页面未记录VexRiscV CPU，它是该CPU的第二代，可在 `此处 " +"` 获取，并提供更好的性能/面积/特性。" #: ../../SpinalHDL/Legacy/riscv.rst:11 msgid "Features" @@ -113,8 +115,7 @@ msgstr "JTAG Avalon主控 -> 238 LE" msgid "" "big core with MUL/DIV/Full shifter/I$/Interrupt/Debug -> 2200 LE, 1.15 " "DMIPS/Mhz, at least 100 Mhz (with default synthesis option)" -msgstr "带MUL/DIV/全移位器/I$/中断/调试的大核 -> 2200 LE，1.15 DMIPS/" -"Mhz，至少100Mhz（使用默认综合选项）" +msgstr "带MUL/DIV/全移位器/I$/中断/调试的大核 -> 2200 LE，1.15 DMIPS/Mhz，至少100Mhz（使用默认综合选项）" #: ../../SpinalHDL/Legacy/riscv.rst:41 msgid "Base FPGA project" @@ -122,14 +123,14 @@ msgstr "基础FPGA项目" #: ../../SpinalHDL/Legacy/riscv.rst:43 msgid "" -"You can find a DE1-SOC project which integrate two instance of the CPU with " -"MUL/DIV/Full shifter/I$/Interrupt/Debug there :" -msgstr "您可以在这里找到一个DE1-SOC项目，它将两个CPU实例与 MUL/DIV/" -"全移位器/I$/中断/调试集成在一起：" +"You can find a DE1-SOC project which integrate two instance of the CPU " +"with MUL/DIV/Full shifter/I$/Interrupt/Debug there :" +msgstr "您可以在这里找到一个DE1-SOC项目，它将两个CPU实例与 MUL/DIV/全移位器/I$/中断/调试集成在一起：" #: ../../SpinalHDL/Legacy/riscv.rst:45 msgid "" -"https://drive.google.com/drive/folders/0B-CqLXDTaMbKNkktb2k3T3lzcUk?usp=sharing" +"https://drive.google.com/drive/folders/0B-" +"CqLXDTaMbKNkktb2k3T3lzcUk?usp=sharing" msgstr "" "https://drive.google.com/drive/folders/0B-" "CqLXDTaMbKNkktb2k3T3lzcUk?usp=sharing" @@ -168,11 +169,8 @@ msgid "An example target configuration file could be find here :" msgstr "可以在此处找到示例目标配置文件：" #: ../../SpinalHDL/Legacy/riscv.rst:71 -msgid "" -"https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/riscv_spinal.cfg" -msgstr "" -"https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/" -"riscv_spinal.cfg" +msgid "https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/riscv_spinal.cfg" +msgstr "https://github.com/Dolu1990/openocd_riscv/blob/riscv_spinal/tcl/target/riscv_spinal.cfg" #: ../../SpinalHDL/Legacy/riscv.rst:73 msgid "Then you can use the RISCV GDB." @@ -187,11 +185,13 @@ msgid "Documentation" msgstr "文档" #: ../../SpinalHDL/Legacy/riscv.rst:80 +#, fuzzy msgid "" -"Optimise instruction/data caches FMax by moving line hit condition forward " -"into combinatorial paths." +"Optimize instruction/data caches FMax by moving line hit condition " +"forward into combinatorial paths." msgstr "通过将行命中条件向前移动到组合路径来优化指令/数据缓存FMax。" #: ../../SpinalHDL/Legacy/riscv.rst:82 msgid "Contact spinalhdl@gmail.com for more information" msgstr "联系spinhdl@gmail.com了解更多信息" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po index fee0b97a17a..91caa127a36 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po @@ -1,92 +1,97 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:3 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:3 msgid "AHB-Lite3" msgstr "AHB-Lite3" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:6 -msgid "Configuration and instanciation" +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:6 +#, fuzzy +msgid "Configuration and instantiation" msgstr "配置和实例化" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:8 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:8 msgid "" "First each time you want to create a AHB-Lite3 bus, you will need a " -"configuration object. This configuration object is an ``AhbLite3Config`` and" -" has following arguments :" -msgstr "首先，每当您想要创建AHB-Lite3总线时，您都需要一个配置对象。该配置对象是一个 " -"``AhbLite3Config`` 并具有以下参数：" +"configuration object. This configuration object is an ``AhbLite3Config`` " +"and has following arguments :" +msgstr "首先，每当您想要创建AHB-Lite3总线时，您都需要一个配置对象。该配置对象是一个 ``AhbLite3Config`` 并具有以下参数：" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:14 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:14 msgid "Parameter name" msgstr "参数名称" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:15 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:15 msgid "Type" msgstr "类型" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:16 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:16 msgid "Default" msgstr "默认值" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:17 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:17 msgid "Description" msgstr "描述" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:18 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:18 msgid "addressWidth" msgstr "addressWidth" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:19 -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:23 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:19 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:23 msgid "Int" msgstr "Int" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:21 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:21 msgid "Width of HADDR (byte granularity)" msgstr "HADDR的位宽（字节粒度）" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:22 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:22 msgid "dataWidth" msgstr "dataWidth" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:25 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:25 msgid "Width of HWDATA and HRDATA" msgstr "HWDATA和HRDATA的位宽" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:28 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:28 msgid "" -"There is in short how the AHB-Lite3 bus is defined in the SpinalHDL library " -":" +"There is in short how the AHB-Lite3 bus is defined in the SpinalHDL " +"library :" msgstr "简而言之，AHB-Lite3总线在SpinalHDL库中是如下定义的：" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:58 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:58 msgid "There is a short example of usage :" msgstr "这是一个简单的使用示例：" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:74 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:74 msgid "Variations" msgstr "变体" -#: ../../source/SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:76 +#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:76 msgid "" -"There is an AhbLite3Master variation. The only difference is the absence of " -"the ``HREADYOUT`` signal. This variation should only be used by masters " -"while the interconnect and slaves use ``AhbLite3``." +"There is an AhbLite3Master variation. The only difference is the absence " +"of the ``HREADYOUT`` signal. This variation should only be used by " +"masters while the interconnect and slaves use ``AhbLite3``." msgstr "" -"有一个AhbLite3Master变体，唯一的区别是缺少 ``HREADYOUT`` 信号。" -"当互连线和从端使用 ``AhbLite3`` 时，此变体只能由主端使用。" +"有一个AhbLite3Master变体，唯一的区别是缺少 ``HREADYOUT`` 信号。当互连线和从端使用 ``AhbLite3`` " +"时，此变体只能由主端使用。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po index 0835437ef7b..ef7c61b831d 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po @@ -1,44 +1,46 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:3 msgid "Apb3" msgstr "Apb3" #: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:5 -msgid "" -"The AMBA3-APB bus is commonly used to interface low bandwidth peripherals." +msgid "The AMBA3-APB bus is commonly used to interface low bandwidth peripherals." msgstr "AMBA3-APB总线通常用于连接低带宽外设。" #: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:8 -msgid "Configuration and instanciation" +#, fuzzy +msgid "Configuration and instantiation" msgstr "配置和实例化" #: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:10 msgid "" -"First each time you want to create a APB3 bus, you will need a configuration" -" object. This configuration object is an ``Apb3Config`` and has following " -"arguments :" -msgstr "首先，每当您想要创建APB3总线时，您都需要一个配置对象。该配置对象是一个 " -"``Apb3Config`` 并具有以下参数：" +"First each time you want to create a APB3 bus, you will need a " +"configuration object. This configuration object is an ``Apb3Config`` and " +"has following arguments :" +msgstr "首先，每当您想要创建APB3总线时，您都需要一个配置对象。该配置对象是一个 ``Apb3Config`` 并具有以下参数：" #: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:16 msgid "Parameter name" @@ -108,8 +110,7 @@ msgid "Specify the presence of PSLVERROR" msgstr "指定是否出现PSLVERROR" #: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:38 -msgid "" -"There is in short how the APB3 bus is defined in the SpinalHDL library :" +msgid "There is in short how the APB3 bus is defined in the SpinalHDL library :" msgstr "简而言之，APB3总线在SpinalHDL库中定义方式如下：" #: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:54 @@ -146,3 +147,4 @@ msgstr "执行>>运算符相反的操作" #~ msgid "Introduction" #~ msgstr "介绍" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po index b676fef5dbf..576712bf0df 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:2 msgid "Axi4" @@ -28,16 +31,16 @@ msgid "The AXI4 is a high bandwidth bus defined by ARM." msgstr "AXI4是ARM定义的高带宽总线。" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:7 -msgid "Configuration and instanciation" +#, fuzzy +msgid "Configuration and instantiation" msgstr "配置和实例化" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:9 msgid "" -"First each time you want to create a AXI4 bus, you will need a configuration" -" object. This configuration object is an ``Axi4Config`` and has following " -"arguments :" -msgstr "首先，每当您想要创建AXI4总线时，您都需要一个配置对象。该配置对象是一个 " -"``Axi4Config`` 并具有以下参数：" +"First each time you want to create a AXI4 bus, you will need a " +"configuration object. This configuration object is an ``Axi4Config`` and " +"has following arguments :" +msgstr "首先，每当您想要创建AXI4总线时，您都需要一个配置对象。该配置对象是一个 ``Axi4Config`` 并具有以下参数：" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:11 msgid "Note : useXXX specify if the bus has XXX signal present." @@ -167,8 +170,7 @@ msgid "false" msgstr "false" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:72 -msgid "" -"There is in short how the AXI4 bus is defined in the SpinalHDL library :" +msgid "There is in short how the AXI4 bus is defined in the SpinalHDL library :" msgstr "简而言之，AXI4总线在SpinalHDL库中定义方式如下：" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:89 @@ -226,8 +228,8 @@ msgstr "AWR通道可用于传输AR和AW事务。为了分离它们，需要一 #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst msgid "" -"The advantage of this Axi4Shared variation is to use less area, especially " -"in the interconnect." +"The advantage of this Axi4Shared variation is to use less area, " +"especially in the interconnect." msgstr "这种Axi4Shared变体的优点是使用更少的面积，特别是在互连方面。" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:128 @@ -250,8 +252,7 @@ msgstr "X >> Y" msgid "" "Connect X to Y. Able infer default values as specified in the AXI4 " "specification, and also to adapt some width in a safe manner." -msgstr "将X连接到Y。能够像AXI4规范中指定的那样推断默认值，并以安全的方式调整一些位宽" -"。" +msgstr "将X连接到Y。能够像AXI4规范中指定的那样推断默认值，并以安全的方式调整一些位宽。" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:140 msgid "X << Y" @@ -279,3 +280,4 @@ msgstr "返回由X驱动的Axi4ReadOnly总线" #~ msgid "Introduction" #~ msgstr "介绍" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po index 78f0fa66f87..c4c7b0c69b4 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:3 msgid "AvalonMM" @@ -33,34 +36,32 @@ msgstr "能够与APB一样简单" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:8 msgid "" -"Better for than AHB in many application that need bandwidth because AvalonMM" -" has a mode that decouple read response from commands (reduce latency read " -"latency impact)." -msgstr "在许多需要带宽的应用中比AHB更好，因为AvalonMM有一种将读取响应与命令解耦的模式" -"（减少延迟读延迟的影响）。" +"Better for than AHB in many application that need bandwidth because " +"AvalonMM has a mode that decouple read response from commands (reduce " +"latency read latency impact)." +msgstr "在许多需要带宽的应用中比AHB更好，因为AvalonMM有一种将读取响应与命令解耦的模式（减少延迟读延迟的影响）。" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:9 msgid "" -"Less performance than AXI but use much less area (Read and write command use" -" the same handshake channel. The master don't need to store address of " -"pending request to avoid Read/Write hazard)" -msgstr "性能不如AXI，但使用的逻辑面积少得多（读取和写入命令使用相同的握手通道。主端不" -"需要存储挂起请求的地址，从而避免读取/写入冒险）" +"Less performance than AXI but use much less area (Read and write command " +"use the same handshake channel. The master don't need to store address of" +" pending request to avoid Read/Write hazard)" +msgstr "性能不如AXI，但使用的逻辑面积少得多（读取和写入命令使用相同的握手通道。主端不需要存储挂起请求的地址，从而避免读取/写入冒险）" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:12 -msgid "Configuration and instanciation" +#, fuzzy +msgid "Configuration and instantiation" msgstr "配置和实例化" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:14 msgid "" "The ``AvalonMM`` Bundle has a construction argument ``AvalonMMConfig``. " -"Because of the flexible nature of the Avalon bus, the ``AvalonMMConfig`` as " -"many configuration elements. For more information the Avalon spec could be " -"find on the intel website." +"Because of the flexible nature of the Avalon bus, the ``AvalonMMConfig`` " +"as many configuration elements. For more information the Avalon spec " +"could be find on the intel website." msgstr "" "``AvalonMM`` 包有一个构造参数 ``AvalonMMConfig`` 。由于Avalon总线的灵活性， " -"``AvalonMMConfig`` " -"有很多配置元素。有关Avalon规范的更多信息，请访问英特尔网站。" +"``AvalonMMConfig`` 有很多配置元素。有关Avalon规范的更多信息，请访问英特尔网站。" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:46 msgid "This configuration class has also some functions :" @@ -107,8 +108,8 @@ msgstr "返回一个类似的配置，但禁用所有读取属性" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:63 msgid "" -"This configuration companion object has also some functions to provide some " -"``AvalonMMConfig`` templates :" +"This configuration companion object has also some functions to provide " +"some ``AvalonMMConfig`` templates :" msgstr "这个配置伴随对象还有一些函数来提供一些 ``AvalonMMConfig`` 模板：" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:72 @@ -132,9 +133,9 @@ msgid "bursted(addressWidth,dataWidth,burstCountWidth)" msgstr "bursted(addressWidth,dataWidth,burstCountWidth)" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:80 -msgid "" -"Return a configuration with variable latency read and burst capabilities" +msgid "Return a configuration with variable latency read and burst capabilities" msgstr "返回一个具有可变延迟读取和突发功能的配置" #~ msgid "Introduction" #~ msgstr "介绍" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po index 3e92fd6af10..c85c688465e 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po @@ -1,32 +1,37 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:3 msgid "Tilelink" msgstr "Tilelink" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:6 -msgid "Configuration and instanciation" +#, fuzzy +msgid "Configuration and instantiation" msgstr "配置和实例化" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:8 msgid "" -"There is a short example to define two non coherent tilelink bus instance " -"and connect them:" +"There is a short example to define two non coherent tilelink bus instance" +" and connect them:" msgstr "这是一个简单的示例，它定义了两个不相干的tilelink总线实例并将它们连接起来：" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:22 @@ -34,12 +39,11 @@ msgid "Here is the same as above, but with coherency channels" msgstr "这里与上面相同，但是具有一致性通道" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:43 +#, fuzzy msgid "" -"Those above where for the hardware instanciation, the thing is that it is " -"the simple / easy part. When things goes into SoC / memory coherency, you " -"kind of need an additional layer to negociate / propagate parameters all " -"around. That's what tilelink.fabric.Node is about." -msgstr "" -"以上的内容是关于硬件实例化的，这是简单/容易的部分。当涉及SoC/" -"内存一致性时，您可能需要一个额外的层来协调/传递参数。这就是tilelink.fabric." -"Node的作用。" +"Those above where for the hardware instantiation, the thing is that it is" +" the simple / easy part. When things goes into SoC / memory coherency, " +"you kind of need an additional layer to negotiate / propagate parameters " +"all around. That's what tilelink.fabric.Node is about." +msgstr "以上的内容是关于硬件实例化的，这是简单/容易的部分。当涉及SoC/内存一致性时，您可能需要一个额外的层来协调/传递参数。这就是tilelink.fabric.Node的作用。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po index 1649b147dcc..260e598c6a2 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po @@ -1,39 +1,43 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-02 00:23+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:3 msgid "tilelink.fabric.Node" msgstr "tilelink.fabric.Node" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:5 +#, fuzzy msgid "" "tilelink.fabric.Node is an additional layer over the regular tilelink " -"hardware instanciation which handle negociation and parameters propagation " -"at a SoC level." -msgstr "tilelink.fabric." -"Node是常规tilelink硬件实例之上的附加层，用于处理SoC级别的协调和参数传递。" +"hardware instantiation which handle negotiation and parameters " +"propagation at a SoC level." +msgstr "tilelink.fabric.Node是常规tilelink硬件实例之上的附加层，用于处理SoC级别的协调和参数传递。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:7 +#, fuzzy msgid "" -"It is mostly based on the Fiber API, which allows to create elaboration time" -" fibers (user-space threads), allowing to schedule future parameter " -"propagation / negociation and hardware elaboration." -msgstr "它主要基于Fiber API，它允许创建精化时间纤程（用户空间线程），从而允许确定未来" -"的参数传递/协调和硬件生成。" +"It is mostly based on the Fiber API, which allows to create elaboration " +"time fibers (user-space threads), allowing to schedule future parameter " +"propagation / negotiation and hardware elaboration." +msgstr "它主要基于Fiber API，它允许创建精化时间纤程（用户空间线程），从而允许确定未来的参数传递/协调和硬件生成。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:9 msgid "A Node can be created in 3 ways :" @@ -41,10 +45,9 @@ msgstr "可以通过3种方式创建节点(Node)：" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:11 msgid "" -"tilelink.fabric.Node.down() : To create a node which can connect downward " -"(toward slaves), so it would be used in a CPU / DMA / bridges agents" -msgstr "tilelink.fabric.Node." -"down()：创建一个可以向下连接（向从端）的节点，因此它将用于CPU/DMA/桥的代理" +"tilelink.fabric.Node.down() : To create a node which can connect downward" +" (toward slaves), so it would be used in a CPU / DMA / bridges agents" +msgstr "tilelink.fabric.Node.down()：创建一个可以向下连接（向从端）的节点，因此它将用于CPU/DMA/桥的代理" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:12 msgid "tilelink.fabric.Node() : To create an intermediate nodes" @@ -53,10 +56,9 @@ msgstr "tilelink.fabric.Node()：创建中间节点" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:13 msgid "" "tilelink.fabric.Node.up() : To create a node which can connect upward " -"(toward masters), so it would be used in peripherals / memories / bridges " -"agents" -msgstr "tilelink.fabric.Node." -"up()：创建一个可以向上连接（向主端）的节点，因此它将用于外设/存储器/桥的代理" +"(toward masters), so it would be used in peripherals / memories / bridges" +" agents" +msgstr "tilelink.fabric.Node.up()：创建一个可以向上连接（向主端）的节点，因此它将用于外设/存储器/桥的代理" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:15 msgid "Nodes mostly have the following attributes :" @@ -74,41 +76,36 @@ msgstr "m2s.proposed : Handle[tilelink.M2sSupport]；由向上连接提出的功 #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:19 msgid "" -"m2s.supported : Handle[tilelink.M2sSupport] : The set of feature supported " -"by the downward connections" +"m2s.supported : Handle[tilelink.M2sSupport] : The set of feature " +"supported by the downward connections" msgstr "m2s.supported : Handle[tilelink.M2sSupport]: 向下连接支持的功能集" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:20 -msgid "" -"m2s.parameter : Handle[tilelink.M2sParameter] : The final bus parameter" +msgid "m2s.parameter : Handle[tilelink.M2sParameter] : The final bus parameter" msgstr "m2s.parameter : Handle[tilelink.M2sParameter]: 最终的总线参数" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:22 msgid "" -"You can note that they all are Handles. Handle is a way in SpinalHDL to have" -" share a value between fibers. If a fiber read a Handle while this one has " -"no value yet, it will block the execution of that fiber until another fiber " -"provide a value to the Handle." -msgstr "" -"您可以注意到它们都是句柄。Handle是SpinalHDL中在纤程之间共享值的一种方式。如果" -"一个纤程读取一个句柄，而这个句柄还没有值，它将阻止该纤程的执行，直到另一个纤" -"程向该句柄提供一个值。" +"You can note that they all are Handles. Handle is a way in SpinalHDL to " +"have share a value between fibers. If a fiber read a Handle while this " +"one has no value yet, it will block the execution of that fiber until " +"another fiber provide a value to the Handle." +msgstr "您可以注意到它们都是句柄。Handle是SpinalHDL中在纤程之间共享值的一种方式。如果一个纤程读取一个句柄，而这个句柄还没有值，它将阻止该纤程的执行，直到另一个纤程向该句柄提供一个值。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:24 +#, fuzzy msgid "" -"There is also a set of attribues like m2s, but reversed (named s2m) which " -"specify the parameters for the transactions initiated by the slave side of " -"the interconnect (ex memory coherency)." -msgstr "还有一组属性，类似于m2s，但是反向的（名为s2m），它们指定了由互连的从端发起的" -"事务的参数（例如内存一致性）。" +"There is also a set of attributes like m2s, but reversed (named s2m) " +"which specify the parameters for the transactions initiated by the slave " +"side of the interconnect (ex memory coherency)." +msgstr "还有一组属性，类似于m2s，但是反向的（名为s2m），它们指定了由互连的从端发起的事务的参数（例如内存一致性）。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:26 msgid "" -"There is two talks which where introducing the tilelink.fabric.Node. Those " -"talk may not exactly follow the actual syntax, they are still follow the " -"concepts :" -msgstr "有两个演讲介绍了tilelink.fabric." -"Node。这两个演讲可能并不完全遵循实际语法，它们仍然遵循以下概念：" +"There is two talks which where introducing the tilelink.fabric.Node. " +"Those talk may not exactly follow the actual syntax, they are still " +"follow the concepts :" +msgstr "有两个演讲介绍了tilelink.fabric.Node。这两个演讲可能并不完全遵循实际语法，它们仍然遵循以下概念：" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:28 msgid "Introduction : https://youtu.be/hVi9xOGuuek" @@ -116,8 +113,8 @@ msgstr "介绍：https://youtu.be/hVi9xOGuuek" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:29 msgid "" -"In depth : " -"https://peertube.f-si.org/videos/watch/bcf49c84-d21d-4571-a73e-96d7eb89e907" +"In depth : https://peertube.f-si.org/videos/watch/bcf49c84-d21d-4571" +"-a73e-96d7eb89e907" msgstr "" "深入：https://peertube.f-si.org/videos/watch/bcf49c84-d21d-4571-a73e-" "96d7eb89e907" @@ -131,8 +128,7 @@ msgid "Here is an example of a simple fictive SoC toplevel :" msgstr "以下是一个简单的虚拟SoC顶层设计示例：" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:46 -msgid "" -"You can also define intermediate nodes in the interconnect as following :" +msgid "You can also define intermediate nodes in the interconnect as following :" msgstr "您还可以定义互连中的中间节点，如下所示：" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:70 @@ -141,8 +137,8 @@ msgstr "GPIOFiber示例" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:72 msgid "" -"GpioFiber is a simple tilelink peripheral which can read / drive a 32 bits " -"tristate array." +"GpioFiber is a simple tilelink peripheral which can read / drive a 32 " +"bits tristate array." msgstr "GpioFiber是一个简单的tilelink外设，可以读取/驱动32位三态阵列。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:116 @@ -166,12 +162,9 @@ msgid "" "One particularity of Tilelink, is that it assumes a master will not emit " "requests to a unmapped memory space. To allow a master to identify what " "memory access it is allowed to do, you can use the " -"spinal.lib.system.tag.MemoryConnection.getMemoryTransfers tool as following " -":" -msgstr "" -"Tilelink的一个特殊性是，它假设主端不会向未映射的内存空间发出请求。为了让主机" -"识别允许访问哪些内存，您可以使用spinal.lib.system.tag.MemoryConnection." -"getMemoryTransfers工具，如下所示：" +"spinal.lib.system.tag.MemoryConnection.getMemoryTransfers tool as " +"following :" +msgstr "Tilelink的一个特殊性是，它假设主端不会向未映射的内存空间发出请求。为了让主机识别允许访问哪些内存，您可以使用spinal.lib.system.tag.MemoryConnection.getMemoryTransfers工具，如下所示：" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:206 msgid "If you run this in the Cpu's fiber, in the following soc :" @@ -183,8 +176,8 @@ msgstr "你会得到 ：" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:236 msgid "" -"\"through=\" specify the chain of address transformations done to reach the " -"target." +"\"through=\" specify the chain of address transformations done to reach " +"the target." msgstr "\"through=\" 指定了到达目标所需的地址转换链。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:237 @@ -196,11 +189,11 @@ msgid "\"OT\" means OffsetTransformer(offset)" msgstr "\"OT\" 表示OffsetTransformer(offset)" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:240 +#, fuzzy msgid "" "Note that you can also add PMA (Physical Memory Attributes) to nodes and " -"retreives them via this getMemoryTransfers utilities." -msgstr "请注意，您还可以将PMA（物理内存属性）添加到节点，并通过此getMemoryTransfers工" -"具检索它们。" +"retrieves them via this getMemoryTransfers utilities." +msgstr "请注意，您还可以将PMA（物理内存属性）添加到节点，并通过此getMemoryTransfers工具检索它们。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:242 msgid "The currently defined PMA are :" @@ -214,12 +207,9 @@ msgstr "getMemoryTransfers工具依赖于专用的SpinalTag：" msgid "" "That SpinalTag can be used applied to both ends of a given memory bus " "connection to keep this connection discoverable at elaboration time, " -"creating a graph of MemoryConnection. One good thing about it is that is is " -"bus agnostic, meaning it isn't tilelink specific." -msgstr "" -"该SpinalTag可以应用于给定内存总线连接的两端，以保持该连接在生成时可被发现，从" -"而创建内存连接(MemoryConnection)图。它的一个优点是它与总线无关，这意味着它不" -"是tilelink特有的。" +"creating a graph of MemoryConnection. One good thing about it is that is " +"is bus agnostic, meaning it isn't tilelink specific." +msgstr "该SpinalTag可以应用于给定内存总线连接的两端，以保持该连接在生成时可被发现，从而创建内存连接(MemoryConnection)图。它的一个优点是它与总线无关，这意味着它不是tilelink特有的。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:274 msgid "Example WidthAdapter" @@ -228,3 +218,4 @@ msgstr "位宽适配器(WidthAdapter)示例" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:276 msgid "The width adapter is a simple example of bridge." msgstr "位宽适配器是桥的一个简单例子。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po index 33b54dc2f0e..1cd953a46cd 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:3 msgid "USB device" @@ -28,7 +31,8 @@ msgid "Here exists a USB device controller in the SpinalHDL library." msgstr "SpinalHDL库中存在一个USB设备控制器。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:7 -msgid "A few bullet points to summarise support:" +#, fuzzy +msgid "A few bullet points to summarize support:" msgstr "用几个要点总结支持的功能：" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:9 @@ -37,33 +41,35 @@ msgstr "实现了允许CPU配置和管理端点" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:10 msgid "" -"A internal ram which store the endpoints states and transactions descriptors" +"A internal ram which store the endpoints states and transactions " +"descriptors" msgstr "存储端点状态和事务描述符的内部RAM" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:11 -msgid "Up to 16 endpoints (for virtualy no price)" +#, fuzzy +msgid "Up to 16 endpoints (for virtually no price)" msgstr "多达6个端点（几乎没有额外开销）" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:12 -msgid "Support USB host full speed (12Mbps)" +#, fuzzy +msgid "Support USB host full speed (12 Mbps)" msgstr "支持全速USB主机（12Mbps）" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:13 msgid "" "Test on linux using its own driver " "(https://github.com/SpinalHDL/linux/blob/dev/drivers/usb/gadget/udc/spinal_udc.c)" -msgstr "" -"在Linux上使用自己的驱动程序进行测试(https://github.com/SpinalHDL/linux/blob/" -"dev/drivers/usb/gadget/udc/spinal_udc.c)" +msgstr "在Linux上使用自己的驱动程序进行测试(https://github.com/SpinalHDL/linux/blob/dev/drivers/usb/gadget/udc/spinal_udc.c)" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:14 -msgid "Bmb memory interace for the configuration" +#, fuzzy +msgid "Bmb memory interface for the configuration" msgstr "用于配置的Bmb内存接口" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:15 msgid "" -"Require a clock for the internal phy which is a multiple of 12 Mhz at least " -"48 Mhz" +"Require a clock for the internal phy which is a multiple of 12 Mhz at " +"least 48 Mhz" msgstr "内部物理层需要一个时钟，该时钟需为12 Mhz的倍数，至少48 Mhz" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:16 @@ -95,17 +101,12 @@ msgid "Deployments :" msgstr "部署：" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:27 -msgid "" -"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux" -msgstr "" -"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/" -"ArtyA7SmpLinux" +msgid "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux" +msgstr "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:28 -msgid "" -"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp" -msgstr "" -"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp" +msgid "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp" +msgstr "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:32 msgid "Architecture" @@ -121,22 +122,22 @@ msgstr "一小部分控制寄存器" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:37 msgid "" -"A internal ram used to store the endpoint status, the transfer descriptors " -"and the endpoint 0 SETUP data." +"A internal ram used to store the endpoint status, the transfer " +"descriptors and the endpoint 0 SETUP data." msgstr "一个用于存储端点状态、传输描述符和端点0配置数据的内部RAM。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:39 msgid "" -"A linked list of descriptors for each endpoint in order to handle the USB " -"IN/OUT transactions and data." +"A linked list of descriptors for each endpoint in order to handle the USB" +" IN/OUT transactions and data." msgstr "每个端点的描述符链表时用于处理USB出入(IN/OUT)事务和数据。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:41 msgid "" -"The endpoint 0 manage the IN/OUT transactions like all the other endpoints " -"but has some additional hardware to manage the SETUP transactions :" -msgstr "端点0也像所有其他端点一样管理出入USB的传输事务，但也会有一些额外的硬件来管理" -"设置(SETUP)事务：" +"The endpoint 0 manage the IN/OUT transactions like all the other " +"endpoints but has some additional hardware to manage the SETUP " +"transactions :" +msgstr "端点0也像所有其他端点一样管理出入USB的传输事务，但也会有一些额外的硬件来管理设置(SETUP)事务：" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:43 msgid "Its linked list is cleared on each setup transactions" @@ -158,10 +159,9 @@ msgstr "寄存器" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:50 msgid "" -"Note that all registers and memories of the controller are only accessible " -"in 32 bits word access, bytes access isn't supported." -msgstr "请注意，控制器的所有寄存器和存储器只能以32位字的访问方式进行访问，不支持字节" -"访问。" +"Note that all registers and memories of the controller are only " +"accessible in 32 bits word access, bytes access isn't supported." +msgstr "请注意，控制器的所有寄存器和存储器只能以32位字的访问方式进行访问，不支持字节访问。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:53 msgid "FRAME (0xFF00)" @@ -249,9 +249,10 @@ msgid "6-0" msgstr "6-0" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:68 +#, fuzzy msgid "" -"The device will only listen at tokens with the specified address This field " -"is automaticaly cleared on usb reset events" +"The device will only listen at tokens with the specified address This " +"field is automatically cleared on usb reset events" msgstr "设备将仅侦听具有指定地址的令牌，该字段在USB复位事件发生时自动清除" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:71 @@ -277,22 +278,24 @@ msgid "9" msgstr "9" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:73 +#, fuzzy msgid "" -"Set the enable (see above) on the next EP0 IN tocken completion Cleared by " -"the hardware after any EP0 completion" +"Set the enable (see above) on the next EP0 IN token completion Cleared by" +" the hardware after any EP0 completion" msgstr "在下一个EP0 IN令牌完成时置位enable（见上文），在任何EP0完成后由硬件清零" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:77 +#, fuzzy msgid "" -"The idea here is to keep the whole register cleared until a USB SET_ADDRESS " -"setup packet is received on EP0. At that moment, you can set the address and" -" the trigger field, then provide the IN zero length descriptor to EP0 to " -"finalise the SET_ADDRESS sequance. The controller will then automaticaly " -"turn on the address filtering at the completion of that descriptor." +"The idea here is to keep the whole register cleared until a USB " +"SET_ADDRESS setup packet is received on EP0. At that moment, you can set " +"the address and the trigger field, then provide the IN zero length " +"descriptor to EP0 to finalize the SET_ADDRESS sequence. The controller " +"will then automatically turn on the address filtering at the completion " +"of that descriptor." msgstr "" -"这里的想法是在EP0上收到USB SET_ADDRESS的设置(setup)数据包前，保持整个寄存器清" -"零。此时，您可以设置地址和触发字段，然后向EP0提供IN零长度描述符以完成SET_ADDR" -"ESS序列。控制器将在该描述符完成时自动打开地址过滤。" +"这里的想法是在EP0上收到USB " +"SET_ADDRESS的设置(setup)数据包前，保持整个寄存器清零。此时，您可以设置地址和触发字段，然后向EP0提供IN零长度描述符以完成SET_ADDRESS序列。控制器将在该描述符完成时自动打开地址过滤。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:82 msgid "INTERRUPT (0xFF08)" @@ -397,15 +400,12 @@ msgstr "暂停HALT (0xFF0C)" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:106 msgid "" -"This register allows placement of a single endpoint into a dormant state in " -"order to ensure atomicity of CPU operations, allowing to do things as " -"read/modify/write on the endpoint registers and descriptors. The peripheral " -"will return NAK if the given endpoint is addressed by the usb host while " -"halt is enabled and the endpoint is enabled." -msgstr "" -"该寄存器允许将单个端点置于休眠状态，以确保CPU操作的原子性，从而允许在端点寄存" -"器和描述符上执行读/修改/写操作。如果USB主机在暂停启用且端点启用的情况下寻址给" -"定端点，那么外设将返回NAK。" +"This register allows placement of a single endpoint into a dormant state " +"in order to ensure atomicity of CPU operations, allowing to do things as " +"read/modify/write on the endpoint registers and descriptors. The " +"peripheral will return NAK if the given endpoint is addressed by the usb " +"host while halt is enabled and the endpoint is enabled." +msgstr "该寄存器允许将单个端点置于休眠状态，以确保CPU操作的原子性，从而允许在端点寄存器和描述符上执行读/修改/写操作。如果USB主机在暂停启用且端点启用的情况下寻址给定端点，那么外设将返回NAK。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:112 msgid "endpointId" @@ -522,9 +522,10 @@ msgid "ENDPOINTS (0x0000 - 0x003F)" msgstr "端点ENDPOINTS (0x0000 - 0x003F)" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:147 +#, fuzzy msgid "" -"The endpoints status are stored at the begining of the internal ram over one" -" 32 bits word each." +"The endpoints status are stored at the beginning of the internal ram over" +" one 32 bits word each." msgstr "端点状态存储在内部RAM的开头，每个端点状态有一个32位字。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:152 @@ -538,7 +539,8 @@ msgid "RW" msgstr "RW" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:152 -msgid "If not set, the endpoint will ignore all the trafic" +#, fuzzy +msgid "If not set, the endpoint will ignore all the traffic" msgstr "如果不设置，端点将忽略所有流量" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:154 @@ -563,8 +565,8 @@ msgstr "dataPhase" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:158 msgid "" -"Specify the IN/OUT data PID used. '0' => DATA0. This field is also updated " -"by the controller." +"Specify the IN/OUT data PID used. '0' => DATA0. This field is also " +"updated by the controller." msgstr "指定使用的出入数据PID。 '0' => DATA0。该字段也由控制器更新。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:161 @@ -607,16 +609,16 @@ msgid "" "Then the there is a few cases : - Either you have the stall or nack flag " "set, and so, the controller will always respond with the corresponding " "responses - Either, for EP0 setup request, the controller will not use " -"descriptors, but will instead write the data into the SETUP_DATA register, " -"and ACK - Either you have a empty linked list (head==0) in which case it " -"will answer NACK - Either you have at least one descriptor pointed by head, " -"in which case it will execute it and ACK if all was going smooth" +"descriptors, but will instead write the data into the SETUP_DATA " +"register, and ACK - Either you have a empty linked list (head==0) in " +"which case it will answer NACK - Either you have at least one descriptor " +"pointed by head, in which case it will execute it and ACK if all was " +"going smooth" msgstr "" "那么有几种情况： -要么设置了stall或nack标志，所以控制器将始终响应相应的响应 " -"-要么，对于EP0设置请求，控制器不会使用描述符，" -"而是会将数据写入SETUP_DATA寄存器和ACK -要么你有一个空链表 (head==0)，" -"在这种情况下它将响应NACK -要么你至少有一个由head指向的描述符，在这种情况下，" -"它将执行该描述符，并在一切顺利时进行ACK" +"-要么，对于EP0设置请求，控制器不会使用描述符，而是会将数据写入SETUP_DATA寄存器和ACK -要么你有一个空链表 " +"(head==0)，在这种情况下它将响应NACK " +"-要么你至少有一个由head指向的描述符，在这种情况下，它将执行该描述符，并在一切顺利时进行ACK" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:180 msgid "SETUP_DATA (0x0040 - 0x0047)" @@ -624,8 +626,8 @@ msgstr "设置数据SETUP_DATA (0x0040 - 0x0047)" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:182 msgid "" -"When endpoint 0 receives a SETUP transaction, the data of the transaction " -"will be stored in this location." +"When endpoint 0 receives a SETUP transaction, the data of the transaction" +" will be stored in this location." msgstr "当端点0接收到SETUP事务时，该事务的数据将存储在该位置。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:185 @@ -634,13 +636,13 @@ msgstr "描述符" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:187 msgid "" -"Descriptors allows to specify how an endpoint needs to handle the data phase" -" of IN/OUT transactions. They are stored in the internal ram, can be linked " -"together via their linked lists and need to be aligned on 16 bytes " -"boundaries" +"Descriptors allows to specify how an endpoint needs to handle the data " +"phase of IN/OUT transactions. They are stored in the internal ram, can be" +" linked together via their linked lists and need to be aligned on 16 " +"bytes boundaries" msgstr "" -"描述符允许指定一个端点需要如何处理出入(IN/OUT)事务的数据阶段。它们存储在内部 " -"RAM 中，可以通过链表链接在一起，并且需要在16字节边界上对齐" +"描述符允许指定一个端点需要如何处理出入(IN/OUT)事务的数据阶段。它们存储在内部 RAM " +"中，可以通过链表链接在一起，并且需要在16字节边界上对齐" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:191 msgid "Word" @@ -708,20 +710,20 @@ msgstr "completionOnFull" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:207 msgid "" -"Normally, a descriptor completion only occurs when a USB transfer is smaller" -" than the maxPacketSize. But if this field is set, then when the descriptor " -"become full is also a considered as a completion event. (offset == length)" +"Normally, a descriptor completion only occurs when a USB transfer is " +"smaller than the maxPacketSize. But if this field is set, then when the " +"descriptor become full is also a considered as a completion event. " +"(offset == length)" msgstr "" -"通常，描述符补全只会在USB传输小于maxPacketSize时发生。但如果置位了该字段，那" -"么当描述符被填满时也被视为事件已完成。(offset == length)" +"通常，描述符补全只会在USB传输小于maxPacketSize时发生。但如果置位了该字段，那么当描述符被填满时也被视为事件已完成。(offset " +"== length)" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:212 msgid "data1OnCompletion" msgstr "data1OnCompletion" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:212 -msgid "" -"force the endpoint dataPhase to DATA1 on the completion of the descriptor" +msgid "force the endpoint dataPhase to DATA1 on the completion of the descriptor" msgstr "描述符完成时强制端点dataPhase为DATA1" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:215 @@ -734,13 +736,13 @@ msgstr "..." #: ../../SpinalHDL/Libraries/Com/usb_device.rst:218 msgid "" -"Note, if the controller receives a frame where the IN/OUT does not match the" -" descriptor IN/OUT, the frame will be ignored." +"Note, if the controller receives a frame where the IN/OUT does not match " +"the descriptor IN/OUT, the frame will be ignored." msgstr "请注意，如果控制器接收到IN/OUT与描述符IN/OUT不匹配的帧，那么该帧将被忽略。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:220 -msgid "" -"Also, to initialise a descriptor, the CPU should set the code field to 0xF" +#, fuzzy +msgid "Also, to initialize a descriptor, the CPU should set the code field to 0xF" msgstr "此外，要初始化描述符，CPU应将代码字段设置为0xF" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:223 @@ -752,3 +754,4 @@ msgstr "用法" #~ msgid "RC" #~ msgstr "RC" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po index 11c28fbeef6..c5d365d3c5c 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:3 msgid "USB OHCI" @@ -28,13 +31,14 @@ msgid "Here exists a USB OHCi controller (host) in the SpinalHDL library." msgstr "SpinalHDL库中有USB OHCi控制器（主机）。" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:7 -msgid "A few bullet points to summarise support:" +#, fuzzy +msgid "A few bullet points to summarize support:" msgstr "用几个要点总结支持的功能：" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:9 msgid "" -"It follow the `OpenHCI Open Host Controller Interface Specification for USB`" -" specification (OHCI)." +"It follow the `OpenHCI Open Host Controller Interface Specification for " +"USB` specification (OHCI)." msgstr "它遵循 `OpenHCI USB开放式主机控制接口规范` (OHCI)。" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:10 @@ -44,9 +48,10 @@ msgid "" msgstr "它已经与上游的linux/uboot OHCI驱动兼容。（tinyUSB上也有OHCI驱动）" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:11 +#, fuzzy msgid "" -"This provides USB host full speed and low speed capabilities (12Mbps and " -"1.5Mbps)" +"This provides USB host full speed and low speed capabilities (12 Mbps and" +" 1.5 Mbps)" msgstr "它提供了USB主机全速和低速功能（12Mbps和1.5Mbps）" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:12 @@ -62,13 +67,14 @@ msgid "Bmb memory interface for DMA accesses" msgstr "用于DMA访问的Bmb存储器接口" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:15 -msgid "Bmb memory interace for the configuration" +#, fuzzy +msgid "Bmb memory interface for the configuration" msgstr "用于配置的Bmb内存接口" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:16 msgid "" -"Requires a clock for the internal phy which is a multiple of 12 Mhz at least" -" 48 Mhz" +"Requires a clock for the internal phy which is a multiple of 12 Mhz at " +"least 48 Mhz" msgstr "内部物理层需要一个时钟，该时钟需要为12 Mhz的倍数，至少48 Mhz" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:17 @@ -105,8 +111,8 @@ msgstr "限制：" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:29 msgid "" -"Some USB hub (had one so far) do not like having a full speed host with low " -"speed devices attached." +"Some USB hub (had one so far) do not like having a full speed host with " +"low speed devices attached." msgstr "某些USB集线器（目前已有一个）对将低速设备连接至全速主机的模式不友好。" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:30 @@ -117,8 +123,8 @@ msgstr "某些现代设备无法在USB全速上运行（例如：Gbps以太网 #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:31 msgid "" -"Require memory coherency with the CPU (or the cpu need to be able to flush " -"its data cache in the driver)" +"Require memory coherency with the CPU (or the cpu need to be able to " +"flush its data cache in the driver)" msgstr "需要与CPU保持内存一致性（或者需要CPU能够刷新驱动中的数据缓存）" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:33 @@ -126,17 +132,12 @@ msgid "Deployments :" msgstr "部署：" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:35 -msgid "" -"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux" -msgstr "" -"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/" -"ArtyA7SmpLinux" +msgid "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux" +msgstr "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:36 -msgid "" -"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp" -msgstr "" -"https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp" +msgid "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp" +msgstr "https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:39 msgid "Usage" @@ -144,3 +145,4 @@ msgstr "用法" #~ msgid "Introduction" #~ msgstr "介绍" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po index 261398f5718..f05ca62030d 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po @@ -1,35 +1,38 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-13 05:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:3 msgid "QSysify" msgstr "QSysify" #: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:5 +#, fuzzy msgid "" -"QSysify is a tool which is able to generate a QSys IP (tcl script) from a " -"SpinalHDL component by analysing its IO definition. It currently implement " -"the following interfaces features :" -msgstr "QSysify是一个能够通过分析SpinalHDL组件的IO定义来生成QSys " -"IP（tcl脚本）的工具。目前它实现了以下接口特性：" +"QSysify is a tool which is able to generate a QSys IP (tcl script) from a" +" SpinalHDL component by analyzing its IO definition. It currently " +"implement the following interfaces features :" +msgstr "QSysify是一个能够通过分析SpinalHDL组件的IO定义来生成QSys IP（tcl脚本）的工具。目前它实现了以下接口特性：" #: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:7 msgid "Master/Slave AvalonMM" @@ -67,10 +70,9 @@ msgstr "以UART控制器为例：" #: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:30 msgid "" -"The following ``main`` will generate the Verilog and the QSys TCL script " -"with io.bus as an AvalonMM and io.uart as a conduit :" -msgstr "下面的 ``main`` 将生成Verilog和QSys TCL脚本，其中io.bus将作为AvalonMM总线，io" -".uart作为导线：" +"The following ``main`` will generate the Verilog and the QSys TCL script" +" with io.bus as an AvalonMM and io.uart as a conduit :" +msgstr "下面的 ``main`` 将生成Verilog和QSys TCL脚本，其中io.bus将作为AvalonMM总线，io.uart作为导线：" #: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:48 msgid "tags" @@ -96,10 +98,8 @@ msgid "" "``emitter`` `(as you can see here) " "`_" msgstr "" -"基本上，QSysify工具可以使用接口 ``emitter`` 列表进行设置 " -"`（如您在此处看到的） `" +"基本上，QSysify工具可以使用接口 ``emitter`` 列表进行设置 `（如您在此处看到的） " +"`" #: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:78 msgid "" @@ -107,9 +107,10 @@ msgid "" "`QSysifyInterfaceEmiter " "`_" msgstr "" -"您可以通过创建一个扩展 `QSysifyInterfaceEmiter `_ 的新类来创建自己的发射器(emitter)" +"您可以通过创建一个扩展 `QSysifyInterfaceEmiter " +"`_ 的新类来创建自己的发射器(emitter)" #~ msgid "Introduction" #~ msgstr "介绍" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po index ff65ff64479..e3b8330ae95 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po @@ -1,116 +1,124 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:7 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:7 msgid "Plic Mapper" msgstr "Plic映射器" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:9 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:9 msgid "" "The PLIC Mapper defines the register generation and access for a PLIC " "(Platform Level Interrupt Controller." msgstr "PLIC映射器定义了PLIC（平台级中断控制器）的寄存器生成和访问。" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:12 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:12 msgid "``PlicMapper.apply``" msgstr "``PlicMapper.apply``" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:14 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:14 msgid "" -"``(bus: BusSlaveFactory, mapping: PlicMapping)(gateways : Seq[PlicGateway], " -"targets : Seq[PlicTarget])``" +"``(bus: BusSlaveFactory, mapping: PlicMapping)(gateways : " +"Seq[PlicGateway], targets : Seq[PlicTarget])``" msgstr "" -"``(bus: BusSlaveFactory, mapping: PlicMapping)(gateways : Seq[PlicGateway], " -"targets : Seq[PlicTarget])``" +"``(bus: BusSlaveFactory, mapping: PlicMapping)(gateways : " +"Seq[PlicGateway], targets : Seq[PlicTarget])``" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:16 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:16 msgid "args for PlicMapper:" msgstr "PlicMapper的参数：" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:18 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:18 msgid "**bus**: bus to which this ctrl is attached" msgstr "**bus**：连接此控制器的总线" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:19 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:19 msgid "**mapping**: a mapping configuration (see above)" msgstr "**mapping**：一个映射配置（见上文）" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:20 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:20 msgid "" -"**gateways**: a sequence of PlicGateway (interrupt sources) to generate the " -"bus access control" +"**gateways**: a sequence of PlicGateway (interrupt sources) to generate " +"the bus access control" msgstr "**gateways**：用于生成总线访问控制的PlicGateway（中断源）序列" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:21 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:21 msgid "" -"**targets**: the sequence of PlicTarget (eg. multiple cores) to generate the" -" bus access control" +"**targets**: the sequence of PlicTarget (eg. multiple cores) to generate " +"the bus access control" msgstr "**targets**：生成总线访问控制的PlicTarget序列（如：多核）" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:24 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:24 msgid "" "It follows the interface given by riscv: https://github.com/riscv/riscv-" "plic-spec/blob/master/riscv-plic.adoc" msgstr "" -"它遵循riscv提供的接口：https://github.com/riscv/riscv-plic-spec/blob/master/" -"riscv-plic.adoc" +"它遵循riscv提供的接口：https://github.com/riscv/riscv-plic-spec/blob/master/riscv-" +"plic.adoc" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:26 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:26 msgid "As of now, two memory mappings are available :" msgstr "截至目前，有两种内存映射可用：" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:29 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:29 msgid "``PlicMapping.sifive``" msgstr "``PlicMapping.sifive``" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:30 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:30 msgid "" "Follows the SiFive PLIC mapping (eg. `E31 core complex Manual " "`_" " ), basically a full fledged PLIC" msgstr "" -"遵循SiFive的PLIC映射（例如 `E31核心复合手册 `_ )，基本上是一个成熟的PLIC" +"遵循SiFive的PLIC映射（例如 `E31核心复合手册 " +"`_" +" )，基本上是一个成熟的PLIC" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:33 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:33 msgid "``PlicMapping.light``" msgstr "``PlicMapping.light``" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:34 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:34 msgid "" -"This mapping generates a lighter PLIC, at the cost of some missing optional " -"features:" +"This mapping generates a lighter PLIC, at the cost of some missing " +"optional features:" msgstr "此映射生成更轻量级的PLIC，但代价是缺少一些可选特性：" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:36 -msgid "no reading the intrerrupt's priority" +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:36 +#, fuzzy +msgid "not reading the interrupt's priority" msgstr "不读取中断优先级" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:37 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:37 +#, fuzzy msgid "" -"no reading the interrupts's pending bit (must use the claim/complete " +"not reading the interrupt's pending bit (must use the claim/complete " "mechanism)" msgstr "不读取中断的挂起位（必须使用声明(claim)/完成(complete)机制）" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:38 -msgid "no reading the target's threshold" +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:38 +#, fuzzy +msgid "not reading the target's threshold" msgstr "不读取目标的阈值" -#: ../../source/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:40 +#: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:40 msgid "The rest of the registers & logic is generated." msgstr "剩下的寄存器&逻辑会被生成." + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/service_plugin.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/service_plugin.po index 41632b7a2b0..a11b9146e46 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/service_plugin.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/service_plugin.po @@ -5,20 +5,19 @@ # msgid "" msgstr "" -"Project-Id-Version: SpinalHDL\n" +"Project-Id-Version: SpinalHDL\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-22 03:53+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-23 07:01+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" -"Content-Type: text/plain; charset=UTF-8\n" +"Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:5 msgid "Plugin" @@ -30,43 +29,39 @@ msgstr "简介" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:10 msgid "" -"For some design, instead of implementing your Component's hardware directly " -"in it, you may instead want to compose its hardware by using some sorts of " -"Plugins. This can provide a few key features :" -msgstr "对于某些设计，您可能希望通过使用某种插件来组合组件的硬件，而不是直接在组件中" -"实现硬件。这可以提供一些关键特性：" +"For some design, instead of implementing your Component's hardware " +"directly in it, you may instead want to compose its hardware by using " +"some sorts of Plugins. This can provide a few key features :" +msgstr "对于某些设计，您可能希望通过使用某种插件来组合组件的硬件，而不是直接在组件中实现硬件。这可以提供一些关键特性：" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:13 msgid "" -"You can extend the features of your component by adding new plugins in its " -"parameters. For instance adding Floating point support in a CPU." -msgstr "您可以通过在组件的参数中添加新的插件来扩展组件的功能。例如，在CPU中添加浮点支" -"持。" +"You can extend the features of your component by adding new plugins in " +"its parameters. For instance adding Floating point support in a CPU." +msgstr "您可以通过在组件的参数中添加新的插件来扩展组件的功能。例如，在CPU中添加浮点支持。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:14 msgid "" -"You can swap various implementations of the same functionality just by using " -"another set of plugins. For instance one implementation of a CPU multiplier " -"may fit well on some FPGA, while others may fit well on ASIC." -msgstr "" -"您可以通过使用另一组插件来轻松切换相同功能的各种实现。例如，某个CPU乘法器的实" -"现可能在某些FPGA上表现良好，而其他实现可能在ASIC上表现良好。" +"You can swap various implementations of the same functionality just by " +"using another set of plugins. For instance one implementation of a CPU " +"multiplier may fit well on some FPGA, while others may fit well on ASIC." +msgstr "您可以通过使用另一组插件来轻松切换相同功能的各种实现。例如，某个CPU乘法器的实现可能在某些FPGA上表现良好，而其他实现可能在ASIC上表现良好。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:15 +#, fuzzy msgid "" -"It avoid the very very very large hand written toplevel syndrom where " -"everything has to be connected manualy. Instead plugins can discover their " -"neighborhood by looking/using the software interface of other plugins." -msgstr "它避免了非常非常庞大的手写顶层结构，其中一切都必须手动连接的情况。相反，插件" -"可以通过查看/使用其他插件的软件接口来发现它们的关联关系。" +"It avoid the very very very large hand written toplevel syndrome where " +"everything has to be connected manually. Instead plugins can discover " +"their neighborhood by looking/using the software interface of other " +"plugins." +msgstr "它避免了非常非常庞大的手写顶层结构，其中一切都必须手动连接的情况。相反，插件可以通过查看/使用其他插件的软件接口来发现它们的关联关系。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:17 msgid "" -"VexRiscv and NaxRiscv projects are an example of this. Their are CPUs which " -"have a mostly empty toplevel, and their hardware parts are injected using " -"plugins. For instance :" -msgstr "VexRiscv和NaxRiscv项目就是这方面的例子。它们是具有大部分是空白的顶层的CPU，其" -"硬件部分通过插件注入。例如：" +"VexRiscv and NaxRiscv projects are an example of this. Their are CPUs " +"which have a mostly empty toplevel, and their hardware parts are injected" +" using plugins. For instance :" +msgstr "VexRiscv和NaxRiscv项目就是这方面的例子。它们是具有大部分是空白的顶层的CPU，其硬件部分通过插件注入。例如：" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:20 msgid "PcPlugin" @@ -93,21 +88,21 @@ msgid "..." msgstr "..." #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:27 +#, fuzzy msgid "" -"And those plugins will then negociate/propagate/interconnect to each others " -"via their pool of services." +"And those plugins will then negotiate/propagate/interconnect to each " +"others via their pool of services." msgstr "这些插件将通过他们的服务池进行协调/传递/互连。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:29 msgid "" "While VexRiscv use a strict synchronous 2 phase system (setup/build " -"callback), NaxRiscv uses a more flexible approach which uses the spinal.core." -"fiber API to fork elaboration threads which can interlock each others in " -"order to ensure a workable elaboration ordering." +"callback), NaxRiscv uses a more flexible approach which uses the " +"spinal.core.fiber API to fork elaboration threads which can interlock " +"each others in order to ensure a workable elaboration ordering." msgstr "" -"虽然VexRiscv使用严格的同步二阶段系统（设置(setup)/构建(build)回调(callback)）" -"，但NaxRiscv采用了一种更灵活的方法，使用spinal.core.fiber " -"API来分叉实例化线程，这些线程可以联锁，以确保可行的实例化顺序。" +"虽然VexRiscv使用严格的同步二阶段系统（设置(setup)/构建(build)回调(callback)），但NaxRiscv采用了一种更灵活的方法，使用spinal.core.fiber" +" API来分叉实例化线程，这些线程可以联锁，以确保可行的实例化顺序。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:31 msgid "" @@ -124,19 +119,21 @@ msgid "The main idea is that you have multiple 2 executions phases :" msgstr "主要思想是您有多个2执行环节：" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:38 +#, fuzzy msgid "" -"Setup phase, in which plugins can lock/retain each others. The idea is not " -"to start negociation / elaboration yet." +"Setup phase, in which plugins can lock/retain each others. The idea is " +"not to start negotiation / elaboration yet." msgstr "设置(Setup)环节，在此环节插件可以联锁/保留。其目的并非开始协调/实例化。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:39 -msgid "Build phase, in which plugins can negociation / elaboration hardware." +#, fuzzy +msgid "Build phase, in which plugins can negotiation / elaboration hardware." msgstr "构建(Build)环节，在此环节插件可以协调/实例化硬件。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:41 msgid "" -"The build phase will not start before all FiberPlugin are done with their " -"setup phase." +"The build phase will not start before all FiberPlugin are done with their" +" setup phase." msgstr "构建环节将不会在所有FiberPlugin完成其设置环节前启动。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:61 @@ -145,8 +142,8 @@ msgstr "简单示例" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:63 msgid "" -"Here is a simple dummy example with a SubComponent which will be composed " -"using 2 plugins :" +"Here is a simple dummy example with a SubComponent which will be composed" +" using 2 plugins :" msgstr "这是一个简单的虚设示例，其中包含一个将使用两个插件组合的SubComponent：" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:102 @@ -155,12 +152,10 @@ msgstr "该TopLevel会生成以下Verilog代码：" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:131 msgid "" -"Note each \"during build\" fork an elaboration thread, the DriverPlugin." -"logic thread execution will be blocked on the \"sp\" evaluation until the " -"StatePlugin.logic execution is done." -msgstr "" -"请注意，每次在“构建期间”分叉一个实例化线程时，DriverPlugin." -"logic线程的执行将在“sp”评估上被阻塞，直到StatePlugin.logic执行完成。" +"Note each \"during build\" fork an elaboration thread, the " +"DriverPlugin.logic thread execution will be blocked on the \"sp\" " +"evaluation until the StatePlugin.logic execution is done." +msgstr "请注意，每次在“构建期间”分叉一个实例化线程时，DriverPlugin.logic线程的执行将在“sp”评估上被阻塞，直到StatePlugin.logic执行完成。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:135 msgid "Interlocking / Ordering" @@ -169,23 +164,20 @@ msgstr "联锁/排序" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:137 msgid "" "Plugins can interlock each others using Retainer instances. Each plugin " -"instance has a built in lock which can be controlled using retain/release " -"functions." -msgstr "插件可以通过Retainer实例相互联锁。每个插件实例都有一个内置锁，可以通过retain/" -"release函数进行控制。" +"instance has a built in lock which can be controlled using retain/release" +" functions." +msgstr "插件可以通过Retainer实例相互联锁。每个插件实例都有一个内置锁，可以通过retain/release函数进行控制。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:140 msgid "" -"Here is an example based on the above `Simple example` but that time, the " -"DriverPlugin will increment the StatePlugin.logic.signal by an amount set by " -"other plugins (SetupPlugin in our case). And to ensure that the DriverPlugin " -"doesn't generate the hardware too early, the SetupPlugin uses the " -"DriverPlugin.retain/release functions." +"Here is an example based on the above `Simple example` but that time, the" +" DriverPlugin will increment the StatePlugin.logic.signal by an amount " +"set by other plugins (SetupPlugin in our case). And to ensure that the " +"DriverPlugin doesn't generate the hardware too early, the SetupPlugin " +"uses the DriverPlugin.retain/release functions." msgstr "" -"这是一个基于上面的 `简单示例` 的例子，但这次，DriverPlugin将通过由其他插件（" -"在我们的例子中是SetupPlugin）设置的数量对StatePlugin.logic." -"signal递增。为了确保DriverPlugin不会过早生成硬件，SetupPlugin使用DriverPlugin" -".retain/release函数。" +"这是一个基于上面的 `简单示例` " +"的例子，但这次，DriverPlugin将通过由其他插件（在我们的例子中是SetupPlugin）设置的数量对StatePlugin.logic.signal递增。为了确保DriverPlugin不会过早生成硬件，SetupPlugin使用DriverPlugin.retain/release函数。" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:207 msgid "Here is the generated verilog" @@ -193,12 +185,13 @@ msgstr "这是生成的verilog" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:236 msgid "" -"Clearly, those examples are overkilled for what they do, the idea in general " -"is more about :" +"Clearly, those examples are overkilled for what they do, the idea in " +"general is more about :" msgstr "显然，这些示例对于它们的功能来说有些过度，总体上的思路更多地是：" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:238 -msgid "Negociate / create interfaces between plugins (ex jump / flush ports)" +#, fuzzy +msgid "Negotiate / create interfaces between plugins (ex jump / flush ports)" msgstr "协调/创建插件之间的接口（例如跳转(jump)/刷新(flush)端口）" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:239 @@ -208,3 +201,4 @@ msgstr "安排实例化（例如解码/调度规范）" #: ../../SpinalHDL/Libraries/Misc/service_plugin.rst:240 msgid "Provide a distributed framework which can scale up (minimal hardcoding)" msgstr "提供一个可扩展的分布式框架（最小硬编码）" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po index 92a903358a9..2cd148e8aa2 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po @@ -5,20 +5,19 @@ # msgid "" msgstr "" -"Project-Id-Version: SpinalHDL\n" +"Project-Id-Version: SpinalHDL\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-02-20 09:54+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-03-01 05:00+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" -"Content-Type: text/plain; charset=UTF-8\n" +"Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.5-dev\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:3 msgid "Introduction" @@ -26,37 +25,32 @@ msgstr "简介" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:5 msgid "" -"spinal.lib.misc.pipeline provides a pipelining API. The main advantages over " -"manual pipelining are :" -msgstr "" -"spinal.lib.misc.pipeline提供了一套流水线API。相对于手动流水线它的主要优点是：" +"spinal.lib.misc.pipeline provides a pipelining API. The main advantages " +"over manual pipelining are :" +msgstr "spinal.lib.misc.pipeline提供了一套流水线API。相对于手动流水线它的主要优点是：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:7 msgid "" -"You don't have to predefine all the signal elements needed for the entire " -"staged system upfront. You can create and consume stagable signals in a more " -"ad hoc fashion as your design requires - without needing to refactor all the " -"intervening stages to know about the signal" -msgstr "" -"您不必预先准备好整个流水系统中所需的所有信号元素。您可以根据设计需要，以更特" -"别的方式创建和使用可分级的信号，而无需重构所有中间阶段来处理信号" +"You don't have to predefine all the signal elements needed for the entire" +" staged system upfront. You can create and consume stagable signals in a " +"more ad hoc fashion as your design requires - without needing to refactor" +" all the intervening stages to know about the signal" +msgstr "您不必预先准备好整个流水系统中所需的所有信号元素。您可以根据设计需要，以更特别的方式创建和使用可分级的信号，而无需重构所有中间阶段来处理信号" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:8 msgid "" "Signals of the pipeline can utilize the powerful parametrization " "capabilities of SpinalHDL and be subject to optimization/removal if a " -"specific design build does not require a particular parametrized feature, " -"without any need to modify the staging system design or project code base in " -"a significant way." -msgstr "" -"流水线的信号可以利用SpinalHDL的强大参数化能力，并且如果设计构建中不需要特定的" -"参数化特征，则可以进行优化/移除，而不需要以显著的方式修改流水系统设计或项目代" -"码库。" +"specific design build does not require a particular parametrized feature," +" without any need to modify the staging system design or project code " +"base in a significant way." +msgstr "流水线的信号可以利用SpinalHDL的强大参数化能力，并且如果设计构建中不需要特定的参数化特征，则可以进行优化/移除，而不需要以显著的方式修改流水系统设计或项目代码库。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:9 +#, fuzzy msgid "" -"Manual retiming is much easier, as you don't have to handle the registers / " -"arbitration manualy" +"Manual retiming is much easier, as you don't have to handle the registers" +" / arbitration manually" msgstr "手动时序调整要容易得多，因为您不必手动处理寄存器/仲裁器" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:10 @@ -76,8 +70,7 @@ msgid "Link : which allows to connect nodes to each other" msgstr "Link：允许节点相互连接" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:16 -msgid "" -"Builder : which will generate the hardware required for a whole pipeline" +msgid "Builder : which will generate the hardware required for a whole pipeline" msgstr "Builder：生成整个管道所需的硬件" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:17 @@ -89,13 +82,10 @@ msgstr "Payload：用于获取流水线的节点上的硬件信号" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:19 msgid "" "It is important to understand that Payload isn't a hardware data/signal " -"instance, but a key to retrieve a data/signal on nodes along the pipeline, " -"and that the pipeline builder will then automatically interconnect/pipeline " -"every occurrence of a given Payload between nodes." -msgstr "" -"重要的是，Payload不是硬件数据/信号实例，而是用于检索流水线在节点中数据/信号的" -"关键，并且流水线构建器随后将在节点之间的每次给定Payload出现时自动互连/流水" -"线。" +"instance, but a key to retrieve a data/signal on nodes along the " +"pipeline, and that the pipeline builder will then automatically " +"interconnect/pipeline every occurrence of a given Payload between nodes." +msgstr "重要的是，Payload不是硬件数据/信号实例，而是用于检索流水线在节点中数据/信号的关键，并且流水线构建器随后将在节点之间的每次给定Payload出现时自动互连/流水线。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:21 msgid "Here is an example to illustrate :" @@ -134,22 +124,20 @@ msgid "Payload" msgstr "Payload" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:150 +#, fuzzy msgid "" -"Payload objects are used to refer to data which can go through the pipeline. " -"Technicaly speaking, Payload is a HardType which has a name and is used as a " -"\"key\" to retrieve the signals in a certain pipeline stage." -msgstr "" -"Payload对象用于引用可以通过流水线的数据。从技术上讲，Payload是一个HardType，" -"它有一个名字，并被用作在流水线某个级中检索信号的“键”。" +"Payload objects are used to refer to data which can go through the " +"pipeline. Technically speaking, Payload is a HardType which has a name " +"and is used as a \"key\" to retrieve the signals in a certain pipeline " +"stage." +msgstr "Payload对象用于引用可以通过流水线的数据。从技术上讲，Payload是一个HardType，它有一个名字，并被用作在流水线某个级中检索信号的“键”。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:163 msgid "" -"Note that I got used to name the Payload instances using uppercase. This is " -"to make it very explicit that the thing isn't a hardware signal, but are " -"more like a \"key/type\" to access things." -msgstr "" -"请注意，我习惯于使用大写对Payload实例命名。这是为了让它非常明确，这不是一个硬" -"件信号，更像是一个“键/类型”访问的东西。" +"Note that I got used to name the Payload instances using uppercase. This " +"is to make it very explicit that the thing isn't a hardware signal, but " +"are more like a \"key/type\" to access things." +msgstr "请注意，我习惯于使用大写对Payload实例命名。这是为了让它非常明确，这不是一个硬件信号，更像是一个“键/类型”访问的东西。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:166 msgid "Node" @@ -198,26 +186,24 @@ msgstr "RW" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:182 msgid "" -"Is the signal which specifies if a transaction is present on the node. It is " -"driven by the upstream. Once asserted, it must only be de-asserted the cycle " -"after which either both valid and ready or node.cancel are high. valid must " -"not depend on ready." -msgstr "" -"指定节点上是否存在事务的信号。它是由上游逻辑驱动的。一旦置为1，则它必须且仅能" -"在valid和ready同时置位或node.cancel为高的周期后解除置位。valid不依赖于ready。" +"Is the signal which specifies if a transaction is present on the node. It" +" is driven by the upstream. Once asserted, it must only be de-asserted " +"the cycle after which either both valid and ready or node.cancel are " +"high. valid must not depend on ready." +msgstr "指定节点上是否存在事务的信号。它是由上游逻辑驱动的。一旦置为1，则它必须且仅能在valid和ready同时置位或node.cancel为高的周期后解除置位。valid不依赖于ready。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:183 msgid "node.ready" msgstr "node.ready" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:185 +#, fuzzy msgid "" "Is the signal which specifies if the node's transaction can proceed " -"downstream. It is driven by the downstream to create backpresure. The signal " -"has no meaning when there is no transaction (node.valid being deasserted)" -msgstr "" -"指定节点的事务是否可以向下游进行的信号。它是由下游驱动以创建反压。当没有事务" -"（node.valid被置0）时，该信号无意义" +"downstream. It is driven by the downstream to create backpressure. The " +"signal has no meaning when there is no transaction (node.valid being " +"deasserted)" +msgstr "指定节点的事务是否可以向下游进行的信号。它是由下游驱动以创建反压。当没有事务（node.valid被置0）时，该信号无意义" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:186 msgid "node.cancel" @@ -225,12 +211,10 @@ msgstr "node.cancel" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:188 msgid "" -"Is the signal which specifies if the node's transaction in being canceled " -"from the pipeline. It is driven by the downstream. The signal has no meaning " -"when there is no transaction (node.valid being deasserted)" -msgstr "" -"指定节点的事务是否正在从流水线中取消的信号。它由下游驱动。当没有事务时（node." -"valid被置0），该信号没有意义" +"Is the signal which specifies if the node's transaction in being canceled" +" from the pipeline. It is driven by the downstream. The signal has no " +"meaning when there is no transaction (node.valid being deasserted)" +msgstr "指定节点的事务是否正在从流水线中取消的信号。它由下游驱动。当没有事务时（node.valid被置0），该信号没有意义" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:189 msgid "node.isValid" @@ -270,12 +254,11 @@ msgid "node.isFiring" msgstr "node.isFiring" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:200 +#, fuzzy msgid "" -"True when the node transaction is successfuly moving futher (valid && ready " -"&& !cancel). Useful to commit state changes." -msgstr "" -"当节点事务成功继续进行时为True（valid && ready && !cancel）。用于提交状态更" -"改。" +"True when the node transaction is successfully moving further (valid && " +"ready && !cancel). Useful to commit state changes." +msgstr "当节点事务成功继续进行时为True（valid && ready && !cancel）。用于提交状态更改。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:201 msgid "node.isMoving" @@ -284,13 +267,12 @@ msgstr "node.isMoving" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:203 msgid "" "True when the node transaction will not be present anymore on the node " -"(starting from the next cycle), either because downstream is ready to take " -"the transaction, or because the transaction is canceled from the pipeline. " -"(valid && (ready || cancel)). Useful to \"reset\" states." +"(starting from the next cycle), either because downstream is ready to " +"take the transaction, or because the transaction is canceled from the " +"pipeline. (valid && (ready || cancel)). Useful to \"reset\" states." msgstr "" -"当节点事务将不再存在于节点上时（从下一周期开始）为True，要么是因为下游准备好" -"接收事务，要么是因为事务已从流水线中取消。（valid && (ready || cancel)）用" -"于“复位”(reset)状态。" +"当节点事务将不再存在于节点上时（从下一周期开始）为True，要么是因为下游准备好接收事务，要么是因为事务已从流水线中取消。（valid && " +"(ready || cancel)）用于“复位”(reset)状态。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:206 msgid "node.isCanceling" @@ -298,40 +280,33 @@ msgstr "node.isCanceling" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:208 msgid "" -"True when the node transaction is being canceled. Meaning that it will not " -"appear anywhere in the pipeline in future cycles." -msgstr "" -"当节点事务正在被取消时为True。这意味着在将来的周期中它不会出现在流水线中的任" -"何地方。" +"True when the node transaction is being canceled. Meaning that it will " +"not appear anywhere in the pipeline in future cycles." +msgstr "当节点事务正在被取消时为True。这意味着在将来的周期中它不会出现在流水线中的任何地方。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:210 msgid "" "Note that the node.valid/node.ready signals follows the same conventions " "than the :doc:`../stream`'s ones ." -msgstr "" -"请注意，node.valid/node.ready信号遵循与 :doc:`../stream` 中相同的规范。" +msgstr "请注意，node.valid/node.ready信号遵循与 :doc:`../stream` 中相同的规范。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:212 +#, fuzzy msgid "" "The Node controls (valid/ready/cancel) and status (isValid, isReady, " -"isCancel, isFiring, ...) signals are created on demande. So for instance you " -"can create pipeline with no backpresure by never refering to the ready " -"signal. That's why it is important to use status signals when you want to " -"read the status of something and only use control signals when you to drive " -"something." -msgstr "" -"Node的控制信号（valid/ready/cancel）和状态信号（isValid、isReady、isCancel、" -"isFiring等）是按需创建的。因此，例如，您可以通过永远不引用ready信号来创建没有" -"反压的流水线。这就是在想要读取某物的状态时使用状态信号，仅在想要驱动某物时使" -"用控制信号的重要性所在。" +"isCancel, isFiring, ...) signals are created on demand. So for instance " +"you can create pipeline with no backpressure by never referring to the " +"ready signal. That's why it is important to use status signals when you " +"want to read the status of something and only use control signals when " +"you to drive something." +msgstr "Node的控制信号（valid/ready/cancel）和状态信号（isValid、isReady、isCancel、isFiring等）是按需创建的。因此，例如，您可以通过永远不引用ready信号来创建没有反压的流水线。这就是在想要读取某物的状态时使用状态信号，仅在想要驱动某物时使用控制信号的重要性所在。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:215 msgid "" -"Here is a list of arbitration cases you can have on a node. valid/ready/" -"cancel define the state we are in, while isFiring/isMoving result of those :" -msgstr "" -"以下是节点上可能出现的仲裁情况列表。valid/ready/cancel定义了我们所处的状态，" -"而isFiring/isMoving是这些状态的结果：" +"Here is a list of arbitration cases you can have on a node. " +"valid/ready/cancel define the state we are in, while isFiring/isMoving " +"result of those :" +msgstr "以下是节点上可能出现的仲裁情况列表。valid/ready/cancel定义了我们所处的状态，而isFiring/isMoving是这些状态的结果：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:218 msgid "valid" @@ -389,12 +364,10 @@ msgstr "取消" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:230 msgid "" -"Note that if you want to model things like for instance a CPU stage which " -"can block and flush stuff, take a look a the CtrlLink, as it provides the " -"API to do such things." -msgstr "" -"请注意，如果您想要建模诸如CPU级可能的阻塞和刷新的情况，可以查看 CtrlLink，因" -"为它提供了执行此类操作的 API。" +"Note that if you want to model things like for instance a CPU stage which" +" can block and flush stuff, take a look a the CtrlLink, as it provides " +"the API to do such things." +msgstr "请注意，如果您想要建模诸如CPU级可能的阻塞和刷新的情况，可以查看 CtrlLink，因为它提供了执行此类操作的 API。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:232 msgid "You can access signals referenced by a Payload via:" @@ -414,13 +387,11 @@ msgstr "node(Payload, Any)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:243 msgid "" -"Same as above, but include a second argument which is used as a \"secondary " -"key\". This eases the construction of multi-lane hardware. For instance, " -"when you have a multi issue CPU pipeline, you can use the lane Int id as " -"secondary key" -msgstr "" -"与上述相同，但包括一个用作“次要键”的第二个参数。这有助于构建多通道硬件。例" -"如，当您有一个多发射CPU流水线时，您可以使用通道Int id作为次要键" +"Same as above, but include a second argument which is used as a " +"\"secondary key\". This eases the construction of multi-lane hardware. " +"For instance, when you have a multi issue CPU pipeline, you can use the " +"lane Int id as secondary key" +msgstr "与上述相同，但包括一个用作“次要键”的第二个参数。这有助于构建多通道硬件。例如，当您有一个多发射CPU流水线时，您可以使用通道Int id作为次要键" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:244 msgid "node.insert(Data)" @@ -428,17 +399,17 @@ msgstr "node.insert(Data)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:245 msgid "" -"Return a new Payload instance which is connected to the given Data hardware " -"signal" +"Return a new Payload instance which is connected to the given Data " +"hardware signal" msgstr "返回一个新的Payload实例，该实例连接到给定的Data硬件信号" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:261 +#, fuzzy msgid "" -"While you can manualy drive/read the arbitration/data of the first/last " -"stage of your pipeline, there is a few utilities to connect its boundaries." -msgstr "" -"虽然您可以手动驱动/读取流水线的第一个/最后一级的仲裁/数据，但有一些实用工具可" -"以连接其边界。" +"While you can manually drive/read the arbitration/data of the first/last " +"stage of your pipeline, there is a few utilities to connect its " +"boundaries." +msgstr "虽然您可以手动驱动/读取流水线的第一个/最后一级的仲裁/数据，但有一些实用工具可以连接其边界。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:270 msgid "node.arbitrateFrom(Stream[T]])" @@ -507,31 +478,28 @@ msgstr "node.driveTo(Flow[T]])((T, Node) => Unit)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:305 msgid "" -"In order to reduce verbosity, there is a set of implicit conversions between " -"Payload toward their data representation which can be used when you are in " -"the context of a Node :" -msgstr "" -"为了减少冗长，在Payload与其数据表示之间有一组隐式转换，可在Node下使用：" +"In order to reduce verbosity, there is a set of implicit conversions " +"between Payload toward their data representation which can be used when " +"you are in the context of a Node :" +msgstr "为了减少冗长，在Payload与其数据表示之间有一组隐式转换，可在Node下使用：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:314 msgid "You can also use those implicit conversions by importing them :" msgstr "您还可以通过导入它们来使用这些隐式转换：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:327 +#, fuzzy msgid "" -"There is also an API which alows you to create new Area which provide the " -"whole API of a given node instance (including implicit convertion) without " -"import :" -msgstr "" -"还有一个API，它允许你创建新的Area，这个Area提供了给定节点实例的全部API（包括" -"隐式转换），而无需导入：" +"There is also an API which allows you to create new Area which provide " +"the whole API of a given node instance (including implicit conversion) " +"without import :" +msgstr "还有一个API，它允许你创建新的Area，这个Area提供了给定节点实例的全部API（包括隐式转换），而无需导入：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:338 msgid "" -"Such feature is very useful when you have parametrizable pipeline locations " -"for your hardware (see retiming example)." -msgstr "" -"当硬件具有可参数化的流水线位置时，这样的功能非常有用（请参阅重定时示例）。" +"Such feature is very useful when you have parametrizable pipeline " +"locations for your hardware (see retiming example)." +msgstr "当硬件具有可参数化的流水线位置时，这样的功能非常有用（请参阅重定时示例）。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:342 msgid "Links" @@ -539,13 +507,13 @@ msgstr "Links" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:344 msgid "" -"There is few different Links already implemented (but you could also create " -"your own custom one). The idea of Links is to connect two nodes together in " -"various ways. They generally have a `up` Node and a `down` Node." +"There is few different Links already implemented (but you could also " +"create your own custom one). The idea of Links is to connect two nodes " +"together in various ways. They generally have a `up` Node and a `down` " +"Node." msgstr "" -"目前已经实现了一些不同的Links（但您也可以创建自己的自定义Links）。Links的思想" -"是以各种方式将两个节点连接在一起，它们通常有一个 `up` 节点和一个 `down` 节" -"点。" +"目前已经实现了一些不同的Links（但您也可以创建自己的自定义Links）。Links的思想是以各种方式将两个节点连接在一起，它们通常有一个 " +"`up` 节点和一个 `down` 节点。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:349 msgid "DirectLink" @@ -561,8 +529,8 @@ msgstr "StageLink" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:363 msgid "" -"This connect two nodes using registers on the data / valid signals and some " -"arbitration on the ready." +"This connect two nodes using registers on the data / valid signals and " +"some arbitration on the ready." msgstr "这使用data/valid信号上的寄存器和ready信号上的一些仲裁连接了两个节点。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:371 @@ -570,11 +538,11 @@ msgid "S2mLink" msgstr "S2mLink" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:373 +#, fuzzy msgid "" "This connect two nodes using registers on the ready signal, which can be " -"useful to improve backpresure combinatorial timings." -msgstr "" -"这使用ready信号上的寄存器连接两个节点，这对于改进反压组合时序非常有用。" +"useful to improve backpressure combinatorial timings." +msgstr "这使用ready信号上的寄存器连接两个节点，这对于改进反压组合时序非常有用。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:380 msgid "CtrlLink" @@ -583,11 +551,9 @@ msgstr "CtrlLink" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:382 msgid "" "This is kind of a special Link, as connect two nodes with optional flow " -"control / bypass logic. Its API should be flexible enough to implement a CPU " -"stage with it." -msgstr "" -"这是一种特殊的 Link，用于连接两个节点，具有可选的流量控制/旁路逻辑。它的应用" -"程序接口应该足够灵活，可以用它来实现 CPU 流水级。" +"control / bypass logic. Its API should be flexible enough to implement a " +"CPU stage with it." +msgstr "这是一种特殊的 Link，用于连接两个节点，具有可选的流量控制/旁路逻辑。它的应用程序接口应该足够灵活，可以用它来实现 CPU 流水级。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:384 msgid "Here is its flow control API (The Bool arguments enable the features) :" @@ -607,10 +573,9 @@ msgstr "throwWhen(Bool)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:395 msgid "" -"Allows to cancel the current transaction from the pipeline (clear down.valid " -"and make the transaction driver forget its current state)" -msgstr "" -"允许从流水线中取消当前事务（清除 down.valid，使事务驱动逻辑忘记其当前状态）" +"Allows to cancel the current transaction from the pipeline (clear " +"down.valid and make the transaction driver forget its current state)" +msgstr "允许从流水线中取消当前事务（清除 down.valid，使事务驱动逻辑忘记其当前状态）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:396 msgid "forgetOneWhen(Bool)" @@ -643,30 +608,27 @@ msgid "terminateWhen(Bool)" msgstr "terminateWhen(Bool)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:403 -msgid "" -"Allows to hide the current transaction from downstream (clear down.valid)" +msgid "Allows to hide the current transaction from downstream (clear down.valid)" msgstr "允许下游节点隐藏当前传输事务（清零 down.valid）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:405 msgid "" -"Also note that if you want to do flow control in a conditional scope (ex in " -"a when statement), you can call the following functions :" -msgstr "" -"还要注意的是，如果要在条件作用域（例如在 when 语句中）进行通信流控制，可以调" -"用以下函数 ：" +"Also note that if you want to do flow control in a conditional scope (ex " +"in a when statement), you can call the following functions :" +msgstr "还要注意的是，如果要在条件作用域（例如在 when 语句中）进行通信流控制，可以调用以下函数 ：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:407 msgid "" -"haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow(), " -"throwIt()" +"haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow()," +" throwIt()" msgstr "" -"haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow(), " -"throwIt()" +"haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow()," +" throwIt()" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:419 msgid "" -"You can retrieve which nodes are connected to the Link using node.up / node." -"down." +"You can retrieve which nodes are connected to the Link using node.up / " +"node.down." msgstr "您可以使用 node.up / node.down 查看哪些节点连接到了链接。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:421 @@ -702,17 +664,17 @@ msgid "link.bypass(Payload)" msgstr "link.bypass(Payload)" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:436 +#, fuzzy msgid "" -"Allows to conditionaly override a Payload value between link.up -> link." -"down. This can be used to fix data hazard in CPU pipelines for instance." -msgstr "" -"允许在 link.up -> link.down 之间有条件地覆盖 Payload 值。例如，这可用于修复 " -"CPU 流水线中的数据冲突。" +"Allows to conditionally override a Payload value between link.up -> " +"link.down. This can be used to fix data hazard in CPU pipelines for " +"instance." +msgstr "允许在 link.up -> link.down 之间有条件地覆盖 Payload 值。例如，这可用于修复 CPU 流水线中的数据冲突。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:455 msgid "" -"Note that if you create a CtrlLink without node arguments, it will create " -"its own nodes internally." +"Note that if you create a CtrlLink without node arguments, it will create" +" its own nodes internally." msgstr "请注意，如果创建的 CtrlLink 不带节点参数，它将在内部创建自己的节点。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:466 @@ -728,8 +690,7 @@ msgid "Your custom Link" msgstr "您的自定义链接" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:473 -msgid "" -"You can implement your custom links by implementing the Link base class." +msgid "You can implement your custom links by implementing the Link base class." msgstr "您可以通过实现 Link 基类来实现自定义链接。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:486 @@ -742,14 +703,15 @@ msgstr "Builder" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:491 msgid "" -"To generate the hardware of your pipeline, you need to give a list of all " -"the Links used in your pipeline." +"To generate the hardware of your pipeline, you need to give a list of all" +" the Links used in your pipeline." msgstr "要生成流水线硬件，您需要提供流水线中使用的所有链接列表。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:506 +#, fuzzy msgid "" -"There is also a set of \"all in one\" builders that you can instanciate to " -"help yourself." +"There is also a set of \"all in one\" builders that you can instantiate " +"to help yourself." msgstr "此外，还有一套 \"一体化 \"的构建工具，您可以利用它来帮助你自己。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:508 @@ -764,23 +726,22 @@ msgstr "组合能力（Composability）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:523 msgid "" -"One good thing about the API is that it easily allows to compose a pipeline " -"with multiple parallel things. What i mean by \"compose\" is that sometime " -"the pipeline you need to design has parallel processing to do." -msgstr "" -"该API的一个优点是，它可以轻松地将多个并行事物组成一个流水线。这里的 \"组成 " -"\"是指有时你设计的流水线需要进行并行处理。" +"One good thing about the API is that it easily allows to compose a " +"pipeline with multiple parallel things. What i mean by \"compose\" is " +"that sometime the pipeline you need to design has parallel processing to " +"do." +msgstr "该API的一个优点是，它可以轻松地将多个并行事物组成一个流水线。这里的 \"组成 \"是指有时你设计的流水线需要进行并行处理。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:525 msgid "" -"Imagine you need to do floating point multiplication on 4 pairs of numbers " -"(to later sum them). If those 4 pairs a provided at the same time by a " -"single stream of data, then you don't want 4 different pipelines to multiply " -"them, instead you want to process them all in parallel in the same pipeline." +"Imagine you need to do floating point multiplication on 4 pairs of " +"numbers (to later sum them). If those 4 pairs a provided at the same time" +" by a single stream of data, then you don't want 4 different pipelines to" +" multiply them, instead you want to process them all in parallel in the " +"same pipeline." msgstr "" -"试想一下，如果您需要对 4 对数字进行浮点乘法运算（稍后求和）。并且这 4 对数字" -"是由一个数据流同时提供的，那么就不需要 4 条不同的流水线来进行乘法运算，而需要" -"在同一条流水线上并行处理。" +"试想一下，如果您需要对 4 对数字进行浮点乘法运算（稍后求和）。并且这 4 对数字是由一个数据流同时提供的，那么就不需要 4 " +"条不同的流水线来进行乘法运算，而需要在同一条流水线上并行处理。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:527 msgid "" @@ -789,28 +750,27 @@ msgid "" msgstr "下面的示例展示了一种模式，它将多个通道组成一个流水线，来并行处理它们。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:571 +#, fuzzy msgid "" "This will produce the following data path (assuming lanesCount = 2), " -"abitration not being shown :" +"arbitration not being shown :" msgstr "这将产生以下数据路径（假设 lanesCount = 2），仲裁器没有显示：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:578 -msgid "Retiming / Variable lenth" +#, fuzzy +msgid "Retiming / Variable length" msgstr "重定时/可变长度" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:580 msgid "" -"Sometime you want to design a pipeline, but you don't really know where the " -"critical paths will be and what the right balance between stages is. And " -"often you can't rely on the synthesis tool doing a good job with automatic " -"retiming." -msgstr "" -"有时，你想设计一个流水线，但你并不真正知道关键路径在哪里，也不知道各阶段之间" -"如何平衡。而且通常情况下，你无法依赖综合工具做好自动重定时工作。" +"Sometime you want to design a pipeline, but you don't really know where " +"the critical paths will be and what the right balance between stages is. " +"And often you can't rely on the synthesis tool doing a good job with " +"automatic retiming." +msgstr "有时，你想设计一个流水线，但你并不真正知道关键路径在哪里，也不知道各阶段之间如何平衡。而且通常情况下，你无法依赖综合工具做好自动重定时工作。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:582 -msgid "" -"So, you kind of need a easy way to move the logic of your pipeline around." +msgid "So, you kind of need a easy way to move the logic of your pipeline around." msgstr "因此，你需要一种简单的方法来构建流水线逻辑。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:584 @@ -835,12 +795,11 @@ msgstr "请注意，生成的硬件 verilog 还算干净（至少按我的标准 #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:779 msgid "" -"Also, you can easily tweak how many stages and where you want the processing " -"to be done, for instance you may want to move the inversion hardware in the " -"same stage as the adder. This can be done the following way :" -msgstr "" -"此外，您还可以轻松调整处理的级数和位置，例如，您可能希望将翻转的硬件逻辑移到" -"与加法器相同级上。具体方法如下：" +"Also, you can easily tweak how many stages and where you want the " +"processing to be done, for instance you may want to move the inversion " +"hardware in the same stage as the adder. This can be done the following " +"way :" +msgstr "此外，您还可以轻松调整处理的级数和位置，例如，您可能希望将翻转的硬件逻辑移到与加法器相同级上。具体方法如下：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:793 msgid "Then you may want to remove the output register stage :" @@ -848,17 +807,18 @@ msgstr "那么您可能需要移除输出寄存器级：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:807 msgid "" -"One thing about this example is the necessity intermediate val as `addNode`. " -"I mean :" +"One thing about this example is the necessity intermediate val as " +"`addNode`. I mean :" msgstr "这个示例的一个特点是，中间值必须是 `addNode`。例如：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:817 +#, fuzzy msgid "" -"Unfortunatly, scala doesn't allow to replace `new addNode.Area` with `new " -"nodes(addAt).Area`. One workaround is to define a class as :" +"Unfortunately, scala doesn't allow to replace `new addNode.Area` with " +"`new nodes(addAt).Area`. One workaround is to define a class as :" msgstr "" -"遗憾的是，scala 不允许用 `new nodes(addAt).Area` 替换 `new addNode." -"Area`。一种变通方法是将其定义为一个类，比如：" +"遗憾的是，scala 不允许用 `new nodes(addAt).Area` 替换 `new " +"addNode.Area`。一种变通方法是将其定义为一个类，比如：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:827 msgid "Depending the scale of your pipeline, it can payoff." @@ -886,6 +846,7 @@ msgstr "add / jump / led /delay 指令" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:907 msgid "" -"Here is a simple testbench which implement a loop which will make the led " -"counting up." +"Here is a simple testbench which implement a loop which will make the led" +" counting up." msgstr "下面是一个简单的测试平台，它实现了一个循环，使 led 计数值上升。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po index 65aa3f17e34..93a2bf7df10 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/fiber.rst:7 msgid "Fiber framework" @@ -26,50 +29,49 @@ msgstr "纤程框架" #: ../../SpinalHDL/Libraries/fiber.rst:10 msgid "" "This framework is not expected to be used for general RTL generation and " -"targets large system design management and code generation. It is currently " -"used as toplevel integration tool in SaxonSoC." -msgstr "该框架设计目标不是用于一般 RTL 生成，而是针对大型系统设计管理和代码生成。" -"它目前在 SaxonSoC 中用作顶级集成工具。" +"targets large system design management and code generation. It is " +"currently used as toplevel integration tool in SaxonSoC." +msgstr "该框架设计目标不是用于一般 RTL 生成，而是针对大型系统设计管理和代码生成。它目前在 SaxonSoC 中用作顶级集成工具。" #: ../../SpinalHDL/Libraries/fiber.rst:13 -msgid "Currently in developpement." +#, fuzzy +msgid "Currently in development." msgstr "目前正在开发中。" #: ../../SpinalHDL/Libraries/fiber.rst:15 msgid "" -"The Fiber to run the hardware elaboration in a out of order manner, a bit " -"similarly to Makefile, where you can define rules and dependencies which " -"will then be solved when you run a make command. It is very similar to the " -"Scala Future feature." +"The Fiber to run the hardware elaboration in a out of order manner, a bit" +" similarly to Makefile, where you can define rules and dependencies which" +" will then be solved when you run a make command. It is very similar to " +"the Scala Future feature." msgstr "" -"纤程(Fiber)以乱序的方式运行硬件生成，有点类似于Makefile，您可以在其中定义规则" -"和依赖关系，然后在运行make命令时解决这些依赖关系。这与Scala " -"Future功能非常相似。" +"纤程(Fiber)以乱序的方式运行硬件生成，有点类似于Makefile，您可以在其中定义规则和依赖关系，然后在运行make命令时解决这些依赖关系。这与Scala" +" Future功能非常相似。" #: ../../SpinalHDL/Libraries/fiber.rst:17 msgid "" -"Using this framework can complicate simple things but provide some strong " -"features for complex cases :" +"Using this framework can complicate simple things but provide some strong" +" features for complex cases :" msgstr "使用这个框架可能会使简单的事情复杂化，但为复杂的情况提供了一些强大的功能：" #: ../../SpinalHDL/Libraries/fiber.rst:19 msgid "" "You can define things before even knowing all their requirements, ex : " -"instantiating a interruption controller, before knowing how many interrupt " -"signal lines you need" -msgstr "您甚至可以在知道所有要求之前就定义事物，例如：在知道需要多少中断信号线之前实" -"例化中断控制器" +"instantiating a interruption controller, before knowing how many " +"interrupt signal lines you need" +msgstr "您甚至可以在知道所有要求之前就定义事物，例如：在知道需要多少中断信号线之前实例化中断控制器" #: ../../SpinalHDL/Libraries/fiber.rst:21 +#, fuzzy msgid "" -"Abstract/lazy/partial SoC architecture definition allowing the creation of " -"SoC template for further specialisations" +"Abstract/lazy/partial SoC architecture definition allowing the creation " +"of SoC template for further specializations" msgstr "抽象/懒惰化/部分化SoC架构定义，允许创建SoC模板以供进一步专门化" #: ../../SpinalHDL/Libraries/fiber.rst:22 msgid "" -"Automatic requirement negotiation between multiple agents in a decentralized" -" way, ex : between masters and slaves of a memory bus" +"Automatic requirement negotiation between multiple agents in a " +"decentralized way, ex : between masters and slaves of a memory bus" msgstr "以分散方式在多个代理之间自动进行需求协商，例如：内存总线的主设备和从设备之间" #: ../../SpinalHDL/Libraries/fiber.rst:24 @@ -82,22 +84,21 @@ msgstr "``Handle[T]``，稍后可用于存储 ``T`` 类型的值。" #: ../../SpinalHDL/Libraries/fiber.rst:27 msgid "" -"``handle.load`` which allow to set the value of a handle (will reschedule " -"all tasks waiting on it)" +"``handle.load`` which allow to set the value of a handle (will reschedule" +" all tasks waiting on it)" msgstr "``handle.load`` 允许设置句柄的值（将启动等待它的所有任务）" #: ../../SpinalHDL/Libraries/fiber.rst:28 msgid "" -"``handle.get``, which return the value of the given handle. Will block the " -"task execution if that handle isn't loaded yet" +"``handle.get``, which return the value of the given handle. Will block " +"the task execution if that handle isn't loaded yet" msgstr "``handle.get``，返回给定句柄的值。如果尚未加载该句柄，将阻止任务执行进入等待" #: ../../SpinalHDL/Libraries/fiber.rst:29 msgid "" -"``Handle{ /*code*/ }``, which fork a new task which will execute the given " -"code. The result of that code will be loaded into the Handle" -msgstr "``Handle{ /*code*/ " -"}``，它派生一个新任务来执行给定的代码。该代码的结果将被加载到句柄中" +"``Handle{ /*code*/ }``, which fork a new task which will execute the " +"given code. The result of that code will be loaded into the Handle" +msgstr "``Handle{ /*code*/ }``，它派生一个新任务来执行给定的代码。该代码的结果将被加载到句柄中" #: ../../SpinalHDL/Libraries/fiber.rst:30 msgid "" @@ -131,7 +132,8 @@ msgstr "创建打印任务分支，但在执行calculator.get时被阻塞" #: ../../SpinalHDL/Libraries/fiber.rst:64 msgid "" -"load a and b, which reschedule the calculator task (as it was waiting on a)" +"load a and b, which reschedule the calculator task (as it was waiting on " +"a)" msgstr "加载a和b，这会重新调度计算器任务（因为它正在等待 a）" #: ../../SpinalHDL/Libraries/fiber.rst:65 @@ -150,11 +152,10 @@ msgstr "完成所有任务" #: ../../SpinalHDL/Libraries/fiber.rst:70 msgid "" -"So, the main point of that example is to show that we kind of overcome the " -"sequential execution of things, as a and b are loaded after the definition " -"of the calculator." -msgstr "因此，该示例的要点是表明我们在某种程度上克服了顺序执行，因为a和b可以在计算器" -"定义之后被加载。" +"So, the main point of that example is to show that we kind of overcome " +"the sequential execution of things, as a and b are loaded after the " +"definition of the calculator." +msgstr "因此，该示例的要点是表明我们在某种程度上克服了顺序执行，因为a和b可以在计算器定义之后被加载。" #: ../../SpinalHDL/Libraries/fiber.rst:74 msgid "Handle[T]" @@ -164,8 +165,7 @@ msgstr "Handle[T]" msgid "" "Handle[T] are a bit like scala's Future[T], they allow to talk about " "something before it is even existing, and wait on it." -msgstr "Handle[T]有点像scala的Future[T]，它们允许在某个对象存在之前就谈及它，并等待它" -"。" +msgstr "Handle[T]有点像scala的Future[T]，它们允许在某个对象存在之前就谈及它，并等待它。" #: ../../SpinalHDL/Libraries/fiber.rst:87 msgid "soon(handle)" @@ -174,9 +174,8 @@ msgstr "soon(handle)" #: ../../SpinalHDL/Libraries/fiber.rst:89 msgid "" "In order to maintain a proper graph of dependencies between tasks and " -"Handle, a task can specify in advance that it will load a given handle. This" -" is very usefull in case of a generation starvation/deadlock for SpinalHDL " -"to report accuratly where is the issue." -msgstr "" -"为了维护任务和句柄之间正确的依赖关系图，任务可以预先指明它将加载给定的句柄。" -"在生成饥饿(starvation)/死锁的情况下非常有用，以便SpinalHDL准确报告问题所在。" +"Handle, a task can specify in advance that it will load a given handle. " +"This is very usefull in case of a generation starvation/deadlock for " +"SpinalHDL to report accuratly where is the issue." +msgstr "为了维护任务和句柄之间正确的依赖关系图，任务可以预先指明它将加载给定的句柄。在生成饥饿(starvation)/死锁的情况下非常有用，以便SpinalHDL准确报告问题所在。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po index c414f03628c..416a4718a98 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po @@ -1,26 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"POT-Creation-Date: 2024-03-30 15:02+0000\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-03-31 12:30+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.5-dev\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/flow.rst:3 msgid "Flow" @@ -132,7 +132,8 @@ msgid "x.m2sPipe()" msgstr "x.m2sPipe()" #: ../../SpinalHDL/Libraries/flow.rst -msgid "Return a Flow drived by x" +#, fuzzy +msgid "Return a Flow driven by x" msgstr "返回一个由 x 驱动的流" #: ../../SpinalHDL/Libraries/flow.rst @@ -355,3 +356,4 @@ msgstr "通常用于比较参考/dut数据" #~ msgid "Assign a new valid payload to the Flow. ``valid`` is set to ``True``." #~ msgstr "为数据流分配一个新的有效负载。 ``valid`` 设置为 ``True`` 。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po index 8a51630e0a1..2d943aaac06 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fsm.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-10 17:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/fsm.rst:7 msgid "State machine" @@ -30,11 +33,9 @@ msgstr "简介" #: ../../SpinalHDL/Libraries/fsm.rst:12 msgid "" "In SpinalHDL you can define your state machine like in VHDL/Verilog, by " -"using enumerations and switch/case statements. But in SpinalHDL you can also" -" use a dedicated syntax." -msgstr "" -"在SpinalHDL中，您可以像在VHDL/Verilog中一样，通过使用枚举和switch/" -"case语句来定义状态机。但在SpinalHDL中，您还可以使用专门的语句。" +"using enumerations and switch/case statements. But in SpinalHDL you can " +"also use a dedicated syntax." +msgstr "在SpinalHDL中，您可以像在VHDL/Verilog中一样，通过使用枚举和switch/case语句来定义状态机。但在SpinalHDL中，您还可以使用专门的语句。" #: ../../SpinalHDL/Libraries/fsm.rst:14 msgid "The state machine below is implemented in the following examples:" @@ -98,8 +99,8 @@ msgstr "入口点" #: ../../SpinalHDL/Libraries/fsm.rst:121 msgid "" -"A state can be defined as the entry point of the state machine by extending " -"the EntryPoint trait:" +"A state can be defined as the entry point of the state machine by " +"extending the EntryPoint trait:" msgstr "通过扩展EntryPoint特征，可以将状态定义为状态机的入口点：" #: ../../SpinalHDL/Libraries/fsm.rst:127 @@ -114,15 +115,13 @@ msgstr "转换" msgid "" "Transitions are represented by ``goto(nextState)``, which schedules the " "state machine to be in ``nextState`` the next cycle." -msgstr "转换由 ``goto(nextState)`` 表示，它使状态机的状态在下一个周期转换到 " -"``nextState`` 。" +msgstr "转换由 ``goto(nextState)`` 表示，它使状态机的状态在下一个周期转换到 ``nextState`` 。" #: ../../SpinalHDL/Libraries/fsm.rst:138 msgid "" "``exit()`` schedules the state machine to be in the boot state the next " "cycle (or, in ``StateFsm``, to exit the current nested state machine)." -msgstr "``exit()`` 使状态机在下一个周期处于启动(boot)状态（或者，在 ``StateFsm`` " -"中，退出当前的嵌套状态机）。" +msgstr "``exit()`` 使状态机在下一个周期处于启动(boot)状态（或者，在 ``StateFsm`` 中，退出当前的嵌套状态机）。" #: ../../SpinalHDL/Libraries/fsm.rst:140 msgid "" @@ -130,25 +129,25 @@ msgid "" "using ``always { yourStatements }``, which always applies " "``yourStatements``, with a priority over states." msgstr "" -"这两个函数可以在状态定义中使用（见下文），或使用 ``always { yourStatements " -"}`` ，这将始终应用 ``yourStatements``，并且优先级高于状态。" +"这两个函数可以在状态定义中使用（见下文），或使用 ``always { yourStatements }`` ，这将始终应用 " +"``yourStatements``，并且优先级高于状态。" #: ../../SpinalHDL/Libraries/fsm.rst:144 msgid "State encoding" msgstr "状态编码" #: ../../SpinalHDL/Libraries/fsm.rst:146 +#, fuzzy msgid "" -"By default the FSM state vector will be encoded using the native encoding of" -" the language/tools the RTL is generated for (Verilog or VHDL). This default" -" can be overriden by using the ``setEncoding(...)`` method which either " -"takes a ``SpinalEnumEncoding`` or varargs of type ``(State, BigInt)`` for a " -"custom encoding." +"By default the FSM state vector will be encoded using the native encoding" +" of the language/tools the RTL is generated for (Verilog or VHDL). This " +"default can be overridden by using the ``setEncoding(...)`` method which " +"either takes a ``SpinalEnumEncoding`` or varargs of type ``(State, " +"BigInt)`` for a custom encoding." msgstr "" -"默认情况下，FSM状态向量将使用（针对Verilog或VHDL）生成RTL的语言/工具的本地编" -"码进行编码。可以通过使用 ``setEncoding(...)`` 函数覆盖此默认设置，该方法接收 " -"``SpinalEnumEncoding`` 或类型为 ``(State, BigInt)`` " -"的可变参数以进行自定义编码。" +"默认情况下，FSM状态向量将使用（针对Verilog或VHDL）生成RTL的语言/工具的本地编码进行编码。可以通过使用 " +"``setEncoding(...)`` 函数覆盖此默认设置，该方法接收 ``SpinalEnumEncoding`` 或类型为 " +"``(State, BigInt)`` 的可变参数以进行自定义编码。" #: ../../SpinalHDL/Libraries/fsm.rst:150 msgid "Using a ``SpinalEnumEncoding``" @@ -160,14 +159,14 @@ msgstr "使用自定义编码" #: ../../SpinalHDL/Libraries/fsm.rst:169 msgid "" -"When using the ``graySequential`` enum encoding, no check is done to verify " -"that the FSM transitions only produce single-bit changes in the state " -"vector. The encoding is done according to the order of state definitions and" -" the designer must ensure that only valid transitions are done if needed." +"When using the ``graySequential`` enum encoding, no check is done to " +"verify that the FSM transitions only produce single-bit changes in the " +"state vector. The encoding is done according to the order of state " +"definitions and the designer must ensure that only valid transitions are " +"done if needed." msgstr "" -"当使用 ``graySequential`` 枚举编码时，不会进行任何检查以验证FSM转换是否只在状" -"态向量中产生单比特的变化。编码是根据状态定义的顺序完成的，设计者必须确保仅在" -"需要时进行有效的转换。" +"当使用 ``graySequential`` " +"枚举编码时，不会进行任何检查以验证FSM转换是否只在状态向量中产生单比特的变化。编码是根据状态定义的顺序完成的，设计者必须确保仅在需要时进行有效的转换。" #: ../../SpinalHDL/Libraries/fsm.rst:174 msgid "States" @@ -195,23 +194,21 @@ msgstr "``StateParallelFsm``" #: ../../SpinalHDL/Libraries/fsm.rst:183 msgid "" -"Each of them provides the following functions to define the logic associated" -" to them:" +"Each of them provides the following functions to define the logic " +"associated to them:" msgstr "它们每个都提供了以下函数来定义与之相关的逻辑：" #: ../../SpinalHDL/Libraries/fsm.rst:196 msgid "" -"``yourStatements`` is applied when the state machine is not in ``state`` and" -" will be in ``state`` the next cycle" -msgstr "当状态机不在 ``state`` 状态，并且在下一个周期将处于 ``state`` 状态时，执行 " -"``yourStatements``" +"``yourStatements`` is applied when the state machine is not in ``state`` " +"and will be in ``state`` the next cycle" +msgstr "当状态机不在 ``state`` 状态，并且在下一个周期将处于 ``state`` 状态时，执行 ``yourStatements``" #: ../../SpinalHDL/Libraries/fsm.rst:202 msgid "" "``yourStatements`` is applied when the state machine is in ``state`` and " "will be in another state the next cycle" -msgstr "当状态机在 ``state`` 状态时执行 ``yourStatements`` " -"，并且在下一个周期将处于另一个状态" +msgstr "当状态机在 ``state`` 状态时执行 ``yourStatements`` ，并且在下一个周期将处于另一个状态" #: ../../SpinalHDL/Libraries/fsm.rst:208 msgid "``yourStatements`` is applied when the state machine is in ``state``" @@ -219,10 +216,9 @@ msgstr "当状态机在 ``state`` 状态时执行 ``yourStatements``" #: ../../SpinalHDL/Libraries/fsm.rst:214 msgid "" -"``yourStatements`` is executed when the state machine will be in ``state`` " -"the next cycle (even if it is already in it)" -msgstr "当状态机在下一个周期处于 ``state`` 状态时， ``yourStatements`` " -"被执行（即使它已经处于该状态）" +"``yourStatements`` is executed when the state machine will be in " +"``state`` the next cycle (even if it is already in it)" +msgstr "当状态机在下一个周期处于 ``state`` 状态时， ``yourStatements`` 被执行（即使它已经处于该状态）" #: ../../SpinalHDL/Libraries/fsm.rst:216 msgid "``state.`` is implicit in a ``new State`` block:" @@ -234,9 +230,9 @@ msgstr "StateDelay（状态延迟）" #: ../../SpinalHDL/Libraries/fsm.rst:238 msgid "" -"``StateDelay`` allows you to create a state which waits for a fixed number " -"of cycles before executing statements in ``whenCompleted {...}``. The " -"preferred way to use it is:" +"``StateDelay`` allows you to create a state which waits for a fixed " +"number of cycles before executing statements in ``whenCompleted {...}``. " +"The preferred way to use it is:" msgstr "" "``StateDelay`` 允许您创建一个状态，该状态在执行 ``whenCompleted {...}`` " "中的语句之前等待固定数量的周期。首选的使用方式是：" @@ -255,8 +251,8 @@ msgid "" "machine. When the nested state machine is done (exited), statements in " "``whenCompleted { ... }`` are executed." msgstr "" -"``StateFsm`` 允许您描述一个包含嵌套状态机的状态。当嵌套状态机完成（退出）时，" -"执行 ``whenCompleted { ... }`` 中的语句。" +"``StateFsm`` 允许您描述一个包含嵌套状态机的状态。当嵌套状态机完成（退出）时，执行 ``whenCompleted { ... }``" +" 中的语句。" #: ../../SpinalHDL/Libraries/fsm.rst:259 msgid "There is an example of StateFsm definition :" @@ -264,11 +260,10 @@ msgstr "这是一个StateFsm定义的示例：" #: ../../SpinalHDL/Libraries/fsm.rst:290 msgid "" -"In the example above, ``exit()`` makes the state machine jump to the boot " -"state (a internal hidden state). This notifies ``StateFsm`` about the " +"In the example above, ``exit()`` makes the state machine jump to the boot" +" state (a internal hidden state). This notifies ``StateFsm`` about the " "completion of the inner state machine." -msgstr "在上面的示例中， ``exit()`` 使状态机跳转到启动状态（内部隐藏状态）。这将通知 " -"``StateFsm`` 其内部状态机已经完成。" +msgstr "在上面的示例中， ``exit()`` 使状态机跳转到启动状态（内部隐藏状态）。这将通知 ``StateFsm`` 其内部状态机已经完成。" #: ../../SpinalHDL/Libraries/fsm.rst:293 msgid "StateParallelFsm" @@ -276,12 +271,12 @@ msgstr "StateParallelFsm" #: ../../SpinalHDL/Libraries/fsm.rst:295 msgid "" -"``StateParallelFsm`` allows you to handle multiple nested state machines. " -"When all nested state machine are done, statements in ``whenCompleted { ... " -"}`` are executed." +"``StateParallelFsm`` allows you to handle multiple nested state machines." +" When all nested state machine are done, statements in ``whenCompleted { " +"... }`` are executed." msgstr "" -"``StateParallelFsm`` 允许您处理多个嵌套状态机。当所有嵌套状态机完成时，执行 " -"``whenCompleted { ... }`` 中的语句。" +"``StateParallelFsm`` 允许您处理多个嵌套状态机。当所有嵌套状态机完成时，执行 ``whenCompleted { ... " +"}`` 中的语句。" #: ../../SpinalHDL/Libraries/fsm.rst:297 ../../SpinalHDL/Libraries/fsm.rst:322 msgid "Example:" @@ -293,35 +288,35 @@ msgstr "关于入口状态的注释" #: ../../SpinalHDL/Libraries/fsm.rst:310 msgid "" -"The way the entry state has been defined above makes it so that between the " -"reset and the first clock sampling, the state machine is in a boot state. It" -" is only after the first clock sampling that the defined entry state becomes" -" active. This allows to properly enter the entry state (applying statements " -"in ``onEntry``), and allows nested state machines." +"The way the entry state has been defined above makes it so that between " +"the reset and the first clock sampling, the state machine is in a boot " +"state. It is only after the first clock sampling that the defined entry " +"state becomes active. This allows to properly enter the entry state " +"(applying statements in ``onEntry``), and allows nested state machines." msgstr "" -"上面定义入口状态的方式使得在复位和第一次时钟采样之间，状态机处于启动状态。只" -"有在第一次时钟采样之后，定义的入口状态才会变为活动状态。这保证了能正确进入入" -"口状态（在 ``onEntry`` 中应用语句），并支持嵌套状态机。" +"上面定义入口状态的方式使得在复位和第一次时钟采样之间，状态机处于启动状态。只有在第一次时钟采样之后，定义的入口状态才会变为活动状态。这保证了能正确进入入口状态（在" +" ``onEntry`` 中应用语句），并支持嵌套状态机。" #: ../../SpinalHDL/Libraries/fsm.rst:312 +#, fuzzy msgid "" -"While it is usefull, it is also possible to bypass that feature and directly" -" having a state machine booting into a user state." +"While it is useful, it is also possible to bypass that feature and " +"directly having a state machine booting into a user state." msgstr "虽然它很有用，但也可以绕过该功能并直接让状态机启动到用户状态。" #: ../../SpinalHDL/Libraries/fsm.rst:314 msgid "" -"To do so, use `makeInstantEntry()` instead of defining a ``new State``. This" -" function returns the boot state, active directly after reset." -msgstr "为此，请使用 `makeInstantEntry()` 而不是定义 ``new State`` " -"。该函数返回启动状态，复位后直接激活。" +"To do so, use `makeInstantEntry()` instead of defining a ``new State``. " +"This function returns the boot state, active directly after reset." +msgstr "为此，请使用 `makeInstantEntry()` 而不是定义 ``new State`` 。该函数返回启动状态，复位后直接激活。" #: ../../SpinalHDL/Libraries/fsm.rst:317 msgid "" -"The ``onEntry`` of that state will only be called when it transitions from " -"another state to this state and not during boot." +"The ``onEntry`` of that state will only be called when it transitions " +"from another state to this state and not during boot." msgstr "该状态的 ``onEntry`` 仅在从另一个状态转换到该状态时调用，而不是在启动期间。" #: ../../SpinalHDL/Libraries/fsm.rst:320 msgid "During simulation, the boot state is always named ``BOOT``." msgstr "在仿真过程中，启动状态始终命名为 ``BOOT`` 。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po index 363bb4f0910..4afb32de000 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-20 16:13+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.3\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/index.rst:5 msgid "Libraries" @@ -50,21 +53,20 @@ msgid "Provide some example to get the spirit of spinal" msgstr "提供一些例子以理解spinal的精髓" #: ../../SpinalHDL/Libraries/index.rst:14 -msgid "" -"Provide some tools and facilities (latency analyser, QSys converter, ...)" +#, fuzzy +msgid "Provide some tools and facilities (latency analyzer, QSys converter, ...)" msgstr "提供一些工具和功能（延迟分析器、QSys转换器……）" #: ../../SpinalHDL/Libraries/index.rst:16 msgid "" -"To use features introduced in followings chapter you need, in most of cases," -" to ``import spinal.lib._`` in your sources." -msgstr "要使用以下章节中介绍的特性，在大多数情况下，您需要使用 ``import spinal.lib." -"_`` 在您的代码中。" +"To use features introduced in followings chapter you need, in most of " +"cases, to ``import spinal.lib._`` in your sources." +msgstr "要使用以下章节中介绍的特性，在大多数情况下，您需要使用 ``import spinal.lib._`` 在您的代码中。" #: ../../SpinalHDL/Libraries/index.rst msgid "" -"This package is currently under construction. Documented features could be " -"considered as stable." +"This package is currently under construction. Documented features could " +"be considered as stable." msgstr "该包目前正在建设中。文档中的特性可以被认为是稳定的。" #: ../../SpinalHDL/Libraries/index.rst @@ -73,3 +75,4 @@ msgstr "请不要犹豫，使用GitHub提供建议/错误/修复/增强等意见 #~ msgid "Introduction" #~ msgstr "介绍" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po index 7216165e261..fbd6d88b065 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po @@ -1,26 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"POT-Creation-Date: 2024-02-26 12:25+0000\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-03-12 16:01+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.5-dev\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/regIf.rst:3 msgid "RegIf" @@ -54,7 +54,8 @@ msgid "Automatic address allocation" msgstr "自动地址分配" #: ../../SpinalHDL/Libraries/regIf.rst:39 -msgid "Automatic fileds allocation" +#, fuzzy +msgid "Automatic filed allocation" msgstr "自动字段分配" #: ../../SpinalHDL/Libraries/regIf.rst:54 @@ -543,7 +544,8 @@ msgid "example1: clock gate software enable" msgstr "示例1：时钟门软件使能" #: ../../SpinalHDL/Libraries/regIf.rst:262 -msgid "example2: interrupt raw reg with foce interface for software" +#, fuzzy +msgid "example2: interrupt raw reg with force interface for software" msgstr "示例2：使用软件的带强制(force)接口的中断原始(raw)状态寄存器" #: ../../SpinalHDL/Libraries/regIf.rst:272 @@ -626,7 +628,8 @@ msgstr "MASK" #: ../../SpinalHDL/Libraries/regIf.rst:414 #: ../../SpinalHDL/Libraries/regIf.rst:433 -msgid "int mask register, 1: off; 0: open; defualt 1 int off" +#, fuzzy +msgid "int mask register, 1: off; 0: open; default 1 int off" msgstr "中断掩码寄存器，1：关闭；0：打开；默认1 中断关闭" #: ../../SpinalHDL/Libraries/regIf.rst:415 @@ -721,7 +724,8 @@ msgstr "" "triggers: Bool*)``" #: ../../SpinalHDL/Libraries/regIf.rst:457 -msgid "creat RAW/FORCE/MASK(SET/CLR)/STATUS for pulse event at addrOffset" +#, fuzzy +msgid "create RAW/FORCE/MASK(SET/CLR)/STATUS for pulse event at addrOffset" msgstr "在addrOffset处为脉冲事件创建RAW/FORCE/MASK(SET/CLR)/STATUS" #: ../../SpinalHDL/Libraries/regIf.rst:458 @@ -729,11 +733,12 @@ msgid "" "``interruptLevel_W1SCmask_FactoryAt(addrOffset: BigInt, regNamePre: " "String, levels: Bool*)``" msgstr "" -"``interruptLevel_W1SCmask_FactoryAt(addrOffset: BigInt, regNamePre: String, " -"levels: Bool*)``" +"``interruptLevel_W1SCmask_FactoryAt(addrOffset: BigInt, regNamePre: " +"String, levels: Bool*)``" #: ../../SpinalHDL/Libraries/regIf.rst:458 -msgid "creat RAW/FORCE/MASK(SET/CLR)/STATUS for leveel event at addrOffset" +#, fuzzy +msgid "create RAW/FORCE/MASK(SET/CLR)/STATUS for level event at addrOffset" msgstr "在addrOffset处为电平事件创建RAW/FORCE/MASK(SET/CLR)/STATUS" #: ../../SpinalHDL/Libraries/regIf.rst:462 @@ -756,7 +761,8 @@ msgid "Developers Area" msgstr "开发者区域" #: ../../SpinalHDL/Libraries/regIf.rst:516 -msgid "You can add your document Type by extending the `BusIfVistor` Trait" +#, fuzzy +msgid "You can add your document Type by extending the `BusIfVisitor` Trait" msgstr "您可以通过扩展 `BusIfVistor` 特征来添加文档类型" #: ../../SpinalHDL/Libraries/regIf.rst:518 @@ -764,8 +770,10 @@ msgid "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``" msgstr "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``" #: ../../SpinalHDL/Libraries/regIf.rst:520 -msgid "BusIfVistor give access BusIf.RegInsts to do what you want" +#, fuzzy +msgid "BusIfVisitor give access BusIf.RegInsts to do what you want" msgstr "BusIfVistor给予访问BusIf.RegInsts的权限来执行您想要的操作" #~ msgid "Interrupt Design Spec" #~ msgstr "中断设计规范" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po index 748d9bea98b..f568ec72ea6 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po @@ -1,26 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"POT-Creation-Date: 2024-06-14 13:17+0000\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-06-15 00:17+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.6-dev\n" -"Generated-By: Babel 2.15.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/stream.rst:7 msgid "Stream" @@ -160,9 +160,10 @@ msgid "When manually reading/driving the signals of a Stream keep in mind that:" msgstr "当手动读取/驱动反压流的信号时，请记住：" #: ../../SpinalHDL/Libraries/stream.rst:82 +#, fuzzy msgid "" "After being asserted, ``valid`` may only be deasserted once the current " -"payload was acknowleged. This means ``valid`` can only toggle to 0 the " +"payload was acknowledged. This means ``valid`` can only toggle to 0 the " "cycle after a the slave did a read by asserting ``ready``." msgstr "" "当 ``valid`` 被置为有效后，它只有在当前负载被使用后才能被置为无效。这意味着 ``valid`` 只能在从端通过置高 ``ready``" @@ -278,7 +279,8 @@ msgid "x.stage()" msgstr "x.stage()" #: ../../SpinalHDL/Libraries/stream.rst -msgid "Return a Stream drived by x" +#, fuzzy +msgid "Return a Stream driven by x" msgstr "返回由x驱动的Stream反压流" #: ../../SpinalHDL/Libraries/stream.rst @@ -713,7 +715,8 @@ msgid "sequentialOrder" msgstr "sequentialOrder" #: ../../SpinalHDL/Libraries/stream.rst -msgid "Could be used to retrieve transaction in a sequancial order" +#, fuzzy +msgid "Could be used to retrieve transaction in a sequential order" msgstr "可用于按顺序遍历任务" #: ../../SpinalHDL/Libraries/stream.rst @@ -919,7 +922,8 @@ msgid "" msgstr "Testbench中主端通过调用函数来应用值（如果可用）以驱动值。如果值可用，则函数必须返回。支持随机的延迟。" #: ../../SpinalHDL/Libraries/stream.rst:599 -msgid "StreamReadyRandmizer" +#, fuzzy +msgid "StreamReadyRandomizer" msgstr "StreamReadyRandmizer" #: ../../SpinalHDL/Libraries/stream.rst:600 @@ -940,3 +944,4 @@ msgstr "通常用于比较参考/dut数据" #~ " preserving the `valid` and `ready` " #~ "signals" #~ msgstr "修改 `x` 流的有效载荷为 `drive` 函数返回值，同时保留 `valid` 和 `ready` 信号" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po index 3b7867cca6f..c73579967e5 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po @@ -1,26 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"POT-Creation-Date: 2024-04-19 10:29+0000\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-04-26 06:37+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.5.1-dev\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Libraries/utils.rst:5 msgid "Utils" @@ -328,6 +328,7 @@ msgid "The Counter tool can be used to easily instantiate a hardware counter." msgstr "计数器工具可用于轻松实例化硬件计数器。" #: ../../SpinalHDL/Libraries/utils.rst:123 +#: ../../SpinalHDL/Libraries/utils.rst:166 msgid "Instantiation syntax" msgstr "实例化语法" @@ -392,10 +393,6 @@ msgstr "超时" msgid "The Timeout tool can be used to easily instantiate an hardware timeout." msgstr "超时工具可用于方便地实例化一个硬件超时。" -#: ../../SpinalHDL/Libraries/utils.rst:166 -msgid "Instanciation syntax" -msgstr "实例化语法" - #: ../../SpinalHDL/Libraries/utils.rst:168 msgid "Timeout(cycles : BigInt)" msgstr "Timeout(cycles : BigInt)" @@ -445,14 +442,15 @@ msgid "asyncAssertSyncDeassert" msgstr "asyncAssertSyncDeassert" #: ../../SpinalHDL/Libraries/utils.rst:196 +#, fuzzy msgid "" "You can filter an asynchronous reset by using an asynchronously asserted " -"synchronously deaserted logic. To do it you can use the " +"synchronously deasserted logic. To do it you can use the " "``ResetCtrl.asyncAssertSyncDeassert`` function which will return you the " "filtered value." msgstr "" -"您可以使用“异步有效同步无效”的逻辑来构造异步复位。为此，可以使用 ``ResetCtrl." -"asyncAssertSyncDeassert`` 函数返回构造的复位信号。" +"您可以使用“异步有效同步无效”的逻辑来构造异步复位。为此，可以使用 ``ResetCtrl.asyncAssertSyncDeassert`` " +"函数返回构造的复位信号。" #: ../../SpinalHDL/Libraries/utils.rst:202 msgid "Argument name" @@ -522,8 +520,8 @@ msgid "" "tool which directly assign the ``clockDomain`` reset with the filtered " "value." msgstr "" -"另外还有一个 ``ResetCtrl.asyncAssertSyncDeassertDrive`` 版本的工具，" -"它直接使用新构造的复位信号作为 ``clockDomain`` 这个时钟域的复位。" +"另外还有一个 ``ResetCtrl.asyncAssertSyncDeassertDrive`` 版本的工具，它直接使用新构造的复位信号作为 " +"``clockDomain`` 这个时钟域的复位。" #: ../../SpinalHDL/Libraries/utils.rst:225 msgid "Special utilities" @@ -548,3 +546,7 @@ msgstr "从第一个节点到最后一个节点" #~ msgid "List[T]" #~ msgstr "List[T]" + +#~ msgid "Instanciation syntax" +#~ msgstr "实例化语法" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po index dfaecca144e..835b31b9478 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-18 07:38+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.3\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Other features/scope_property.rst:4 language msgid "ScopeProperty" @@ -25,23 +28,23 @@ msgstr "ScopeProperty" #: ../../SpinalHDL/Other features/scope_property.rst:6 language msgid "" -"A scope property is a thing which can store values locally to the current " -"thread. Its API can be used to set/get that value, but also to apply " -"modification to the value for a portion of the execution in a stack manner." -msgstr "范围属性是可以在当前线程本地存储值的东西。它的 API " -"可用于设置/获取该值，还可以以堆栈方式对部分值进行修改。" +"A scope property is a thing which can store values locally to the current" +" thread. Its API can be used to set/get that value, but also to apply " +"modification to the value for a portion of the execution in a stack " +"manner." +msgstr "范围属性是可以在当前线程本地存储值的东西。它的 API 可用于设置/获取该值，还可以以堆栈方式对部分值进行修改。" #: ../../SpinalHDL/Other features/scope_property.rst:8 language msgid "" "In other words it is a alternative to global variable, scala implicit, " "ThreadLocal." -msgstr "换句话说，它是全局变量、scala 隐式变量、线程本地变量（ThreadLocal） " -"的替代品。" +msgstr "换句话说，它是全局变量、scala 隐式变量、线程本地变量（ThreadLocal） 的替代品。" #: ../../SpinalHDL/Other features/scope_property.rst:10 language +#, fuzzy msgid "" -"To compare with global variable, It allow to run multiple thread running the" -" same code indepedently" +"To compare with global variable, It allow to run multiple thread running " +"the same code independently" msgstr "与全局变量相比，它允许运行多个线程独立运行相同的代码" #: ../../SpinalHDL/Other features/scope_property.rst:11 language @@ -50,7 +53,7 @@ msgstr "与 scala 隐式变量相比，它与代码库的耦合较小" #: ../../SpinalHDL/Other features/scope_property.rst:12 language msgid "" -"To compare with ThreadLocal, it has some API to collect all ScopeProperty " -"and restore them in the same state later on" -msgstr "与线程本地变量（ThreadLocal） 相比，它有一些 API " -"可以收集所有范围属性并稍后将它们恢复到相同状态" +"To compare with ThreadLocal, it has some API to collect all ScopeProperty" +" and restore them in the same state later on" +msgstr "与线程本地变量（ThreadLocal） 相比，它有一些 API 可以收集所有范围属性并稍后将它们恢复到相同状态" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po index 022c5f37b5c..7068b19fe18 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-03 17:03+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.3-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Other features/stub.rst:3 language msgid "Stub" @@ -48,9 +51,11 @@ msgid "then remove all children component" msgstr "然后删除所有子组件" #: ../../SpinalHDL/Other features/stub.rst:53 language -msgid "then remove all assignment and logic we dont want" +#, fuzzy +msgid "then remove all assignment and logic we don't want" msgstr "然后删除我们不需要的所有赋值和逻辑" #: ../../SpinalHDL/Other features/stub.rst:54 language msgid "tile 0 to output port" msgstr "给输出端口赋值0" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po index 90b9e177ab1..3117d12ecb5 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-18 09:29+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.3\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Semantic/assignments.rst:2 msgid "Assignments" @@ -53,8 +56,7 @@ msgid "" "Equivalent to ``:=`` in VHDL and ``=`` in Verilog. The value is updated " "instantly in-place. Only works with combinational signals, does not work " "with registers." -msgstr "相当于 VHDL 中的 ``:=`` 和 Verilog 中的 " -"``=``。该值会立即就地更新。仅适用于组合信号，不适用于寄存器。" +msgstr "相当于 VHDL 中的 ``:=`` 和 Verilog 中的 ``=``。该值会立即就地更新。仅适用于组合信号，不适用于寄存器。" #: ../../SpinalHDL/Semantic/assignments.rst:16 msgid "``<>``" @@ -63,51 +65,48 @@ msgstr "``<>``" #: ../../SpinalHDL/Semantic/assignments.rst:17 msgid "" "Automatic connection between 2 signals or two bundles of the same type. " -"Direction is inferred by using signal direction (in/out). (Similar behavior " -"to ``:=``\\ )" -msgstr "2 个信号或相同类型的两个信号线束之间的自动连接。通过使用信号定义（输入/输出）" -"来推断方向。 （与 ``:=``\\ 类似的行为）" +"Direction is inferred by using signal direction (in/out). (Similar " +"behavior to ``:=``\\ )" +msgstr "2 个信号或相同类型的两个信号线束之间的自动连接。通过使用信号定义（输入/输出）来推断方向。 （与 ``:=``\\ 类似的行为）" #: ../../SpinalHDL/Semantic/assignments.rst:19 +#, fuzzy msgid "" -"When muxing (for instance using ``when``, see :doc:`when_switch`.), the last" -" valid standard assignment ``:=`` wins. Else, assigning twice to the same " -"assignee from the same scope results in an assignment overlap. SpinalHDL " -"will assume this is a unintentional design error by default and halt " -"elaboration with error. For special use-cases assignment overlap can be " -"programatically permitted on a case by case basis. (see :doc:`../Design " -"errors/assignment_overlap`)." +"When muxing (for instance using ``when``, see :doc:`when_switch`.), the " +"last valid standard assignment ``:=`` wins. Else, assigning twice to the " +"same assignee from the same scope results in an assignment overlap. " +"SpinalHDL will assume this is a unintentional design error by default and" +" halt elaboration with error. For special use-cases assignment overlap " +"can be programmatically permitted on a case by case basis. (see " +":doc:`../Design errors/assignment_overlap`)." msgstr "" -"当多路复用时（例如使用 ``when``，请参阅 :doc:`when_switch`。），" -"最后一个有效的赋值 ``:=`` " -"为准。否则，向同一范围内的同一信号赋值两次会导致重叠错误。 SpinalHDL 默认情况" -"下会假设这是一个无意的设计错误，并因错误而停止实例细化。对于特殊用例，可以根" -"据具体情况以编程方式允许重叠赋值。 （参见 :doc:`../Design errors/" -"assignment_overlap`）。" +"当多路复用时（例如使用 ``when``，请参阅 :doc:`when_switch`。），最后一个有效的赋值 ``:=`` " +"为准。否则，向同一范围内的同一信号赋值两次会导致重叠错误。 SpinalHDL " +"默认情况下会假设这是一个无意的设计错误，并因错误而停止实例细化。对于特殊用例，可以根据具体情况以编程方式允许重叠赋值。 （参见 " +":doc:`../Design errors/assignment_overlap`）。" #: ../../SpinalHDL/Semantic/assignments.rst:45 msgid "" -"It also supports Bundle assignment (convert all bit signals into a single " -"bit-bus of suitable width of type Bits, to then use that wider form in an " -"assignment expression). Bundle multiple signals together using ``()`` " -"(Scala Tuple syntax) on both the left hand side and right hand side of an " -"assignment expression." +"It also supports Bundle assignment (convert all bit signals into a single" +" bit-bus of suitable width of type Bits, to then use that wider form in " +"an assignment expression). Bundle multiple signals together using ``()``" +" (Scala Tuple syntax) on both the left hand side and right hand side of " +"an assignment expression." msgstr "" -"它还支持线束赋值（将所有位信号转换为适当位宽的 `Bits` " -"类型的单位总线，然后在赋值表达式中使用更宽的形式）。" -"在赋值表达式的左侧和右侧使用 ``()`` （Scala 元组语法）将多个信号捆绑在一起。" +"它还支持线束赋值（将所有位信号转换为适当位宽的 `Bits` 类型的单位总线，然后在赋值表达式中使用更宽的形式）。在赋值表达式的左侧和右侧使用 " +"``()`` （Scala 元组语法）将多个信号捆绑在一起。" #: ../../SpinalHDL/Semantic/assignments.rst:62 msgid "" "It is important to understand that in SpinalHDL, the nature of a signal " -"(combinational/sequential) is defined in its declaration, not by the way it " -"is assigned. All datatype instances will define a combinational signal, " -"while a datatype instance wrapped with ``Reg(...)`` will define a sequential" -" (registered) signal." +"(combinational/sequential) is defined in its declaration, not by the way " +"it is assigned. All datatype instances will define a combinational " +"signal, while a datatype instance wrapped with ``Reg(...)`` will define a" +" sequential (registered) signal." msgstr "" -"重要的是要理解，在 SpinalHDL 中，信号的性质（组合/时序）是在其声明中定义的，" -"而不是通过赋值的方式定义的。所有数据类型实例都将定义一个组合信号，而用 " -"``Reg(...)`` 包装的实例将定义为一个时序信号（寄存器）。" +"重要的是要理解，在 SpinalHDL " +"中，信号的性质（组合/时序）是在其声明中定义的，而不是通过赋值的方式定义的。所有数据类型实例都将定义一个组合信号，而用 ``Reg(...)`` " +"包装的实例将定义为一个时序信号（寄存器）。" #: ../../SpinalHDL/Semantic/assignments.rst:73 msgid "Width checking" @@ -115,12 +114,12 @@ msgstr "位宽检查" #: ../../SpinalHDL/Semantic/assignments.rst:75 msgid "" -"SpinalHDL checks that the bit count of the left side and the right side of " -"an assignment matches. There are multiple ways to adapt the width of a given" -" BitVector (``Bits``, ``UInt``, ``SInt``):" +"SpinalHDL checks that the bit count of the left side and the right side " +"of an assignment matches. There are multiple ways to adapt the width of a" +" given BitVector (``Bits``, ``UInt``, ``SInt``):" msgstr "" -"SpinalHDL 检查赋值左侧和右侧的位数是否匹配。有多种方法可以改变给定 BitVector " -"（``Bits``, ``UInt``, ``SInt``）的位宽：" +"SpinalHDL 检查赋值左侧和右侧的位数是否匹配。有多种方法可以改变给定 BitVector （``Bits``, ``UInt``, " +"``SInt``）的位宽：" #: ../../SpinalHDL/Semantic/assignments.rst:81 msgid "Resizing techniques" @@ -148,35 +147,33 @@ msgstr "x := y.resizeLeft(newWidth)" #: ../../SpinalHDL/Semantic/assignments.rst:88 msgid "" -"Assign x with a resized copy of y :code:`newWidth` bits wide. Pads at the " -"LSB if needed." +"Assign x with a resized copy of y :code:`newWidth` bits wide. Pads at the" +" LSB if needed." msgstr "对 x 赋值 y 变为 newWidth 位宽后的副本。如果需要，可在 LSB 处进行填充。" #: ../../SpinalHDL/Semantic/assignments.rst:91 msgid "" "All resize methods may cause the resulting width to be wider or narrower " -"than the original width of :code:`y`. When widening occurs the extra bits " -"are padded with zeros." -msgstr "所有改变位宽方法都可能导致生成的位宽比 y " -"的原始位宽更宽或更窄。当发生加宽时，额外的位将用零填充。" +"than the original width of :code:`y`. When widening occurs the extra bits" +" are padded with zeros." +msgstr "所有改变位宽方法都可能导致生成的位宽比 y 的原始位宽更宽或更窄。当发生加宽时，额外的位将用零填充。" #: ../../SpinalHDL/Semantic/assignments.rst:95 msgid "" -"The inferred conversion with ``x.resized`` is based on the target width on " -"the left hand side of the assignment expression being resolved and obeys the" -" same semantics as ``y.resize(someWidth)``. The expression ``x := " -"y.resized`` is equivalent to ``x := y.resize(x.getBitsWidth bits)``." +"The inferred conversion with ``x.resized`` is based on the target width " +"on the left hand side of the assignment expression being resolved and " +"obeys the same semantics as ``y.resize(someWidth)``. The expression ``x " +":= y.resized`` is equivalent to ``x := y.resize(x.getBitsWidth bits)``." msgstr "" -"``x.resized`` 根据赋值表达式左侧的目标位宽推断转换方法，并遵循与 ``y." -"resize(someWidth)`` 相同的语义。表达式 ``x := y.resized`` 相当于 ``x := y." -"resize(x.getBitsWidth bits)``。" +"``x.resized`` 根据赋值表达式左侧的目标位宽推断转换方法，并遵循与 ``y.resize(someWidth)`` 相同的语义。表达式" +" ``x := y.resized`` 相当于 ``x := y.resize(x.getBitsWidth bits)``。" #: ../../SpinalHDL/Semantic/assignments.rst:99 msgid "" -"While the example code snippets show the use of an assignment statement, the" -" resize family of methods can be chained like any ordinary Scala method." -msgstr "虽然示例代码片段显示了赋值语句的使用方法，但 resize 系列方法可以像任何普通 " -"Scala 方法一样进行级联。" +"While the example code snippets show the use of an assignment statement, " +"the resize family of methods can be chained like any ordinary Scala " +"method." +msgstr "虽然示例代码片段显示了赋值语句的使用方法，但 resize 系列方法可以像任何普通 Scala 方法一样进行级联。" #: ../../SpinalHDL/Semantic/assignments.rst:102 msgid "There is one case where Spinal automatically resizes a value:" @@ -184,18 +181,16 @@ msgstr "在一种情况下，Spinal 会自动调整位宽的大小：" #: ../../SpinalHDL/Semantic/assignments.rst:109 msgid "" -"Because ``U(3)`` is a \"weak\" bit count inferred signal, SpinalHDL widens " -"it automatically. This can be considered to be functionally equivalent to " -"``U(3, 2 bits).resized`` However rest reassured SpinalHDL will do the " -"correct thing and continue to flag an error if the scenario would require " -"narrowing. An error is reported if the literal required 9 bits (e.g. " -"``U(0x100)``) when trying to assign into ``myUIntOf_8bits``." +"Because ``U(3)`` is a \"weak\" bit count inferred signal, SpinalHDL " +"widens it automatically. This can be considered to be functionally " +"equivalent to ``U(3, 2 bits).resized`` However rest reassured SpinalHDL " +"will do the correct thing and continue to flag an error if the scenario " +"would require narrowing. An error is reported if the literal required 9 " +"bits (e.g. ``U(0x100)``) when trying to assign into ``myUIntOf_8bits``." msgstr "" -"因为 ``U(3)`` 是一个“弱”位计数推断信号，SpinalHDL 会自动加宽它。" -"这可以被认为在功能上等同于 ``U(3, 2 bits).resized`` " -"，但是请放心，如果场景需要缩小范围，SpinalHDL 将做正确的事情并报告错误。" -"当尝试赋值 ``myUIntOf_8bits``时，如果字面量需要 9 位（例如 " -"``U(0x100)``），则会报告错误。" +"因为 ``U(3)`` 是一个“弱”位计数推断信号，SpinalHDL 会自动加宽它。这可以被认为在功能上等同于 ``U(3, 2 " +"bits).resized`` ，但是请放心，如果场景需要缩小范围，SpinalHDL 将做正确的事情并报告错误。当尝试赋值 " +"``myUIntOf_8bits``时，如果字面量需要 9 位（例如 ``U(0x100)``），则会报告错误。" #: ../../SpinalHDL/Semantic/assignments.rst:117 msgid "Combinatorial loops" @@ -204,11 +199,9 @@ msgstr "组合逻辑环(Combinatorial loops)" #: ../../SpinalHDL/Semantic/assignments.rst:119 msgid "" "SpinalHDL checks that there are no combinatorial loops (latches) in your " -"design. If one is detected, it raises an error and SpinalHDL will print the " -"path of the loop." -msgstr "SpinalHDL " -"检查您的设计中是否存在组合逻辑环（锁存器）。如果检测到，会引发错误，并且 " -"SpinalHDL 将打印造成循环的路径。" +"design. If one is detected, it raises an error and SpinalHDL will print " +"the path of the loop." +msgstr "SpinalHDL 检查您的设计中是否存在组合逻辑环（锁存器）。如果检测到，会引发错误，并且 SpinalHDL 将打印造成循环的路径。" #: ../../SpinalHDL/Semantic/assignments.rst:123 msgid "CombInit" @@ -217,38 +210,38 @@ msgstr "CombInit" #: ../../SpinalHDL/Semantic/assignments.rst:125 msgid "" "``CombInit`` can be used to copy a signal and its current combinatorial " -"assignments. The main use-case is to be able to overwrite the copied later, " -"without impacting the original signal." -msgstr "``CombInit`` 可用于复制信号及其当前的组合逻辑赋值。主要用例是能够稍后覆盖复制" -"后信号，而不影响原始信号。" +"assignments. The main use-case is to be able to overwrite the copied " +"later, without impacting the original signal." +msgstr "``CombInit`` 可用于复制信号及其当前的组合逻辑赋值。主要用例是能够稍后覆盖复制后信号，而不影响原始信号。" #: ../../SpinalHDL/Semantic/assignments.rst:149 msgid "" "If we look at the resulting Verilog, ``b`` is not present. Since it is a " -"copy of ``a`` by reference, these variables designate the same Verilog wire." -msgstr "" -"如果我们查看生成的 Verilog，会发现``b`` 不存在。由于它是引用的 ``a`` 的副本，" -"因此这些变量指代相同的 Verilog 信号。" +"copy of ``a`` by reference, these variables designate the same Verilog " +"wire." +msgstr "如果我们查看生成的 Verilog，会发现``b`` 不存在。由于它是引用的 ``a`` 的副本，因此这些变量指代相同的 Verilog 信号。" #: ../../SpinalHDL/Semantic/assignments.rst:168 msgid "" -"``CombInit`` is particularly helpful in helper functions to ensure that the " -"returned value is not referencing an input." +"``CombInit`` is particularly helpful in helper functions to ensure that " +"the returned value is not referencing an input." msgstr "``CombInit`` 在辅助函数中特别有用，可确保返回值不引用输入。" #: ../../SpinalHDL/Semantic/assignments.rst:181 +#, fuzzy msgid "" -"Without ``CombInit``, if ``c`` == false (but not if ``c`` == true), ``a1`` " -"and ``a2`` reference the same signal and the zero assignment is also applied" -" to ``a1``. With ``CombInit`` we have a coherent behaviour whatever the " -"``c`` value." +"Without ``CombInit``, if ``c`` == false (but not if ``c`` == true), " +"``a1`` and ``a2`` reference the same signal and the zero assignment is " +"also applied to ``a1``. With ``CombInit`` we have a coherent behavior " +"whatever the ``c`` value." msgstr "" -"没有 ``CombInit`` 的话，如果 ``c`` == false（而不是 ``c`` == true），``a1`` " -"和 ``a2`` 会引用相同的信号，并且 ``a1`` 被赋值为零。有了 ``CombInit`` ，无论 " -"``c`` 的值是多少，我们都有一致的行为（CombInit创建新的信号）。" +"没有 ``CombInit`` 的话，如果 ``c`` == false（而不是 ``c`` == true），``a1`` 和 ``a2`` " +"会引用相同的信号，并且 ``a1`` 被赋值为零。有了 ``CombInit`` ，无论 ``c`` " +"的值是多少，我们都有一致的行为（CombInit创建新的信号）。" #~ msgid "" -#~ "It also supports Bundle assignment. Bundle multiple signals together using " +#~ "It also supports Bundle assignment. " +#~ "Bundle multiple signals together using " #~ "``()`` to assign and assign to" #~ msgstr "它还支持 Bundle 分配。使用“()”将多个信号捆绑在一起进行分配和分配" @@ -265,10 +258,14 @@ msgstr "" #~ msgstr "myUIntOf_8bit := U(3)" #~ msgid "" -#~ "U(3) creates an UInt of 2 bits, which doesn't match the left side (8 bits)" +#~ "U(3) creates an UInt of 2 bits," +#~ " which doesn't match the left side" +#~ " (8 bits)" #~ msgstr "U(3) 创建一个 2 位的 UInt，与左侧（8 位）不匹配" #~ msgid "" -#~ "Because U(3) is a \"weak\" bit count inferred signal, SpinalHDL resizes it " -#~ "automatically" +#~ "Because U(3) is a \"weak\" bit " +#~ "count inferred signal, SpinalHDL resizes " +#~ "it automatically" #~ msgstr "由于 U(3) 是“弱”位计数推断信号，SpinalHDL 会自动调整其大小" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po index 2d9bfb69693..b480f9c5ace 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-12 04:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Semantic/rules.rst:2 msgid "Rules" @@ -26,10 +29,9 @@ msgstr "规则" #: ../../SpinalHDL/Semantic/rules.rst:4 msgid "" "The semantics behind SpinalHDL are important to learn, so that you " -"understand what is really happening behind the scenes, and how to control " -"it." -msgstr "SpinalHDL " -"背后的语义很重要，这样您就可以了解幕后真正发生的事情以及如何控制它。" +"understand what is really happening behind the scenes, and how to control" +" it." +msgstr "SpinalHDL 背后的语义很重要，这样您就可以了解幕后真正发生的事情以及如何控制它。" #: ../../SpinalHDL/Semantic/rules.rst:6 msgid "These semantics are defined by multiple rules:" @@ -37,20 +39,20 @@ msgstr "这些语义由多个规则定义：" #: ../../SpinalHDL/Semantic/rules.rst:8 msgid "" -"Signals and registers are operating concurrently with each other (parallel " -"behavioral, as in VHDL and Verilog)" +"Signals and registers are operating concurrently with each other " +"(parallel behavioral, as in VHDL and Verilog)" msgstr "信号和寄存器彼此同时运行（并行行为，如 VHDL 和 Verilog）" #: ../../SpinalHDL/Semantic/rules.rst:9 msgid "" -"An assignment to a combinational signal is like expressing a rule which is " -"always true" +"An assignment to a combinational signal is like expressing a rule which " +"is always true" msgstr "对组合信号的赋值就像表达一条始终为真的规则" #: ../../SpinalHDL/Semantic/rules.rst:10 msgid "" -"An assignment to a register is like expressing a rule which is applied on " -"each cycle of its clock domain" +"An assignment to a register is like expressing a rule which is applied on" +" each cycle of its clock domain" msgstr "对寄存器的赋值就像表达一条应用于其时钟域的每个周期的规则" #: ../../SpinalHDL/Semantic/rules.rst:11 @@ -63,8 +65,8 @@ msgid "" "elaboration in a `OOP `_ manner" msgstr "" -"每个信号和寄存器都可以作为对象在硬件实例细化期间进行操作，用 `OOP `_ 的思想" +"每个信号和寄存器都可以作为对象在硬件实例细化期间进行操作，用 `OOP `_ 的思想" #: ../../SpinalHDL/Semantic/rules.rst:15 msgid "Concurrency" @@ -72,8 +74,8 @@ msgstr "并发" #: ../../SpinalHDL/Semantic/rules.rst:17 msgid "" -"The order in which you assign each combinational or registered signal has no" -" behavioral impact." +"The order in which you assign each combinational or registered signal has" +" no behavioral impact." msgstr "您对每个组合或时序信号的赋值顺序不会对行为产生影响。" #: ../../SpinalHDL/Semantic/rules.rst:19 @@ -88,8 +90,7 @@ msgstr "这相当于：" msgid "" "More generally, when you use the ``:=`` assignment operator, it's like " "specifying an additional new rule for the left side signal/register." -msgstr "更一般地说，当您使用 ``:=`` " -"赋值运算符时，就像为左侧信号/寄存器指定一个附加的新规则。" +msgstr "更一般地说，当您使用 ``:=`` 赋值运算符时，就像为左侧信号/寄存器指定一个附加的新规则。" #: ../../SpinalHDL/Semantic/rules.rst:40 msgid "Last valid assignment wins" @@ -97,40 +98,39 @@ msgstr "最后有效赋值生效" #: ../../SpinalHDL/Semantic/rules.rst:42 msgid "" -"If a combinational signal or register is assigned multiple times through the" -" use of the SpinalHDL ``:=`` operator, the last assignment that may execute " -"wins (and so gets to set the value as a result for this state)." +"If a combinational signal or register is assigned multiple times through " +"the use of the SpinalHDL ``:=`` operator, the last assignment that may " +"execute wins (and so gets to set the value as a result for this state)." msgstr "" -"如果通过使用 SpinalHDL ``:=`` 运算符对组合信号或寄存器进行多次分配，则可能执" -"行的最后一次赋值生效（因此可以将值设置为该状态的结果）。" +"如果通过使用 SpinalHDL ``:=`` " +"运算符对组合信号或寄存器进行多次分配，则可能执行的最后一次赋值生效（因此可以将值设置为该状态的结果）。" #: ../../SpinalHDL/Semantic/rules.rst:46 +#, fuzzy msgid "" "It could be said that top to bottom evaluation occurs based on the state " -"that exists at that time. If your upstream signal inputs are driven from " -"registers and so have synchronous behaviour, then it could be said that at " -"each clock cycle the assignments are re-evaluated based on the new state at " -"the time." -msgstr "" -"可以说，自上而下的评估计算是根据当时的状态进行的。如果您的上游信号输入是从寄" -"存器驱动的，因此具有同步行为，那么可以说，在每个时钟周期，都会根据当时的新状" -"态重新计算、赋值。" +"that exists at that time. If your upstream signal inputs are driven from" +" registers and so have synchronous behavior, then it could be said that " +"at each clock cycle the assignments are re-evaluated based on the new " +"state at the time." +msgstr "可以说，自上而下的评估计算是根据当时的状态进行的。如果您的上游信号输入是从寄存器驱动的，因此具有同步行为，那么可以说，在每个时钟周期，都会根据当时的新状态重新计算、赋值。" #: ../../SpinalHDL/Semantic/rules.rst:51 msgid "" -"Some reasons why an assignment statement may not get to execute in hardware " -"this clock cycle, maybe due to it being wrapped in a ``when(cond)`` clause." -msgstr "在硬件中，赋值语句可能无法在本时钟周期执行的一些原因，可能是由于它被包装在 " -"``when(cond)`` 子句中。" +"Some reasons why an assignment statement may not get to execute in " +"hardware this clock cycle, maybe due to it being wrapped in a " +"``when(cond)`` clause." +msgstr "在硬件中，赋值语句可能无法在本时钟周期执行的一些原因，可能是由于它被包装在 ``when(cond)`` 子句中。" #: ../../SpinalHDL/Semantic/rules.rst:54 +#, fuzzy msgid "" "Another reason maybe that the SpinalHDL code never made it through " -"elaboration because the feature was paramaterized and disabled during HDL " -"code-generation, see ``paramIsFalse`` use below." +"elaboration because the feature was parameterized and disabled during HDL" +" code-generation, see ``paramIsFalse`` use below." msgstr "" -"另一个原因，可能是 SpinalHDL 代码从未通过实力细化，因为该功能在 HDL " -"代码生成期间被参数化并禁用，请参阅下面 ``paramIsFalse`` 的案例。" +"另一个原因，可能是 SpinalHDL 代码从未通过实力细化，因为该功能在 HDL 代码生成期间被参数化并禁用，请参阅下面 " +"``paramIsFalse`` 的案例。" #: ../../SpinalHDL/Semantic/rules.rst:58 msgid "As an example:" @@ -166,8 +166,7 @@ msgid "1" msgstr "1" #: ../../SpinalHDL/Semantic/rules.rst:92 ../../SpinalHDL/Semantic/rules.rst:95 -#: ../../SpinalHDL/Semantic/rules.rst:99 -#: ../../SpinalHDL/Semantic/rules.rst:100 +#: ../../SpinalHDL/Semantic/rules.rst:99 ../../SpinalHDL/Semantic/rules.rst:100 msgid "True" msgstr "True" @@ -180,8 +179,7 @@ msgid "3" msgstr "3" #: ../../SpinalHDL/Semantic/rules.rst:106 -msgid "" -"Signal and register interactions with Scala (OOP reference + Functions)" +msgid "Signal and register interactions with Scala (OOP reference + Functions)" msgstr "信号和寄存器与 Scala 语言的协作（OOP 引用 + 函数）" #: ../../SpinalHDL/Semantic/rules.rst:108 @@ -189,17 +187,16 @@ msgid "" "In SpinalHDL, each hardware element is modeled by a class instance. This " "means you can manipulate instances by using their references, such as " "passing them as arguments to a function." -msgstr "在 SpinalHDL 中，每个硬件元素都由一个类实例建模。这意味着您可以通过使用实例的" -"引用来操作实例，例如将它们作为参数传递给函数。" +msgstr "在 SpinalHDL 中，每个硬件元素都由一个类实例建模。这意味着您可以通过使用实例的引用来操作实例，例如将它们作为参数传递给函数。" #: ../../SpinalHDL/Semantic/rules.rst:110 msgid "" -"As an example, the following code implements a register which is incremented" -" when ``inc`` is True and cleared when ``clear`` is True (``clear`` has " -"priority over ``inc``) :" +"As an example, the following code implements a register which is " +"incremented when ``inc`` is True and cleared when ``clear`` is True " +"(``clear`` has priority over ``inc``) :" msgstr "" -"作为示例，以下代码实现了一个寄存器，当 ``inc`` 为 True 时递增，当 ``clear`` " -"为 True 时清零（``clear`` 优先于 ``inc``）：" +"作为示例，以下代码实现了一个寄存器，当 ``inc`` 为 True 时递增，当 ``clear`` 为 True 时清零（``clear`` " +"优先于 ``inc``）：" #: ../../SpinalHDL/Semantic/rules.rst:124 msgid "" @@ -217,29 +214,30 @@ msgstr "并指定函数应实现的赋值：" #: ../../SpinalHDL/Semantic/rules.rst:174 msgid "" -"All of the previous examples are strictly equivalent both in their generated" -" RTL and also in the SpinalHDL compiler's perspective. This is because " -"SpinalHDL only cares about the Scala runtime and the objects instantiated " -"there, it doesn't care about the Scala syntax itself." +"All of the previous examples are strictly equivalent both in their " +"generated RTL and also in the SpinalHDL compiler's perspective. This is " +"because SpinalHDL only cares about the Scala runtime and the objects " +"instantiated there, it doesn't care about the Scala syntax itself." msgstr "" -"前面的所有示例在生成的 RTL 中，从 SpinalHDL 编译器的角度来看都是严格等效的。" -"这是因为 SpinalHDL 只关心 Scala 运行时实例化的对象，它不关心 Scala 语法本身。" +"前面的所有示例在生成的 RTL 中，从 SpinalHDL 编译器的角度来看都是严格等效的。这是因为 SpinalHDL 只关心 Scala " +"运行时实例化的对象，它不关心 Scala 语法本身。" #: ../../SpinalHDL/Semantic/rules.rst:177 msgid "" "In other words, from a generated RTL generation / SpinalHDL perspective, " "when you use functions in Scala which generate hardware, it is like the " -"function was inlined. This is also true case for Scala loops, as they will " -"appear in unrolled form in the generated RTL." +"function was inlined. This is also true case for Scala loops, as they " +"will appear in unrolled form in the generated RTL." msgstr "" -"换句话说，从生成的 RTL 生成/SpinalHDL 的角度来看，当您调用 Scala " -"中生成硬件的函数时，就像该函数被内联了一样。 Scala 循环也是如此，" -"因为它们将以展开的形式出现在生成的 RTL 中。" +"换句话说，从生成的 RTL 生成/SpinalHDL 的角度来看，当您调用 Scala 中生成硬件的函数时，就像该函数被内联了一样。 Scala " +"循环也是如此，因为它们将以展开的形式出现在生成的 RTL 中。" #~ msgid "Introduction" #~ msgstr "介绍" #~ msgid "" -#~ "If a combinational signal or register is assigned multiple times, the last " -#~ "valid one wins." +#~ "If a combinational signal or register" +#~ " is assigned multiple times, the last" +#~ " valid one wins." #~ msgstr "如果组合信号或寄存器被分配多次，则最后一个有效的获胜。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po index abcf2b76dc8..53169b30401 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po @@ -1,26 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"POT-Creation-Date: 2024-01-31 16:22+0000\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-02-01 09:13+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Simulation/bootstraps.rst:3 msgid "Boot a simulation" @@ -223,22 +223,21 @@ msgid "" "The location of the wave file depend the backend used. For verilator it " "will be in the folder (``$WORKSPACE/$COMPILED/$TEST`` by default)." msgstr "" -"波形文件的存放路径会根据所选用的后端工具有所变化。在 Verilator 的情况下，" -"它通常会被保存在默认的路径 ``$WORKSPACE/$COMPILED/$TEST`` 下。" +"波形文件的存放路径会根据所选用的后端工具有所变化。在 Verilator 的情况下，它通常会被保存在默认的路径 " +"``$WORKSPACE/$COMPILED/$TEST`` 下。" #: ../../SpinalHDL/Simulation/bootstraps.rst:164 msgid "" "For the verilator backend, you can override the location of the test " "folder via the ``SimConfig.setTestPath(path)`` function." -msgstr "对于 Verilator 后端，可以使用 ``SimConfig.setTestPath(path)`` " -"函数设置测试文件夹位置。" +msgstr "对于 Verilator 后端，可以使用 ``SimConfig.setTestPath(path)`` 函数设置测试文件夹位置。" #: ../../SpinalHDL/Simulation/bootstraps.rst:165 +#, fuzzy msgid "" -"You can retrieve the location of the test path durring simulation by " +"You can retrieve the location of the test path during simulation by " "calling the currentTestPath() function." -msgstr "在进行仿真时，要确定测试文件夹的当前路径，可以调用 currentTestPath() " -"方法来获取。" +msgstr "在进行仿真时，要确定测试文件夹的当前路径，可以调用 currentTestPath() 方法来获取。" #: ../../SpinalHDL/Simulation/bootstraps.rst:169 msgid "Running multiple tests on the same hardware" @@ -334,3 +333,4 @@ msgstr "simWorkspace/Toplevel/tracer.fst : Waveform of the failure" #: ../../SpinalHDL/Simulation/bootstraps.rst:225 msgid "The scala terminal will show the explorer simulation stdout." msgstr "scala 终端将显示仿真结果到标准输出。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po index 69fc4352aeb..9eb8c8a9c20 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-13 05:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:3 msgid "Setup and installation of Icarus Verilog" @@ -25,24 +28,23 @@ msgstr "Icarus Verilog 的设置和安装" #: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:6 msgid "" -"If you installed the recommended oss-cad-suite during SpinalHDL :ref:`setup " -"` you can skip the instructions below - but you need to activate " -"the oss-cad-suite environment." +"If you installed the recommended oss-cad-suite during SpinalHDL " +":ref:`setup ` you can skip the instructions below - but you need" +" to activate the oss-cad-suite environment." msgstr "" -"如果您在 SpinalHDL :ref:`安装和设置 ` 期间安装了推荐的 oss-cad-" -"suite，您可以跳过下面的说明 - 但您需要激活 oss-cad-suite 环境。" +"如果您在 SpinalHDL :ref:`安装和设置 ` 期间安装了推荐的 oss-cad-suite，您可以跳过下面的说明 -" +" 但您需要激活 oss-cad-suite 环境。" #: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:9 msgid "" -"In most recent linux distributions, a recent version of Icarus Verilog is " -"generally available through the package system. The C++ library boost-" -"interprocess, which is contained in the libboost-dev package in debian-like " -"distributions, has to be installed too. boost-interprocess is required to " -"generate the shared memory communication interface." +"In most recent linux distributions, a recent version of Icarus Verilog is" +" generally available through the package system. The C++ library boost-" +"interprocess, which is contained in the libboost-dev package in debian-" +"like distributions, has to be installed too. boost-interprocess is " +"required to generate the shared memory communication interface." msgstr "" -"在大多数最新的 Linux 发行版中，最新版本的 Icarus Verilog " -"通常可以通过软件包系统获得。还必须安装 C++ 库 boost-interprocess，" -"它包含在类似 debian 发行版的 libboost-dev 包中。需要 boost-interprocess " +"在大多数最新的 Linux 发行版中，最新版本的 Icarus Verilog 通常可以通过软件包系统获得。还必须安装 C++ 库 boost-" +"interprocess，它包含在类似 debian 发行版的 libboost-dev 包中。需要 boost-interprocess " "来生成共享内存通信接口。" #: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:13 @@ -50,11 +52,13 @@ msgid "Linux" msgstr "Linux" #: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:20 +#, fuzzy msgid "" "Also the openjdk package that corresponds to your Java version has to be " -"installed. Refer to ``_" -" for more informations about Windows and installation from source." +"installed. Refer to " +"``_ for more " +"information about Windows and installation from source." msgstr "" "还必须安装与您的 Java 版本相对应的 openjdk 软件包。有关 Windows " -"和从源安装的更多信息，请参阅``_。" +"和从源安装的更多信息，请参阅``_。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po index 9e20aa1c7a7..bac1e393792 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-13 05:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Simulation/install/VCS.rst:3 msgid "VCS Simulation Configuration" @@ -52,13 +55,13 @@ msgstr "将以下路径添加到 ``LD_LIBRARY_PATH`` 变量的前部以启用 PL #: ../../SpinalHDL/Simulation/install/VCS.rst:26 msgid "" "If you encounter the ``Compilation of SharedMemIface.cpp failed`` error, " -"make sure that you have installed C++ boost library correctly. The header " -"and library files path should be added to ``CPLUS_INCLUDE_PATH``, " +"make sure that you have installed C++ boost library correctly. The header" +" and library files path should be added to ``CPLUS_INCLUDE_PATH``, " "``LIBRARY_PATH`` and ``LD_LIBRARY_PATH`` respectively." msgstr "" -"如果您遇到 ``Compilation of SharedMemIface.cpp failed`` 错误，" -"请确保您已正确安装 C++ boost 库。头文件和库文件路径应分别添加到 " -"``CPLUS_INCLUDE_PATH``、 ``LIBRARY_PATH`` 和 ``LD_LIBRARY_PATH`` 中。" +"如果您遇到 ``Compilation of SharedMemIface.cpp failed`` 错误，请确保您已正确安装 C++ boost" +" 库。头文件和库文件路径应分别添加到 ``CPLUS_INCLUDE_PATH``、 ``LIBRARY_PATH`` 和 " +"``LD_LIBRARY_PATH`` 中。" #: ../../SpinalHDL/Simulation/install/VCS.rst:30 msgid "User defined environment setup" @@ -66,23 +69,22 @@ msgstr "用户定义的环境设置" #: ../../SpinalHDL/Simulation/install/VCS.rst:32 msgid "" -"Sometimes a VCS environment setup file `synopsys_sim.setup` is required to " -"run VCS simulation. Also you may want to run some scripts or code to setup " -"the environment just before VCS starting compilation. You can do this by " -"`withVCSSimSetup`." +"Sometimes a VCS environment setup file `synopsys_sim.setup` is required " +"to run VCS simulation. Also you may want to run some scripts or code to " +"setup the environment just before VCS starting compilation. You can do " +"this by `withVCSSimSetup`." msgstr "" -"有时需要 VCS 环境设置文件 `synopsys_sim.setup` 来运行 VCS 仿真。此外，" -"您可能希望在 VCS 开始编译之前运行一些脚本或代码来设置环境。您可以通过 " -"`withVCSSimSetup` 来完成此操作。" +"有时需要 VCS 环境设置文件 `synopsys_sim.setup` 来运行 VCS 仿真。此外，您可能希望在 VCS " +"开始编译之前运行一些脚本或代码来设置环境。您可以通过 `withVCSSimSetup` 来完成此操作。" #: ../../SpinalHDL/Simulation/install/VCS.rst:47 msgid "" "This method will copy your own `synopsys_sim.setup` file to the VCS work " -"directory under the `workspacePath` (default as `simWorkspace`) directory, " -"and run your scripts." +"directory under the `workspacePath` (default as `simWorkspace`) " +"directory, and run your scripts." msgstr "" -"此方法将您自己的 `synopsys_sim.setup` 文件复制到 `workspacePath` （默认为 " -"`simWorkspace` ）目录下的VCS工作目录，并运行脚本。" +"此方法将您自己的 `synopsys_sim.setup` 文件复制到 `workspacePath` （默认为 `simWorkspace` " +"）目录下的VCS工作目录，并运行脚本。" #: ../../SpinalHDL/Simulation/install/VCS.rst:51 msgid "VCS Flags" @@ -110,8 +112,7 @@ msgstr "仿真步骤：运行仿真。" msgid "" "In each step, user can pass some specific flags through ``VCSFlags`` to " "enable some features like SDF back-annotation or multi-threads." -msgstr "在每个步骤中，用户可以通过 ``VCSFlags`` 传递一些特定的标志，以启用一些功能，" -"例如 SDF 反注释或多线程。" +msgstr "在每个步骤中，用户可以通过 ``VCSFlags`` 传递一些特定的标志，以启用一些功能，例如 SDF 反注释或多线程。" #: ../../SpinalHDL/Simulation/install/VCS.rst:63 msgid "``VCSFlags`` takes three parameters," @@ -210,8 +211,8 @@ msgstr "生成 ``FSDB`` 波形。" #: ../../SpinalHDL/Simulation/install/VCS.rst:120 msgid "" -"Also, you can control the wave trace depth by using ``withWaveDepth(depth: " -"Int)``." +"Also, you can control the wave trace depth by using " +"``withWaveDepth(depth: Int)``." msgstr "此外，您可以使用 ``withWaveDepth(depth: Int)`` 来控制波形文件记录的深度。" #: ../../SpinalHDL/Simulation/install/VCS.rst:123 @@ -219,24 +220,26 @@ msgid "Simulation with ``Blackbox``" msgstr "``Blackbox`` 仿真" #: ../../SpinalHDL/Simulation/install/VCS.rst:125 +#, fuzzy msgid "" -"Sometimes, IP vendors will provide you with some design entites in " +"Sometimes, IP vendors will provide you with some design entities in " "Verilog/VHDL format and you want to integrate them into your SpinalHDL " "design. The integration can done by following two ways:" msgstr "" -"有时，您希望将 IP 供应商为您提供的一些 Verilog/VHDL 格式的设计实体集成到您的 " -"SpinalHDL 设计中。可以通过以下两种方式完成：" +"有时，您希望将 IP 供应商为您提供的一些 Verilog/VHDL 格式的设计实体集成到您的 SpinalHDL " +"设计中。可以通过以下两种方式完成：" #: ../../SpinalHDL/Simulation/install/VCS.rst:128 msgid "" -"In a ``Blackbox`` definition, use ``addRTLPath(path: String)`` to assign a " -"external Verilog/VHDL file to this blackbox." +"In a ``Blackbox`` definition, use ``addRTLPath(path: String)`` to assign " +"a external Verilog/VHDL file to this blackbox." msgstr "" -"在 ``Blackbox`` 定义中，使用 ``addRTLPath(path: String)`` 将外部 Verilog/" -"VHDL 文件分配给该黑盒。" +"在 ``Blackbox`` 定义中，使用 ``addRTLPath(path: String)`` 将外部 Verilog/VHDL " +"文件分配给该黑盒。" #: ../../SpinalHDL/Simulation/install/VCS.rst:129 msgid "" "Use the method ``mergeRTLSource(fileName: String=null)`` of " "``SpinalReport``." msgstr "使用 ``SpinalReport`` 的 ``mergeRTLSource(fileName: String=null)`` 方法。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po index 9a91c4ac719..be499f9912c 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-13 05:06+0000\n" "Last-Translator: tsy0123 <675526215@qq.com>\n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Simulation/install/Verilator.rst:3 msgid "Setup and installation of Verilator" @@ -25,37 +28,34 @@ msgstr "Verilator 的设置和安装" #: ../../SpinalHDL/Simulation/install/Verilator.rst:6 msgid "" -"If you installed the recommended oss-cad-suite during SpinalHDL :ref:`setup " -"` you can skip the instructions below - but you need to activate " -"the oss-cad-suite environment." +"If you installed the recommended oss-cad-suite during SpinalHDL " +":ref:`setup ` you can skip the instructions below - but you need" +" to activate the oss-cad-suite environment." msgstr "" -"如果您在 SpinalHDL :ref:`安装和设置 ` 期间安装了推荐的 oss-cad-" -"suite，您可以跳过下面的说明 - 但您需要激活 oss-cad-suite 环境。" +"如果您在 SpinalHDL :ref:`安装和设置 ` 期间安装了推荐的 oss-cad-suite，您可以跳过下面的说明 -" +" 但您需要激活 oss-cad-suite 环境。" #: ../../SpinalHDL/Simulation/install/Verilator.rst:9 -msgid "" -"SpinalSim + Verilator is supported on both Linux and Windows platforms." +msgid "SpinalSim + Verilator is supported on both Linux and Windows platforms." msgstr "Linux 和 Windows 平台均支持 SpinalSim + Verilator。" #: ../../SpinalHDL/Simulation/install/Verilator.rst:11 msgid "" -"It is recommended that v4.218 is the oldest Verilator version to use. While" -" it maybe possible to use older verilator versions, some optional and Scala " -"source dependent features that SpinalHDL can use (such as Verilog " -"``$urandom`` support) may not be supported by older Verilator versions and " -"will cause an error when trying to simulate." +"It is recommended that v4.218 is the oldest Verilator version to use. " +"While it maybe possible to use older verilator versions, some optional " +"and Scala source dependent features that SpinalHDL can use (such as " +"Verilog ``$urandom`` support) may not be supported by older Verilator " +"versions and will cause an error when trying to simulate." msgstr "" -"建议使用的 Verilator 版本最老不低于 v4.218。虽然可以使用较旧的 verilator " -"版本，但 SpinalHDL 可以使用的一些可选的和 Scala 源文件相关功能（例如 Verilog " -"``$urandom`` 支持）可能不受旧版本 Verilator " +"建议使用的 Verilator 版本最老不低于 v4.218。虽然可以使用较旧的 verilator 版本，但 SpinalHDL " +"可以使用的一些可选的和 Scala 源文件相关功能（例如 Verilog ``$urandom`` 支持）可能不受旧版本 Verilator " "支持，并且会在尝试仿真时会导致错误。" #: ../../SpinalHDL/Simulation/install/Verilator.rst:16 msgid "" "Ideally the latest v4.xxx and v5.xxx is well supported and bug reports " "should be opened with any issues you have." -msgstr "理想情况下，最新的 v4.xxx 和 v5.xxx " -"得到良好支持，并且应针对您遇到的任何问题打开错误报告工单。" +msgstr "理想情况下，最新的 v4.xxx 和 v5.xxx 得到良好支持，并且应针对您遇到的任何问题打开错误报告工单。" #: ../../SpinalHDL/Simulation/install/Verilator.rst:20 msgid "Scala" @@ -66,8 +66,7 @@ msgid "Don't forget to add the following in your ``build.sbt`` file:" msgstr "不要忘记在 ``build.sbt`` 文件中添加以下内容：" #: ../../SpinalHDL/Simulation/install/Verilator.rst:28 -msgid "" -"And you will always need the following imports in your Scala testbench:" +msgid "And you will always need the following imports in your Scala testbench:" msgstr "你总是需要在Scala测试平台中加入以下导入代码：" #: ../../SpinalHDL/Simulation/install/Verilator.rst:36 @@ -84,8 +83,8 @@ msgstr "Windows" #: ../../SpinalHDL/Simulation/install/Verilator.rst:58 msgid "" -"In order to get SpinalSim + Verilator working on Windows, you have to do the" -" following:" +"In order to get SpinalSim + Verilator working on Windows, you have to do " +"the following:" msgstr "为了让 SpinalSim + Verilator 在 Windows 上工作，您必须执行以下操作：" #: ../../SpinalHDL/Simulation/install/Verilator.rst:60 @@ -94,8 +93,8 @@ msgstr "安装 `MSYS2 `_" #: ../../SpinalHDL/Simulation/install/Verilator.rst:61 msgid "" -"Via MSYS2 get gcc/g++/verilator (for Verilator you can compile it from the " -"sources)" +"Via MSYS2 get gcc/g++/verilator (for Verilator you can compile it from " +"the sources)" msgstr "通过 MSYS2 获取 gcc/g++/verilator （对于 Verilator，您可以从源代码编译它）" #: ../../SpinalHDL/Simulation/install/Verilator.rst:62 @@ -103,30 +102,27 @@ msgid "" "Add ``bin`` and ``usr\\bin`` of MSYS2 into your windows ``PATH`` (ie : " "``C:\\msys64\\usr\\bin;C:\\msys64\\mingw64\\bin``)" msgstr "" -"将 MSYS2 的 ``bin`` 和 ``usr\\bin`` 添加到 Windows ``PATH`` 中（即：``C:" -"\\msys64\\usr\\bin;C:\\msys64\\mingw64 \\bin``)" +"将 MSYS2 的 ``bin`` 和 ``usr\\bin`` 添加到 Windows ``PATH`` " +"中（即：``C:\\msys64\\usr\\bin;C:\\msys64\\mingw64 \\bin``)" #: ../../SpinalHDL/Simulation/install/Verilator.rst:63 msgid "" -"Check that the JAVA_HOME environment variable points to the JDK installation" -" folder (i.e.: ``C:\\Program Files\\Java\\jdk-13.0.2``)" -msgstr "" -"检查 JAVA_HOME 环境变量是否指向 JDK 安装文件夹（即：``C:\\Program Files\\Java" -"\\jdk-13.0.2``）" +"Check that the JAVA_HOME environment variable points to the JDK " +"installation folder (i.e.: ``C:\\Program Files\\Java\\jdk-13.0.2``)" +msgstr "检查 JAVA_HOME 环境变量是否指向 JDK 安装文件夹（即：``C:\\Program Files\\Java\\jdk-13.0.2``）" #: ../../SpinalHDL/Simulation/install/Verilator.rst:65 msgid "" -"Then you should be able to run SpinalSim + Verilator from your Scala project" -" without having to use MSYS2 anymore." +"Then you should be able to run SpinalSim + Verilator from your Scala " +"project without having to use MSYS2 anymore." msgstr "然后您应该能够从 Scala 项目运行 SpinalSim + Verilator，而无需再使用 MSYS2。" #: ../../SpinalHDL/Simulation/install/Verilator.rst:67 msgid "" "From a fresh install of MSYS2 MinGW 64-bit, you will have to run the " -"following commands inside the MSYS2 MinGW 64-bits shell (enter commands one " -"by one):" -msgstr "从全新安装 MSYS2 MinGW 64 位开始，您必须在 MSYS2 MinGW 64 位 shell " -"中运行以下命令：" +"following commands inside the MSYS2 MinGW 64-bits shell (enter commands " +"one by one):" +msgstr "从全新安装 MSYS2 MinGW 64 位开始，您必须在 MSYS2 MinGW 64 位 shell 中运行以下命令：" #: ../../SpinalHDL/Simulation/install/Verilator.rst:70 msgid "From the MinGW package manager" @@ -138,16 +134,17 @@ msgstr "从源码安装" #: ../../SpinalHDL/Simulation/install/Verilator.rst:114 msgid "" -"Be sure that your ``PATH`` environnement variable is pointing to the JDK 1.8" -" and doesn't contain a JRE installation." +"Be sure that your ``PATH`` environnement variable is pointing to the JDK " +"1.8 and doesn't contain a JRE installation." msgstr "确保您的 ``PATH`` 环境变量指向 JDK 1.8 并且不包含 JRE 安装。" #: ../../SpinalHDL/Simulation/install/Verilator.rst:117 +#, fuzzy msgid "" -"Adding the MSYS2 ``bin`` folders into your windows ``PATH`` could potentialy" -" have some side effects. This is why it is safer to add them as the last " -"elements of the ``PATH`` to reduce their priority." +"Adding the MSYS2 ``bin`` folders into your windows ``PATH`` could " +"potentially have some side effects. This is why it is safer to add them " +"as the last elements of the ``PATH`` to reduce their priority." msgstr "" -"将 MSYS2 ``bin`` 文件夹添加到 Windows ``PATH`` 可能会产生一些副作用。" -"这就是为什么将它们添加为 ``PATH`` " +"将 MSYS2 ``bin`` 文件夹添加到 Windows ``PATH`` 可能会产生一些副作用。这就是为什么将它们添加为 ``PATH`` " "的最后一个元素以降低其优先级，这样会更安全。" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po index 9f25d83beee..aa2d4441739 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po @@ -1,26 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"POT-Creation-Date: 2024-01-26 16:21+0000\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2024-01-26 17:04+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Language-Team: Chinese (Simplified) \n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" -"Generated-By: Babel 2.14.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Structuring/clock_domain.rst:4 msgid "Clock domains" @@ -362,10 +362,11 @@ msgstr "" "``syncReset`` 和 ``softReset``。" #: ../../SpinalHDL/Structuring/clock_domain.rst:300 +#, fuzzy msgid "" "Please be careful that clockEnable has a higher priority than syncReset. " "If you do a sync reset when the clockEnable is disabled (especially at " -"the beginning of a simulation), the gated registers will not be reseted." +"the beginning of a simulation), the gated registers will not be reset." msgstr "" "请注意，clockEnable " "的优先级高于syncReset。如果在禁用clockEnable（尤其是在仿真开始时）时执行同步重置，则门控寄存器将不会重置。" @@ -379,8 +380,9 @@ msgid "It will generate VerilogHDL codes like:" msgstr "它将生成 Verilog HDL 代码，例如：" #: ../../SpinalHDL/Structuring/clock_domain.rst:324 +#, fuzzy msgid "" -"If that behaviour is problematic, one workaround is to use a when " +"If that behavior is problematic, one workaround is to use a when " "statement as a clock enable instead of using the ClockDomain.enable " "feature. This is open for future improvements." msgstr "如果该行为有问题，一种解决方法是使用when 语句作为时钟使能，而不是使用ClockDomain.enable 功能。这对于未来的改进是开放的。" @@ -591,9 +593,8 @@ msgid "" "``ClockDomain.current.readClockEnableWire``" msgstr "" "SlowArea 中使用的时钟信号与父区域相同。而 SlowArea " -"会添加一个时钟启用信号，以减慢其内部的采样率。换句话说，``ClockDomain.current" -".readClockWire`` 将返回快速（父域）时钟。要获取时钟使能信号，请使用 " -"``ClockDomain.current.readClockEnableWire``" +"会添加一个时钟启用信号，以减慢其内部的采样率。换句话说，``ClockDomain.current.readClockWire`` " +"将返回快速（父域）时钟。要获取时钟使能信号，请使用 ``ClockDomain.current.readClockEnableWire``" #: ../../SpinalHDL/Structuring/clock_domain.rst:517 msgid "BootReset" @@ -627,3 +628,4 @@ msgid "" "A ``ClockEnableArea`` is used to add an additional clock enable in the " "current clock domain:" msgstr "``ClockEnableArea`` 用于在当前时钟域中添加额外的时钟使能信号：" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po index 1352908e0f6..006f6772679 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po @@ -10,7 +10,7 @@ msgstr "" "+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" -"POT-Creation-Date: 2024-07-29 08:01+0000\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-24 15:38+0000\n" "Last-Translator: Readon \n" "Language: zh_CN\n" @@ -20,7 +20,7 @@ msgstr "" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Generated-By: Babel 2.15.0\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Structuring/components_hierarchy.rst:4 msgid "Components and hierarchy" @@ -177,8 +177,9 @@ msgid "Pruned signals" msgstr "裁剪信号" #: ../../SpinalHDL/Structuring/components_hierarchy.rst:92 +#, fuzzy msgid "" -"SpinalHDL will generate all the named signals and their depedencies, " +"SpinalHDL will generate all the named signals and their dependencies, " "while all the useless anonymous / zero width ones are removed from the " "RTL generation." msgstr "SpinalHDL 将生成所有命名信号及其依赖性，而所有无用的匿名/零位宽信号将从 RTL 生成中删除。" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po index 914268904b1..3f4c259ac0b 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-24 15:38+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Structuring/index.rst:3 msgid "Structuring" @@ -40,9 +43,11 @@ msgid "handling of clock/reset domains" msgstr "时钟/复位域的处理" #: ../../SpinalHDL/Structuring/index.rst:10 -msgid "instantitation of existing VHDL and Verilog IP" +#, fuzzy +msgid "instantiation of existing VHDL and Verilog IP" msgstr "现有 VHDL 和 Verilog IP 的实例化" #: ../../SpinalHDL/Structuring/index.rst:11 msgid "how names are assigned in SpinalHDL, and how naming can be influenced" msgstr "SpinalHDL 中如何为信号等分配名称，以及如何影响命名" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po index 98c7c3a59db..62e3a62e66d 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-24 15:38+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Structuring/naming.rst:2 msgid "Preserving names" @@ -25,12 +28,10 @@ msgstr "保留名称的方法" #: ../../SpinalHDL/Structuring/naming.rst:4 msgid "" -"This page will describe how SpinalHDL propagate names from the scala code to" -" the generated hardware. Knowing them should enable you to preserve those " -"names as much as possible to generate understandable netlists." -msgstr "" -"本页将描述 SpinalHDL 如何将名称从 scala 代码传播到生成的硬件 " -"RTL。您应该了解它们，从而尽可能保留这些名称，以生成可理解的网表。" +"This page will describe how SpinalHDL propagate names from the scala code" +" to the generated hardware. Knowing them should enable you to preserve " +"those names as much as possible to generate understandable netlists." +msgstr "本页将描述 SpinalHDL 如何将名称从 scala 代码传播到生成的硬件 RTL。您应该了解它们，从而尽可能保留这些名称，以生成可理解的网表。" #: ../../SpinalHDL/Structuring/naming.rst:7 msgid "Nameable base class" @@ -67,11 +68,11 @@ msgid "Will generation :" msgstr "会生成：" #: ../../SpinalHDL/Structuring/naming.rst:41 +#, fuzzy msgid "" -"In general, you don't realy need to access that API, unless you want to do " -"tricky stuff for debug reasons or for elaboration purposes." -msgstr "一般来说，您实际上并不需要访问该 " -"API，除非您出于调试原因或出于详细说明的目的想要做一些精巧的工作。" +"In general, you don't really need to access that API, unless you want to " +"do tricky stuff for debug reasons or for elaboration purposes." +msgstr "一般来说，您实际上并不需要访问该 API，除非您出于调试原因或出于详细说明的目的想要做一些精巧的工作。" #: ../../SpinalHDL/Structuring/naming.rst:44 msgid "Name extraction from Scala" @@ -79,17 +80,15 @@ msgstr "从 Scala 中提取名称" #: ../../SpinalHDL/Structuring/naming.rst:46 msgid "" -"First, since version 1.4.0, SpinalHDL use a scala compiler plugin which can " -"provide a call back each time a new val is defined during the construction " -"of an class." -msgstr "" -"首先，从 1.4.0 版本开始，SpinalHDL 使用 scala 编译器插件，" -"该插件可以在类构造期间在每次定义新 val 时，实现函数回调。" +"First, since version 1.4.0, SpinalHDL use a scala compiler plugin which " +"can provide a call back each time a new val is defined during the " +"construction of an class." +msgstr "首先，从 1.4.0 版本开始，SpinalHDL 使用 scala 编译器插件，该插件可以在类构造期间在每次定义新 val 时，实现函数回调。" #: ../../SpinalHDL/Structuring/naming.rst:48 msgid "" -"There is a example showing more or less how SpinalHDL itself is implemented " -":" +"There is a example showing more or less how SpinalHDL itself is " +"implemented :" msgstr "这个示例或多或少地展示了 SpinalHDL 本身是如何实现的：" #: ../../SpinalHDL/Structuring/naming.rst:78 @@ -100,12 +99,12 @@ msgstr "使用 ValCallback“自省”功能，SpinalHDL 的组件类能够了 #: ../../SpinalHDL/Structuring/naming.rst:80 msgid "" -"But this also mean that if you want something to get a name, and you only " -"rely on this automatic naming feature, the reference to your Data (UInt, " -"SInt, ...) instances should be stored somewhere in a Component val." +"But this also mean that if you want something to get a name, and you only" +" rely on this automatic naming feature, the reference to your Data (UInt," +" SInt, ...) instances should be stored somewhere in a Component val." msgstr "" -"但这也意味着，如果您希望某些东西获得名称，并且仅依赖于此自动命名功能，则对 " -"Data (UInt、SInt、...) 实例的引用应存储在组件的某个 val 对象定义中。" +"但这也意味着，如果您希望某些东西获得名称，并且仅依赖于此自动命名功能，则对 Data (UInt、SInt、...) 实例的引用应存储在组件的某个" +" val 对象定义中。" #: ../../SpinalHDL/Structuring/naming.rst:82 msgid "For instance :" @@ -146,8 +145,8 @@ msgstr "函数中的逻辑区" #: ../../SpinalHDL/Structuring/naming.rst:147 msgid "" -"You can also define function which will create new Area which will provide a" -" namespace for all its content :" +"You can also define function which will create new Area which will " +"provide a namespace for all its content :" msgstr "您还可以定义将创建新逻辑区的函数，该逻辑区将为其所有内容提供命名空间：" #: ../../SpinalHDL/Structuring/naming.rst:163 @@ -160,10 +159,9 @@ msgstr "函数中的复合区（Composite）" #: ../../SpinalHDL/Structuring/naming.rst:181 msgid "" -"Added in SpinalHDL 1.5.0, Composite which allow you to create a scope which " -"will use as prefix another Nameable:" -msgstr "SpinalHDL 1.5.0 中添加了复合区，它允许您创建一个范围，该范围将用作另一个 " -"Nameable 的前缀：" +"Added in SpinalHDL 1.5.0, Composite which allow you to create a scope " +"which will use as prefix another Nameable:" +msgstr "SpinalHDL 1.5.0 中添加了复合区，它允许您创建一个范围，该范围将用作另一个 Nameable 的前缀：" #: ../../SpinalHDL/Structuring/naming.rst:213 msgid "Composite chains" @@ -178,8 +176,9 @@ msgid "Composite in a Bundle's function" msgstr "在一个线束（Bundle）的函数中的复合区" #: ../../SpinalHDL/Structuring/naming.rst:255 +#, fuzzy msgid "" -"This behaviour can be very useful when implementing Bundle utilities. For " +"This behavior can be very useful when implementing Bundle utilities. For " "instance in the spinal.lib.Stream class is defined the following :" msgstr "在实现线束工具时，此行为非常有用。例如，在 ``spin.lib.Stream`` 类中定义如下：" @@ -188,51 +187,55 @@ msgid "Which allow nested calls while preserving the names :" msgstr "这将允许嵌套调用，同时保留名称：" #: ../../SpinalHDL/Structuring/naming.rst:363 -msgid "Unamed signal handling" +#, fuzzy +msgid "Unnamed signal handling" msgstr "未命名信号处理" #: ../../SpinalHDL/Structuring/naming.rst:365 +#, fuzzy msgid "" "Since 1.5.0, for signal which end up without name, SpinalHDL will find a " -"signal which is driven by that unamed signal and propagate its name. This " -"can produce useful results as long you don't have too large island of unamed" -" stuff." +"signal which is driven by that unnamed signal and propagate its name. " +"This can produce useful results as long you don't have too large island " +"of unnamed stuff." msgstr "" -"从 1.5.0 开始，对于最终没有名称的信号，SpinalHDL 将找到由该信号驱动的信号并传" -"播其名称。只要您没有太多未命名的东西，这就可以产生有用的结果。" +"从 1.5.0 开始，对于最终没有名称的信号，SpinalHDL " +"将找到由该信号驱动的信号并传播其名称。只要您没有太多未命名的东西，这就可以产生有用的结果。" #: ../../SpinalHDL/Structuring/naming.rst:367 +#, fuzzy msgid "" -"The name attributed to such unamed signal is : _zz_ + drivenSignal.getName()" +"The name attributed to such unnamed signal is : _zz_ + " +"drivenSignal.getName()" msgstr "这种未命名信号的名称是：_zz_ +drivenSignal.getName()" #: ../../SpinalHDL/Structuring/naming.rst:369 msgid "" -"Note that this naming pattern is also used by the generation backend when " -"they need to breakup some specific expressions or long chain of expression " -"into multiple signals." -msgstr "请注意，当生成后端需要将某些特定表达式或表达式链分解为多个信号时，也会使用此" -"命名模式。" +"Note that this naming pattern is also used by the generation backend when" +" they need to breakup some specific expressions or long chain of " +"expression into multiple signals." +msgstr "请注意，当生成后端需要将某些特定表达式或表达式链分解为多个信号时，也会使用此命名模式。" #: ../../SpinalHDL/Structuring/naming.rst:372 msgid "Verilog expression splitting" msgstr "Verilog 表达式分割" #: ../../SpinalHDL/Structuring/naming.rst:374 +#, fuzzy msgid "" "There is an instance of expressions (ex : the + operator) that SpinalHDL " -"need to express in dedicated signals to match the behaviour with the Scala " -"API :" -msgstr "下例中， SpinalHDL 需要使用指定信号描述一个表达式（例如：+ 运算符），" -"以将其行为与 Scala API 相匹配：" +"need to express in dedicated signals to match the behavior with the Scala" +" API :" +msgstr "下例中， SpinalHDL 需要使用指定信号描述一个表达式（例如：+ 运算符），以将其行为与 Scala API 相匹配：" #: ../../SpinalHDL/Structuring/naming.rst:404 msgid "Verilog long expression splitting" msgstr "Verilog 长表达式分割" #: ../../SpinalHDL/Structuring/naming.rst:406 +#, fuzzy msgid "" -"There is a instance of how a very long expression chain will be splited up " +"There is a instance of how a very long expression chain will be split up " "by SpinalHDL :" msgstr "下例说明了 SpinalHDL 如何分割一个长表达式链：" @@ -243,11 +246,11 @@ msgstr "When 语句条件" #: ../../SpinalHDL/Structuring/naming.rst:450 msgid "" "The `when(cond) { }` statements condition are generated into separated " -"signals named `when_` + fileName + line. A similar thing will also be done " -"for switch statements." +"signals named `when_` + fileName + line. A similar thing will also be " +"done for switch statements." msgstr "" -"`when(cond) { }` 语句条件生成为名为 `when_` + fileName + line 的单独信号。 " -"对 switch 语句也会做类似的事情。" +"`when(cond) { }` 语句条件生成为名为 `when_` + fileName + line 的单独信号。 对 switch " +"语句也会做类似的事情。" #: ../../SpinalHDL/Structuring/naming.rst:500 msgid "In last resort" @@ -255,22 +258,21 @@ msgstr "最后一招" #: ../../SpinalHDL/Structuring/naming.rst:502 msgid "" -"In last resort, if a signal has no name (anonymous signal), SpinalHDL will " -"seek for a named signal which is driven by the anonymous signal, and use it " -"as a name postfix :" -msgstr "最后，如果信号没有名称（匿名信号），SpinalHDL " -"将寻找由匿名信号驱动的命名信号，并将其用作名称后缀：" +"In last resort, if a signal has no name (anonymous signal), SpinalHDL " +"will seek for a named signal which is driven by the anonymous signal, and" +" use it as a name postfix :" +msgstr "最后，如果信号没有名称（匿名信号），SpinalHDL 将寻找由匿名信号驱动的命名信号，并将其用作名称后缀：" #: ../../SpinalHDL/Structuring/naming.rst:542 -msgid "" -"This last resort naming skim isn't ideal in all cases, but can help out." +msgid "This last resort naming skim isn't ideal in all cases, but can help out." msgstr "最后的命名方法并不适合所有情况，但可以提供帮助。" #: ../../SpinalHDL/Structuring/naming.rst:544 msgid "" -"Note that signal starting with a underscore aren't stored in the Verilator " -"waves (on purpose)" +"Note that signal starting with a underscore aren't stored in the " +"Verilator waves (on purpose)" msgstr "请注意，以下划线开头的信号不会存储在 Verilator 波形中（这是故意的）" #~ msgid "Introduction" #~ msgstr "介绍" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po index c33a1b2f00f..c67ffe37e7e 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-24 15:57+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/Structuring/parametrization.rst:2 msgid "Parametrization" @@ -31,98 +34,94 @@ msgstr "参数化有多个方面的含义：" msgid "" "Providing and the management of, elaboration time parameters provided to " "SpinalHDL during elaboration of the design" -msgstr "在设计实例细化（elaboration）过程中向 SpinalHDL " -"提供细化过程的参数并对其进行管理" +msgstr "在设计实例细化（elaboration）过程中向 SpinalHDL 提供细化过程的参数并对其进行管理" #: ../../SpinalHDL/Structuring/parametrization.rst:8 msgid "" "Using the parameter data to allow the designer to perform any kind of " -"hardware construction, configuration and interconnection task needed in the " -"design. Such as optional component generation within the hardware design." -msgstr "通过使用参数，设计人员可以实现任何类型硬件的构造、配置和互连任务。例如硬件设" -"计中的可选组件生成。" +"hardware construction, configuration and interconnection task needed in " +"the design. Such as optional component generation within the hardware " +"design." +msgstr "通过使用参数，设计人员可以实现任何类型硬件的构造、配置和互连任务。例如硬件设计中的可选组件生成。" #: ../../SpinalHDL/Structuring/parametrization.rst:13 msgid "" "Parallels exist with the aims of HDL features such as Verilog module " "parameters and VHDL generics. SpinalHDL brings a far richer and more " -"powerful set of capabilities into this area with the additional protection " -"of Scala type safety and SpinalHDL built in HDL design rule checking." +"powerful set of capabilities into this area with the additional " +"protection of Scala type safety and SpinalHDL built in HDL design rule " +"checking." msgstr "" -"与 HDL 泛化功能（例如 Verilog 模块参数和 VHDL 泛型）的目标类似。 SpinalHDL " -"通过 Scala 类型安全和内置 HDL " -"设计规则检查带来额外保护，提供了更丰富、更强大的功能集。" +"与 HDL 泛化功能（例如 Verilog 模块参数和 VHDL 泛型）的目标类似。 SpinalHDL 通过 Scala 类型安全和内置 HDL" +" 设计规则检查带来额外保护，提供了更丰富、更强大的功能集。" #: ../../SpinalHDL/Structuring/parametrization.rst:19 msgid "" -"The SpinalHDL mechanisms for parameterization of components is not built on " -"top of any native HDL mechanism and so is not impeded by HDL language " +"The SpinalHDL mechanisms for parameterization of components is not built " +"on top of any native HDL mechanism and so is not impeded by HDL language " "level/version support or restrictions about what can be achieved in hand " "written HDL." msgstr "" -"用于组件参数化的 SpinalHDL 机制不是构建在任何 HDL 机制之上，因此，不会受到 " -"HDL 语言级别/版本支持或手写 HDL 带来限制的影响。" +"用于组件参数化的 SpinalHDL 机制不是构建在任何 HDL 机制之上，因此，不会受到 HDL 语言级别/版本支持或手写 HDL " +"带来限制的影响。" #: ../../SpinalHDL/Structuring/parametrization.rst:24 msgid "" "For readers looking to interoperate with parameterized Verilog or " -"genericized VHDL using SpinalHDL, please see the section on :ref:`BlackBox " -"` IP for those scenarios your project requires." +"genericized VHDL using SpinalHDL, please see the section on " +":ref:`BlackBox ` IP for those scenarios your project requires." msgstr "" -"对于希望使用 SpinalHDL 与参数化 Verilog 或通用 VHDL 进行互操作的读者，请参阅 " -":ref:`BlackBox ` IP 中有关您的项目所需场景的部分。" +"对于希望使用 SpinalHDL 与参数化 Verilog 或通用 VHDL 进行互操作的读者，请参阅 :ref:`BlackBox " +"` IP 中有关您的项目所需场景的部分。" #: ../../SpinalHDL/Structuring/parametrization.rst:31 msgid "Elaboration time parameters" msgstr "实例细化时参数" #: ../../SpinalHDL/Structuring/parametrization.rst:33 -msgid "" -"You can use the whole Scala syntax to provide elaboration time parameters." +msgid "You can use the whole Scala syntax to provide elaboration time parameters." msgstr "您可以使用所有 Scala 语法来提供实例细化时参数。" #: ../../SpinalHDL/Structuring/parametrization.rst:35 msgid "" "The whole syntax means you have the entire power and feature set of the " -"Scala language at your disposal to solve parameterization requirements for " -"your project at the level of complexity you choose." -msgstr "所有的语法意味着您可以使用 Scala " -"语言的全部功能，以按照您选择的复杂程度解决项目的参数化要求。" +"Scala language at your disposal to solve parameterization requirements " +"for your project at the level of complexity you choose." +msgstr "所有的语法意味着您可以使用 Scala 语言的全部功能，以按照您选择的复杂程度解决项目的参数化要求。" #: ../../SpinalHDL/Structuring/parametrization.rst:39 msgid "" -"SpinalHDL does not place any opinionated restrictions on how to achieve your" -" parameterization goals. As such there are many Scala design patterns and a" -" few SpinalHDL helpers that can be used to manage parameters that are suited" -" to different parameter management scenarios." +"SpinalHDL does not place any opinionated restrictions on how to achieve " +"your parameterization goals. As such there are many Scala design " +"patterns and a few SpinalHDL helpers that can be used to manage " +"parameters that are suited to different parameter management scenarios." msgstr "" -"SpinalHDL 不会对如何实现参数化目标施加任何特殊限制。因此，有许多 Scala " -"设计模式和一些 SpinalHDL 帮助程序可用于管理参数，以适合不同场景。" +"SpinalHDL 不会对如何实现参数化目标施加任何特殊限制。因此，有许多 Scala 设计模式和一些 SpinalHDL " +"帮助程序可用于管理参数，以适合不同场景。" #: ../../SpinalHDL/Structuring/parametrization.rst:44 msgid "Here are some examples and ideas of the possibilities:" msgstr "以下是一些示例和可能的想法：" #: ../../SpinalHDL/Structuring/parametrization.rst:46 +#, fuzzy msgid "" -"Hardwired code and constants (not strictly parameter management at all but " -"serves to hilight the most basic mechanism, a code change, not a parameter " -"data change)" -msgstr "硬连线代码和常量（突出最基本的机制，而不是严格的参数管理，代码上的变更，而不" -"是数据上的变更）" +"Hardwired code and constants (not strictly parameter management at all " +"but serves to highlight the most basic mechanism, a code change, not a " +"parameter data change)" +msgstr "硬连线代码和常量（突出最基本的机制，而不是严格的参数管理，代码上的变更，而不是数据上的变更）" #: ../../SpinalHDL/Structuring/parametrization.rst:49 msgid "" -"Constant values provided from a companion object that are static constants " -"in Scala." +"Constant values provided from a companion object that are static " +"constants in Scala." msgstr "由伴随对象提供的常量值在 Scala 中是静态常量。" #: ../../SpinalHDL/Structuring/parametrization.rst:51 msgid "" "Values provided to Scala class constructor, often a ``case class`` that " "causes Scala to capture those constructor argument values as constants." -msgstr "提供给 Scala 类构造函数的值，通常一个 ``case class`` 会导致 Scala " -"将这些构造函数的参数值捕获为常量。" +msgstr "提供给 Scala 类构造函数的值，通常一个 ``case class`` 会导致 Scala 将这些构造函数的参数值捕获为常量。" #: ../../SpinalHDL/Structuring/parametrization.rst:53 msgid "" @@ -138,10 +137,9 @@ msgstr "配置类的模式（示例存在于库中，包括 UartCtrlConfig_, Spi #: ../../SpinalHDL/Structuring/parametrization.rst:57 msgid "" -"Project defined 'Plugin' pattern (examples exist in the VexRiscV_ project to" -" configure the feature set the resulting CPU IP core is built with)" -msgstr "项目定义的“插件”模式（在 VexRiscV_ 项目中有示例，用于配置生成的 CPU IP " -"核所使用的功能集）" +"Project defined 'Plugin' pattern (examples exist in the VexRiscV_ project" +" to configure the feature set the resulting CPU IP core is built with)" +msgstr "项目定义的“插件”模式（在 VexRiscV_ 项目中有示例，用于配置生成的 CPU IP 核所使用的功能集）" #: ../../SpinalHDL/Structuring/parametrization.rst:59 msgid "" @@ -155,16 +153,16 @@ msgstr "“任何你可以创建的机制”" #: ../../SpinalHDL/Structuring/parametrization.rst:63 msgid "" -"All of the mechanisms result in a change in resulting elaborated HDL output." +"All of the mechanisms result in a change in resulting elaborated HDL " +"output." msgstr "所有机制都会导致实力细化生成的 HDL 输出发生变化。" #: ../../SpinalHDL/Structuring/parametrization.rst:65 msgid "" -"This could vary from a single constant value change all the way through to " -"describing the entire bus and interconnection architecture of an entire SoC " -"all without leaving the Scala programming paradigm." -msgstr "这可以仅仅使用 Scala 编程就完成设计，支持单个常数值到整个 SoC " -"的所有总线和互连架构描述的参数化。" +"This could vary from a single constant value change all the way through " +"to describing the entire bus and interconnection architecture of an " +"entire SoC all without leaving the Scala programming paradigm." +msgstr "这可以仅仅使用 Scala 编程就完成设计，支持单个常数值到整个 SoC 的所有总线和互连架构描述的参数化。" #: ../../SpinalHDL/Structuring/parametrization.rst:70 msgid "Here is an example of class parameters" @@ -172,13 +170,12 @@ msgstr "这是一个类参数的示例" #: ../../SpinalHDL/Structuring/parametrization.rst:84 msgid "" -"You can also use global variable defined in Scala objects (companion object " -"pattern)." +"You can also use global variable defined in Scala objects (companion " +"object pattern)." msgstr "您还可以使用 Scala 对象（伴随对象模式）中定义的全局变量。" #: ../../SpinalHDL/Structuring/parametrization.rst:87 -msgid "" -"A :ref:`ScopeProperty ` can also be used for configuration." +msgid "A :ref:`ScopeProperty ` can also be used for configuration." msgstr "\\ :ref:`ScopeProperty ` 也可用于配置。" #: ../../SpinalHDL/Structuring/parametrization.rst:90 @@ -197,33 +194,35 @@ msgstr "对于可选信号：" msgid "" "The ``generate`` method is a mechanism to evaluate the expression that " "follows for an optional value. If the predicate is true, generate will " -"evaluate the given expression and return the result, otherwise it returns " -"null." +"evaluate the given expression and return the result, otherwise it returns" +" null." msgstr "" -"``generate`` 函数是一种实现具有可选值的表达式机制。如果谓词为 true，generate " -"将计算给定表达式并返回结果，否则返回 null。" +"``generate`` 函数是一种实现具有可选值的表达式机制。如果谓词为 true，generate 将计算给定表达式并返回结果，否则返回 " +"null。" #: ../../SpinalHDL/Structuring/parametrization.rst:111 +#, fuzzy msgid "" "This may be used in cases to help parameterize the SpinalHDL hardware " -"description using an elaboration-time conditional expression. Causing HDL " -"constructs to be emitted or not-emitted in the resulting HDL. The generate " -"method can be seen as SpinalHDL syntatic sugar reducing language clutter." +"description using an elaboration-time conditional expression. Causing " +"HDL constructs to be emitted or not-emitted in the resulting HDL. The " +"generate method can be seen as SpinalHDL syntactic sugar reducing " +"language clutter." msgstr "" -"使用实例细化时条件表达式有助于参数化 SpinalHDL 硬件描述。导致 HDL " -"结构在生成的 HDL 中存在或不存在。generate函数可以看作是 SpinalHDL " -"语法糖，减少语言混乱。" +"使用实例细化时条件表达式有助于参数化 SpinalHDL 硬件描述。导致 HDL 结构在生成的 HDL " +"中存在或不存在。generate函数可以看作是 SpinalHDL 语法糖，减少语言混乱。" #: ../../SpinalHDL/Structuring/parametrization.rst:116 +#, fuzzy msgid "" "Project SpinalHDL code referencing ``mySignal`` would need to ensure it " -"handles the possiblity of null gracefully. This is usually not a problem as" -" those parts of the design can also be omitted dependant on the ``flag`` " -"value. Thus the feature of parameterizing this component is demonstrated." +"handles the possibility of null gracefully. This is usually not a " +"problem as those parts of the design can also be omitted dependant on the" +" ``flag`` value. Thus the feature of parameterizing this component is " +"demonstrated." msgstr "" "SpinalHDL 代码中引用 ``mySignal`` 信号将需要确保它优雅地处理 null " -"的可能性。这通常不是问题，因为实际设计中的这些部分也会根据 ``flag`` " -"值省略。从而达到了该组件参数化的目的。" +"的可能性。这通常不是问题，因为实际设计中的这些部分也会根据 ``flag`` 值省略。从而达到了该组件参数化的目的。" #: ../../SpinalHDL/Structuring/parametrization.rst:122 msgid "You can do the same in Bundle." @@ -243,17 +242,17 @@ msgstr "您还可以使用 scala 中的 for 循环：" #: ../../SpinalHDL/Structuring/parametrization.rst:146 msgid "" -"So, you can extends those scala usages at elaboration time as much as you " -"want, including using the whole scala collections (List, Set, Map, ...) to " -"build some data model and then converting them into hardware in a procedural" -" way (ex iterating over those list elements)." +"So, you can extends those scala usages at elaboration time as much as you" +" want, including using the whole scala collections (List, Set, Map, ...) " +"to build some data model and then converting them into hardware in a " +"procedural way (ex iterating over those list elements)." msgstr "" -"因此，您可以在实例细化时根据需要扩展这些 scala 用法，包括使用整个 scala 集合" -"（List、Set、Map...）来构建一些数据模型，然后以程序方式将它们转换为硬件（例如" -"，迭代这些列表中的元素）。" +"因此，您可以在实例细化时根据需要扩展这些 scala 用法，包括使用整个 scala " +"集合（List、Set、Map...）来构建一些数据模型，然后以程序方式将它们转换为硬件（例如，迭代这些列表中的元素）。" #~ msgid "Introduction" #~ msgstr "介绍" #~ msgid "Optionaly generate some hardware" #~ msgstr "可选择生成一些硬件" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po index f9403e6b1a8..9a419e19fc7 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-26 05:04+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/miscelenea/core/core_components.rst:8 msgid "The ``spinal.core`` components" @@ -25,8 +28,8 @@ msgstr "``spinal.core`` 组件" #: ../../SpinalHDL/miscelenea/core/core_components.rst:9 msgid "" -"The core components of the language are described in this document. It is " -"part of the general" +"The core components of the language are described in this document. It is" +" part of the general" msgstr "本文档描述了该语言的核心组件。它涵盖了大部分情况" #: ../../SpinalHDL/miscelenea/core/core_components.rst:13 @@ -37,13 +40,12 @@ msgstr "核心语言组件如下：" msgid "" ":ref:`*Clock domains* `, which " "allow to define and interoperate multiple clock domains within a design" -msgstr ":ref:`*时钟域* " -"`，允许在设计中定义和操作多个时钟域" +msgstr ":ref:`*时钟域* `，允许在设计中定义和操作多个时钟域" #: ../../SpinalHDL/miscelenea/core/core_components.rst:16 msgid "" -"*Memory instantiation*\\ , which permit the automatic instantiation of RAM " -"and ROM memories." +"*Memory instantiation*\\ , which permit the automatic instantiation of " +"RAM and ROM memories." msgstr "*存储器实例化*\\ ，允许自动实例化 RAM 和 ROM 存储器。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:17 @@ -87,20 +89,19 @@ msgstr "时钟域定义" #: ../../SpinalHDL/miscelenea/core/core_components.rst:31 msgid "" -"In *Spinal*\\ , clock and reset signals can be combined to create a **clock " -"domain**. Clock domains could be applied to some area of the design and then" -" all synchronous elements instantiated into this area will then " -"**implicitly** use this clock domain." +"In *Spinal*\\ , clock and reset signals can be combined to create a " +"**clock domain**. Clock domains could be applied to some area of the " +"design and then all synchronous elements instantiated into this area will" +" then **implicitly** use this clock domain." msgstr "" -"在 *Spinal*\\ 中，时钟和复位信号可以组合起来创建**时钟域**。时钟域可以应用于" -"设计的某些区域，该区域的所有实例化的同步元件将**隐式地**使用该时钟域。" +"在 *Spinal*\\ " +"中，时钟和复位信号可以组合起来创建**时钟域**。时钟域可以应用于设计的某些区域，该区域的所有实例化的同步元件将**隐式地**使用该时钟域。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:33 msgid "" "Clock domain application work like a stack, which mean, if you are in a " "given clock domain, you can still apply another clock domain locally." -msgstr "时钟域像堆栈一样工作，这意味着，如果您的逻辑位于给定时钟域中，您仍然可以在其" -"上应用另一个时钟域。" +msgstr "时钟域像堆栈一样工作，这意味着，如果您的逻辑位于给定时钟域中，您仍然可以在其上应用另一个时钟域。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:39 msgid "Clock domain syntax" @@ -126,21 +127,19 @@ msgstr "时钟域的时钟信号" msgid "" "An optional ``reset``\\ signal. If a register which need a reset and his " "clock domain didn't provide one, an error message happen" -msgstr "可选的 ``reset`` " -"复位信号。如果需要重置的寄存器并且其时钟域没有提供重置，则会出现错误提示" +msgstr "可选的 ``reset`` 复位信号。如果需要重置的寄存器并且其时钟域没有提供重置，则会出现错误提示" #: ../../SpinalHDL/miscelenea/core/core_components.rst:50 msgid "" "An optional ``enable`` signal. The goal of this signal is to disable the " -"clock on the whole clock domain without having to manually implement that " -"on each synchronous element." -msgstr "可选的 ``enable`` 使能信号。该信号的目标是禁用整个时钟域上的时钟，而无需在每" -"个同步元件上手动实现。" +"clock on the whole clock domain without having to manually implement " +"that on each synchronous element." +msgstr "可选的 ``enable`` 使能信号。该信号的目标是禁用整个时钟域上的时钟，而无需在每个同步元件上手动实现。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:52 msgid "" -"An applied example to define a specific clock domain within the design is as" -" follows:" +"An applied example to define a specific clock domain within the design is" +" as follows:" msgstr "在设计中定义具有指定属性时钟域的示例如下：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:70 @@ -150,11 +149,11 @@ msgstr "时钟配置" #: ../../SpinalHDL/miscelenea/core/core_components.rst:72 msgid "" "In addition to the constructor parameters given :ref:`here " -"` , the following elements of each clock " -"domain are configurable via a ``ClockDomainConfig`` class :" +"` , the following elements of each " +"clock domain are configurable via a ``ClockDomainConfig`` class :" msgstr "" -"除了 :ref:`此处 ` 给出的构造函数参数之外，" -"每个时钟域的以下元素都可以通过 ``ClockDomainConfig`` 类进行配置：" +"除了 :ref:`此处 ` " +"给出的构造函数参数之外，每个时钟域的以下元素都可以通过 ``ClockDomainConfig`` 类进行配置：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:78 msgid "Property" @@ -195,8 +194,8 @@ msgstr "``clockEnableActiveHigh``" #: ../../SpinalHDL/miscelenea/core/core_components.rst:112 msgid "" -"By default, a ClockDomain is applied to the whole design. The configuration " -"of this one is :" +"By default, a ClockDomain is applied to the whole design. The " +"configuration of this one is :" msgstr "默认情况下，时钟域应用于整个设计。缺省的配置是：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:115 @@ -217,11 +216,10 @@ msgstr "外部时钟" #: ../../SpinalHDL/miscelenea/core/core_components.rst:122 msgid "" -"You can define everywhere a clock domain which is driven by the outside. It " -"will then automatically add clock and reset wire from the top level inputs " -"to all synchronous elements." -msgstr "您可以在任何地方定义由外部驱动的时钟域。然后，它会自动将时钟和复位线从顶层输" -"入添加到所有同步元件。" +"You can define everywhere a clock domain which is driven by the outside. " +"It will then automatically add clock and reset wire from the top level " +"inputs to all synchronous elements." +msgstr "您可以在任何地方定义由外部驱动的时钟域。然后，它会自动将时钟和复位线从顶层输入添加到所有同步元件。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:140 msgid "Cross Clock Domain" @@ -229,21 +227,22 @@ msgstr "跨时钟域设计" #: ../../SpinalHDL/miscelenea/core/core_components.rst:142 msgid "" -"SpinalHDL checks at compile time that there is no unwanted/unspecified cross" -" clock domain signal reads. If you want to read a signal that is emitted by " -"another ``ClockDomain`` area, you should add the ``crossClockDomain`` tag to" -" the destination signal as depicted in the following example:" +"SpinalHDL checks at compile time that there is no unwanted/unspecified " +"cross clock domain signal reads. If you want to read a signal that is " +"emitted by another ``ClockDomain`` area, you should add the " +"``crossClockDomain`` tag to the destination signal as depicted in the " +"following example:" msgstr "" -"SpinalHDL 在编译时检查是否存在不需要的/未指定的跨时钟域信号访问。" -"如果您想读取另一个 ``ClockDomain`` （时钟域）发出的信号，则应给目标信号增加 " -"``crossClockDomain`` 标记，如下例所示：" +"SpinalHDL 在编译时检查是否存在不需要的/未指定的跨时钟域信号访问。如果您想读取另一个 ``ClockDomain`` " +"（时钟域）发出的信号，则应给目标信号增加 ``crossClockDomain`` 标记，如下例所示：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:162 msgid "There are multiple assignment operator :" msgstr "有多种赋值运算符：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:168 -msgid "Symbole" +#, fuzzy +msgid "Symbol" msgstr "符号" #: ../../SpinalHDL/miscelenea/core/core_components.rst:169 @@ -288,15 +287,16 @@ msgid "" msgstr "2 个信号之间的自动连接。通过输入/输出设置推断信号方向" #: ../../SpinalHDL/miscelenea/core/core_components.rst -msgid "Similar behavioural than :=" +#, fuzzy +msgid "Similar behavioral than :=" msgstr "与 := 类似的行为" #: ../../SpinalHDL/miscelenea/core/core_components.rst:197 msgid "" -"SpinalHDL check that bitcount of left and right assignment side match. There" -" is multiple ways to adapt bitcount of BitVector (Bits, UInt, SInt) :" -msgstr "SpinalHDL 检查左右分配端的位数是否匹配。有多种方法可以改变 BitVector " -"（Bits、UInt、SInt）的位数：" +"SpinalHDL check that bitcount of left and right assignment side match. " +"There is multiple ways to adapt bitcount of BitVector (Bits, UInt, SInt) " +":" +msgstr "SpinalHDL 检查左右分配端的位数是否匹配。有多种方法可以改变 BitVector （Bits、UInt、SInt）的位数：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:203 msgid "Resizing ways" @@ -308,8 +308,8 @@ msgstr "x := y.resized" #: ../../SpinalHDL/miscelenea/core/core_components.rst:206 msgid "" -"Assign x wit a resized copy of y, resize value is automatically inferred to " -"match x" +"Assign x wit a resized copy of y, resize value is automatically inferred " +"to match x" msgstr "将 y 改变位宽后的副本赋值给 x，自动推断位宽以匹配 x" #: ../../SpinalHDL/miscelenea/core/core_components.rst:207 @@ -321,11 +321,13 @@ msgid "Assign x with a resized copy of y, size is manually calculated" msgstr "将 y 改变位宽后的副本分配给 x，大小是手动计算的" #: ../../SpinalHDL/miscelenea/core/core_components.rst:211 -msgid "There are 2 cases where spinal automaticly resize things :" +#, fuzzy +msgid "There are 2 cases where spinal automatically resize things :" msgstr "有两种情况会导致spinal自动调整位宽：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:217 -msgid "Assignement" +#, fuzzy +msgid "Assignment" msgstr "赋值" #: ../../SpinalHDL/miscelenea/core/core_components.rst:218 @@ -355,8 +357,7 @@ msgid "myUIntOf_8bit := U(2 -> False default -> true)" msgstr "myUIntOf_8bit := U(2 -> False default -> true)" #: ../../SpinalHDL/miscelenea/core/core_components.rst:224 -msgid "" -"The right part infer a 3 bit UInt, which doesn't match with the left part" +msgid "The right part infer a 3 bit UInt, which doesn't match with the left part" msgstr "右侧部分推断出 3 位 UInt，与左侧部分不匹配" #: ../../SpinalHDL/miscelenea/core/core_components.rst:225 @@ -367,13 +368,12 @@ msgstr "SpinalHDL 将默认值重新应用于丢失的位" msgid "" "As VHDL and Verilog, wire and register can be conditionally assigned by " "using when and switch syntaxes" -msgstr "与 VHDL 和 Verilog 一样，信号线和寄存器可以通过使用 when 和 switch " -"语法进行条件赋值" +msgstr "与 VHDL 和 Verilog 一样，信号线和寄存器可以通过使用 when 和 switch 语法进行条件赋值" #: ../../SpinalHDL/miscelenea/core/core_components.rst:255 msgid "" -"You can also define new signals into a when/switch statement. It's useful if" -" you want to calculate an intermediate value." +"You can also define new signals into a when/switch statement. It's useful" +" if you want to calculate an intermediate value." msgstr "您还可以在when/switch 语句中定义新信号。如果您想计算中间值时，它很有用。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:272 @@ -382,11 +382,10 @@ msgstr "组件/层次结构" #: ../../SpinalHDL/miscelenea/core/core_components.rst:274 msgid "" -"Like in VHDL and Verilog, you can define components that could be used to " -"build a design hierarchy. But unlike them, you don't need to bind them at " -"instantiation." -msgstr "与 VHDL 和 Verilog 一样，您可以定义可用于构建设计层次结构的组件。但与它们不同" -"的是，您不需要在实例化时绑定它们。" +"Like in VHDL and Verilog, you can define components that could be used to" +" build a design hierarchy. But unlike them, you don't need to bind them " +"at instantiation." +msgstr "与 VHDL 和 Verilog 一样，您可以定义可用于构建设计层次结构的组件。但与它们不同的是，您不需要在实例化时绑定它们。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:300 msgid "Syntax to define in/out is the following :" @@ -453,18 +452,17 @@ msgstr "组件可以读取输出/输入端口值" #: ../../SpinalHDL/miscelenea/core/core_components.rst:325 msgid "" "If for some reason, you need to read a signals from far away in the " -"hierarchy (debug, temporal patch) you can do it by using the value returned " -"by some.where.else.theSignal.pull()." +"hierarchy (debug, temporal patch) you can do it by using the value " +"returned by some.where.else.theSignal.pull()." msgstr "" -"如果由于某种原因，您需要从层次结构中的远处读取信号时（调试、临时补丁），" -"您可以使用 some.where.else.theSignal.pull() 返回的值来实现。" +"如果由于某种原因，您需要从层次结构中的远处读取信号时（调试、临时补丁），您可以使用 " +"some.where.else.theSignal.pull() 返回的值来实现。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:330 msgid "" -"Sometime, creating a component to define some logic is overkill and to much " -"verbose. For this kind of cases you can use Area :" -msgstr "有时，创建一个组件来定义某些逻辑是多余的并且过于冗长。对于这种情况，" -"您可以使用 Area 逻辑区 ：" +"Sometime, creating a component to define some logic is overkill and to " +"much verbose. For this kind of cases you can use Area :" +msgstr "有时，创建一个组件来定义某些逻辑是多余的并且过于冗长。对于这种情况，您可以使用 Area 逻辑区 ：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:360 msgid "Function" @@ -478,7 +476,8 @@ msgstr "使用 Scala 函数生成硬件的方式与 VHDL/Verilog 完全不同， #: ../../SpinalHDL/miscelenea/core/core_components.rst:365 msgid "" -"You can instantiate register, combinatorial logic and component inside them." +"You can instantiate register, combinatorial logic and component inside " +"them." msgstr "您可以在其中实例化寄存器、组合逻辑和组件。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:366 @@ -492,9 +491,10 @@ msgid "Everything work by reference, which allow many manipulation." msgstr "一切都按参考工作，这允许许多操作。" #: ../../SpinalHDL/miscelenea/core/core_components.rst +#, fuzzy msgid "" -"For example you can give to a function an bus as argument, then the function" -" can internaly read/write it." +"For example you can give to a function an bus as argument, then the " +"function can internally read/write it." msgstr "例如，您可以为函数提供总线作为参数，然后可以在该函数内部读取/写入它。" #: ../../SpinalHDL/miscelenea/core/core_components.rst @@ -509,8 +509,8 @@ msgstr "RGB信号转灰度信号" #: ../../SpinalHDL/miscelenea/core/core_components.rst:374 msgid "" -"For example if you want to convert a Red/Green/Blue color into a gray one by" -" using coefficient, you can use functions to apply them :" +"For example if you want to convert a Red/Green/Blue color into a gray one" +" by using coefficient, you can use functions to apply them :" msgstr "例如，如果您想使用系数将红/绿/蓝颜色转换为灰色，您可以使用函数来应用它们：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:390 @@ -519,10 +519,9 @@ msgstr "Valid Ready Payload 总线" #: ../../SpinalHDL/miscelenea/core/core_components.rst:392 msgid "" -"For instance if you define a simple Valid Ready Payload bus, you can then " -"define useful function inside it." -msgstr "例如，如果您定义一个简单的 Valid Ready Payload " -"总线，则可以在其中定义有用的函数。" +"For instance if you define a simple Valid Ready Payload bus, you can then" +" define useful function inside it." +msgstr "例如，如果您定义一个简单的 Valid Ready Payload 总线，则可以在其中定义有用的函数。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:417 msgid "VHDL generation" @@ -530,8 +529,8 @@ msgstr "VHDL生成" #: ../../SpinalHDL/miscelenea/core/core_components.rst:419 msgid "" -"There is a small component and a ``main`` that generate the corresponding " -"VHDL." +"There is a small component and a ``main`` that generate the corresponding" +" VHDL." msgstr "有一个小组件和一个生成相应 VHDL 的 ``main`` 。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:448 @@ -541,13 +540,13 @@ msgstr "实例化 VHDL 和 Verilog IP" #: ../../SpinalHDL/miscelenea/core/core_components.rst:450 msgid "" "In some cases, it could be useful to instantiate a VHDL or a Verilog " -"component into a SpinalHDL design. To do that, you need to define BlackBox " -"which is like a Component, but its internal implementation should be " -"provided by a separate VHDL/Verilog file to the simulator/synthesis tool." +"component into a SpinalHDL design. To do that, you need to define " +"BlackBox which is like a Component, but its internal implementation " +"should be provided by a separate VHDL/Verilog file to the " +"simulator/synthesis tool." msgstr "" -"在某些情况下，将 VHDL 或 Verilog 组件实例化到 SpinalHDL " -"设计中可能会很有用。为此，您需要定义 BlackBox，它就像一个组件，" -"但其内部实现应由单独的 VHDL/Verilog 文件提供给仿真/综合工具。" +"在某些情况下，将 VHDL 或 Verilog 组件实例化到 SpinalHDL 设计中可能会很有用。为此，您需要定义 " +"BlackBox，它就像一个组件，但其内部实现应由单独的 VHDL/Verilog 文件提供给仿真/综合工具。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:479 msgid "Utils" @@ -617,3 +616,7 @@ msgstr "Spindle.lib 中提供了更多工具和实用程序" #~ msgid "Synchronous read" #~ msgstr "同步读取" + +#~ msgid "Assignement" +#~ msgstr "赋值" + diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po index dc405369f7b..70c026c7722 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po @@ -1,23 +1,26 @@ + msgid "" msgstr "" -"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-Date:2023-12-" -"01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " -"Language:zh_CNLanguage-Team:zh_CN Plural-" -"Forms:nplurals=1; plural=0;MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" -"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23+0800PO-" -"Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME Language-Team:LANGUAGE MIME-Version:1.0Content-Type:text/plain; " -"charset=UTF-8\n" +"Project-Id-Version: SpinalHDLReport-Msgid-Bugs-To:POT-Creation-" +"Date:2023-12-01 11:48+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-" +"Translator:FULL NAME Language:zh_CNLanguage-Team:zh_CN " +"Plural-Forms:nplurals=1; plural=0;MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"Report-Msgid-Bugs-To: EMAIL@ADDRESSPOT-Creation-Date:2023-12-02 00:23" +"+0800PO-Revision-Date:YEAR-MO-DA HO:MI+ZONELast-Translator:FULL NAME " +"Language-Team:LANGUAGE MIME-Version:1.0Content-" +"Type:text/plain; charset=UTF-8\n" +"POT-Creation-Date: 2024-08-19 09:12+0000\n" "PO-Revision-Date: 2023-12-18 07:38+0000\n" "Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bitGenerated-By:Babel 2.13.1\n" +"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.3\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Generated-By: Babel 2.16.0\n" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:7 msgid "Frequent Errors" @@ -25,8 +28,8 @@ msgstr "常见错误" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:9 msgid "" -"This page will talk about errors which could happen when people are using " -"SpinalHDL." +"This page will talk about errors which could happen when people are using" +" SpinalHDL." msgstr "本页将讨论人们在使用 SpinalHDL 时可能出现的错误。" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:12 @@ -56,17 +59,17 @@ msgstr "**问题解释：**" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:29 msgid "" -"SpinalHDL is not a language, it is an Scala library, which mean, it obey to " -"the same rules than the Scala general purpose programming language. When you" -" run your SpinalHDL hardware description to generate the corresponding " -"VHDL/Verilog RTL, your SpinalHDL hardware description will be executed as a " -"Scala programm, and b will be a ``null`` reference until the programm " -"execution come to that line, and it's why you can't use it before." +"SpinalHDL is not a language, it is an Scala library, which mean, it obey " +"to the same rules than the Scala general purpose programming language. " +"When you run your SpinalHDL hardware description to generate the " +"corresponding VHDL/Verilog RTL, your SpinalHDL hardware description will " +"be executed as a Scala programm, and b will be a ``null`` reference until" +" the programm execution come to that line, and it's why you can't use it " +"before." msgstr "" -"SpinalHDL 不是一种语言，它是一个 Scala 库，这意味着它遵循与 Scala " -"语言相同的通用规则。当您运行 SpinalHDL 硬件描述来生成相应的 VHDL/Verilog RTL " -"时，您的 SpinalHDL 硬件描述将作为 Scala 程序执行，并且执行程序到该行时， b " -"将是一个 ``null`` 空引用，这就是为什么你在这之前不能使用它的原因。" +"SpinalHDL 不是一种语言，它是一个 Scala 库，这意味着它遵循与 Scala 语言相同的通用规则。当您运行 SpinalHDL " +"硬件描述来生成相应的 VHDL/Verilog RTL 时，您的 SpinalHDL 硬件描述将作为 Scala 程序执行，并且执行程序到该行时，" +" b 将是一个 ``null`` 空引用，这就是为什么你在这之前不能使用它的原因。" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:32 msgid "Hierarchy violation" @@ -75,45 +78,46 @@ msgstr "层次违例(Hierarchy violation)" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:34 msgid "" "The SpinalHDL compiler check that all your assignments are legal from an " -"hierarchy perspective. Multiple cases are elaborated in following chapters" -msgstr "SpinalHDL " -"编译器从层次结构的角度检查所有赋值是否合法。后续章节将详细阐述多个案例" +"hierarchy perspective. Multiple cases are elaborated in following " +"chapters" +msgstr "SpinalHDL 编译器从层次结构的角度检查所有赋值是否合法。后续章节将详细阐述多个案例" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:37 msgid "Signal X can't be assigned by Y" msgstr "Signal X can't be assigned by Y" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:82 +#, fuzzy msgid "" "You can only assign input signals of subcomponents, else there is an " -"hierarchy violation. If this issue happend, you probably forgot to specify " -"the X signal's direction." -msgstr "您只能给子组件的输入信号赋值，否则会违反层次结构。如果发生这样的问题，" -"可能是您忘记指定 X 信号的方向。" +"hierarchy violation. If this issue happened, you probably forgot to " +"specify the X signal's direction." +msgstr "您只能给子组件的输入信号赋值，否则会违反层次结构。如果发生这样的问题，可能是您忘记指定 X 信号的方向。" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:85 msgid "Input signal X can't be assigned by Y" msgstr "Input signal X can't be assigned by Y" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:109 +#, fuzzy msgid "" -"You can only assign an input signals from the parent component, else there " -"is an hierarchy violation. If this issue happend, you probably mixed signals" -" direction declaration." -msgstr "您只能从父组件对输入信号赋值，否则会违反层次结构。如果发生此问题，您可能把声" -"明的信号方向弄混了。" +"You can only assign an input signals from the parent component, else " +"there is an hierarchy violation. If this issue happened, you probably " +"mixed signals direction declaration." +msgstr "您只能从父组件对输入信号赋值，否则会违反层次结构。如果发生此问题，您可能把声明的信号方向弄混了。" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:112 msgid "Output signal X can't be assigned by Y" msgstr "Output signal X can't be assigned by Y" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:141 +#, fuzzy msgid "" "You can only assign output signals of a component from the inside of it, " -"else there is an hierarchy violation. If this issue happend, you probably " -"mixed signals direction declaration." -msgstr "您只能从组件内部赋值组件的输出信号，否则会违反层次结构。如果发生此问题，您可" -"能把声明信号的方向弄混了。" +"else there is an hierarchy violation. If this issue happened, you " +"probably mixed signals direction declaration." +msgstr "您只能从组件内部赋值组件的输出信号，否则会违反层次结构。如果发生此问题，您可能把声明信号的方向弄混了。" #~ msgid "Introduction" #~ msgstr "介绍" +