From 2cd19c89b13a0dee4441a6f1fb71eb434946ddf6 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Mon, 12 Feb 2024 12:47:31 +0100
Subject: [PATCH] Revert unwanted push IBusDBusCachedTightlyCoupledRam

---
 src/main/scala/vexriscv/VexRiscvBmbGenerator.scala | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
index e42d82be..50cd15b8 100644
--- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
+++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
@@ -120,10 +120,6 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
       case _ =>
     }
 
-    config.plugins += new IBusDBusCachedTightlyCoupledRam(
-      mapping = SizeMapping(0x20000000, 0x1000)
-    )
-
     val cpu = new VexRiscv(config)
     def doExport(value : => Any, postfix : String) = {
       sexport(Handle(value).setCompositeName(VexRiscvBmbGenerator.this, postfix))