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Copy pathHeartrate_Varaibility_hw.tcl~
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Heartrate_Varaibility_hw.tcl~
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# TCL File Generated by Component Editor 18.1
# Tue Jan 11 08:08:53 CET 2022
# DO NOT MODIFY
#
# Heartrate_Variability "Heartrate" v1.0
# 2022.01.11.08:08:53
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module Heartrate_Variability
#
set_module_property DESCRIPTION ""
set_module_property NAME Heartrate_Variability
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME Heartrate
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL DE2_115
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file DE2_115.vhd VHDL PATH hrv_source/DE2_115.vhd TOP_LEVEL_FILE
add_fileset_file DE2_115.vhd.bak OTHER PATH hrv_source/DE2_115.vhd.bak
add_fileset_file HRV.vhd.bak OTHER PATH hrv_source/HRV.vhd.bak
add_fileset_file HRV_architecture.vhd.bak OTHER PATH hrv_source/HRV_architecture.vhd.bak
add_fileset_file HRV_buffer.vhd VHDL PATH hrv_source/HRV_buffer.vhd
add_fileset_file HRV_buffer.vhd.bak OTHER PATH hrv_source/HRV_buffer.vhd.bak
add_fileset_file HRV_calculator.vhd VHDL PATH hrv_source/HRV_calculator.vhd
add_fileset_file HRV_calculator.vhd.bak OTHER PATH hrv_source/HRV_calculator.vhd.bak
add_fileset_file HRV_calculator_architecture.vhd VHDL PATH hrv_source/HRV_calculator_architecture.vhd
add_fileset_file HRV_calculator_architecture.vhd.bak OTHER PATH hrv_source/HRV_calculator_architecture.vhd.bak
add_fileset_file HRV_calculator_test.vhd VHDL PATH hrv_source/HRV_calculator_test.vhd
add_fileset_file HRV_calculator_test_architecture.vhd VHDL PATH hrv_source/HRV_calculator_test_architecture.vhd
add_fileset_file HRV_calculator_test_architecture.vhd.bak OTHER PATH hrv_source/HRV_calculator_test_architecture.vhd.bak
add_fileset_file RR_calculator.vhd VHDL PATH hrv_source/RR_calculator.vhd
add_fileset_file RR_calculator.vhd.bak OTHER PATH hrv_source/RR_calculator.vhd.bak
add_fileset_file RR_calculator_architecture.vhd VHDL PATH hrv_source/RR_calculator_architecture.vhd
add_fileset_file RR_calculator_architecture.vhd.bak OTHER PATH hrv_source/RR_calculator_architecture.vhd.bak
add_fileset_file RR_timer.vhd VHDL PATH hrv_source/RR_timer.vhd
add_fileset_file RR_timer.vhd.bak OTHER PATH hrv_source/RR_timer.vhd.bak
add_fileset_file RR_timer_architecture.vhd VHDL PATH hrv_source/RR_timer_architecture.vhd
add_fileset_file RR_timer_architecture.vhd.bak OTHER PATH hrv_source/RR_timer_architecture.vhd.bak
add_fileset_file SDRR2_calculator.vhd VHDL PATH hrv_source/SDRR2_calculator.vhd
add_fileset_file SDRR2_calculator_architecture.vhd VHDL PATH hrv_source/SDRR2_calculator_architecture.vhd
add_fileset_file SDRR2_calculator_architecture.vhd.bak OTHER PATH hrv_source/SDRR2_calculator_architecture.vhd.bak
add_fileset_file SDRR_calculator.vhd VHDL PATH hrv_source/SDRR_calculator.vhd
add_fileset_file SDRR_calculator.vhd.bak OTHER PATH hrv_source/SDRR_calculator.vhd.bak
add_fileset_file SDRR_calculator_architecture.vhd VHDL PATH hrv_source/SDRR_calculator_architecture.vhd
add_fileset_file SDRR_calculator_architecture.vhd.bak OTHER PATH hrv_source/SDRR_calculator_architecture.vhd.bak
add_fileset_file clock_divider.vhd VHDL PATH hrv_source/clock_divider.vhd
add_fileset_file clock_divider.vhd.bak OTHER PATH hrv_source/clock_divider.vhd.bak
add_fileset_file i2c_controller.vhd VHDL PATH hrv_source/i2c_controller.vhd
add_fileset_file i2c_controller.vhd.bak OTHER PATH hrv_source/i2c_controller.vhd.bak
add_fileset_file i2c_controller_architecture.vhd VHDL PATH hrv_source/i2c_controller_architecture.vhd
add_fileset_file i2c_controller_architecture.vhd.bak OTHER PATH hrv_source/i2c_controller_architecture.vhd.bak
add_fileset_file i2c_master.vhd VHDL PATH hrv_source/i2c_master.vhd
add_fileset_file moving_average_calculator.vhd VHDL PATH hrv_source/moving_average_calculator.vhd
add_fileset_file moving_average_calculator.vhd.bak OTHER PATH hrv_source/moving_average_calculator.vhd.bak
add_fileset_file moving_average_calculator_architecture.vhd VHDL PATH hrv_source/moving_average_calculator_architecture.vhd
add_fileset_file moving_average_calculator_architecture.vhd.bak OTHER PATH hrv_source/moving_average_calculator_architecture.vhd.bak
add_fileset_file peak_detector.vhd VHDL PATH hrv_source/peak_detector.vhd
add_fileset_file peak_detector.vhd.bak OTHER PATH hrv_source/peak_detector.vhd.bak
add_fileset_file peak_detector_architecture.vhd VHDL PATH hrv_source/peak_detector_architecture.vhd
add_fileset_file peak_detector_architecture.vhd.bak OTHER PATH hrv_source/peak_detector_architecture.vhd.bak
add_fileset_file peak_time.vhd.bak OTHER PATH hrv_source/peak_time.vhd.bak
add_fileset_file peak_time_architecture.vhd.bak OTHER PATH hrv_source/peak_time_architecture.vhd.bak
add_fileset_file rom.vhd VHDL PATH hrv_source/rom.vhd
add_fileset_file seg7dec.vhd VHDL PATH hrv_source/seg7dec.vhd
add_fileset_file seg7dec.vhd.bak OTHER PATH hrv_source/seg7dec.vhd.bak
add_fileset_file seg7dec_architecture.vhd VHDL PATH hrv_source/seg7dec_architecture.vhd
add_fileset_file seg7dec_architecture.vhd.bak OTHER PATH hrv_source/seg7dec_architecture.vhd.bak
add_fileset_file signal_filter.vhd.bak OTHER PATH hrv_source/signal_filter.vhd.bak
add_fileset_file signal_filter_architecture.vhd.bak OTHER PATH hrv_source/signal_filter_architecture.vhd.bak
add_fileset_file signal_generator.vhd VHDL PATH hrv_source/signal_generator.vhd
add_fileset_file signal_generator.vhd.bak OTHER PATH hrv_source/signal_generator.vhd.bak
add_fileset_file signal_smoother.vhd VHDL PATH hrv_source/signal_smoother.vhd
add_fileset_file signal_smoother.vhd.bak OTHER PATH hrv_source/signal_smoother.vhd.bak
add_fileset_file signal_smoother_architecture.vhd VHDL PATH hrv_source/signal_smoother_architecture.vhd
add_fileset_file signal_smoother_architecture.vhd.bak OTHER PATH hrv_source/signal_smoother_architecture.vhd.bak
add_fileset_file square_root_calculator.vhd VHDL PATH hrv_source/square_root_calculator.vhd
add_fileset_file synchronizer.vhd VHDL PATH hrv_source/synchronizer.vhd
add_fileset_file synchronizer_architecture.vhd VHDL PATH hrv_source/synchronizer_architecture.vhd
add_fileset_file synchronizer_architecture.vhd.bak OTHER PATH hrv_source/synchronizer_architecture.vhd.bak
add_fileset SIM_VHDL SIM_VHDL "" ""
set_fileset_property SIM_VHDL TOP_LEVEL DE2_115
set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file avalon_bus.vhd VHDL PATH avalon_bus.vhd
add_fileset_file HRV.vhd.bak OTHER PATH hrv_source/HRV.vhd.bak
add_fileset_file HRV_architecture.vhd.bak OTHER PATH hrv_source/HRV_architecture.vhd.bak
add_fileset_file HRV_calculator.vhd VHDL PATH hrv_source/HRV_calculator.vhd
add_fileset_file HRV_calculator.vhd.bak OTHER PATH hrv_source/HRV_calculator.vhd.bak
add_fileset_file HRV_calculator_architecture.vhd VHDL PATH hrv_source/HRV_calculator_architecture.vhd
add_fileset_file HRV_calculator_architecture.vhd.bak OTHER PATH hrv_source/HRV_calculator_architecture.vhd.bak
add_fileset_file HRV_calculator_test.vhd VHDL PATH hrv_source/HRV_calculator_test.vhd
add_fileset_file HRV_calculator_test_architecture.vhd VHDL PATH hrv_source/HRV_calculator_test_architecture.vhd
add_fileset_file HRV_calculator_test_architecture.vhd.bak OTHER PATH hrv_source/HRV_calculator_test_architecture.vhd.bak
add_fileset_file RR_calculator.vhd VHDL PATH hrv_source/RR_calculator.vhd
add_fileset_file RR_calculator.vhd.bak OTHER PATH hrv_source/RR_calculator.vhd.bak
add_fileset_file RR_calculator_architecture.vhd VHDL PATH hrv_source/RR_calculator_architecture.vhd
add_fileset_file RR_calculator_architecture.vhd.bak OTHER PATH hrv_source/RR_calculator_architecture.vhd.bak
add_fileset_file RR_timer.vhd VHDL PATH hrv_source/RR_timer.vhd
add_fileset_file RR_timer.vhd.bak OTHER PATH hrv_source/RR_timer.vhd.bak
add_fileset_file RR_timer_architecture.vhd VHDL PATH hrv_source/RR_timer_architecture.vhd
add_fileset_file RR_timer_architecture.vhd.bak OTHER PATH hrv_source/RR_timer_architecture.vhd.bak
add_fileset_file SDRR2_calculator.vhd VHDL PATH hrv_source/SDRR2_calculator.vhd
add_fileset_file SDRR2_calculator_architecture.vhd VHDL PATH hrv_source/SDRR2_calculator_architecture.vhd
add_fileset_file SDRR2_calculator_architecture.vhd.bak OTHER PATH hrv_source/SDRR2_calculator_architecture.vhd.bak
add_fileset_file SDRR_calculator.vhd VHDL PATH hrv_source/SDRR_calculator.vhd
add_fileset_file SDRR_calculator.vhd.bak OTHER PATH hrv_source/SDRR_calculator.vhd.bak
add_fileset_file SDRR_calculator_architecture.vhd VHDL PATH hrv_source/SDRR_calculator_architecture.vhd
add_fileset_file SDRR_calculator_architecture.vhd.bak OTHER PATH hrv_source/SDRR_calculator_architecture.vhd.bak
add_fileset_file clock_divider.vhd VHDL PATH hrv_source/clock_divider.vhd
add_fileset_file clock_divider.vhd.bak OTHER PATH hrv_source/clock_divider.vhd.bak
add_fileset_file moving_average_calculator.vhd VHDL PATH hrv_source/moving_average_calculator.vhd
add_fileset_file moving_average_calculator.vhd.bak OTHER PATH hrv_source/moving_average_calculator.vhd.bak
add_fileset_file moving_average_calculator_architecture.vhd VHDL PATH hrv_source/moving_average_calculator_architecture.vhd
add_fileset_file moving_average_calculator_architecture.vhd.bak OTHER PATH hrv_source/moving_average_calculator_architecture.vhd.bak
add_fileset_file peak_detector.vhd VHDL PATH hrv_source/peak_detector.vhd
add_fileset_file peak_detector.vhd.bak OTHER PATH hrv_source/peak_detector.vhd.bak
add_fileset_file peak_detector_architecture.vhd VHDL PATH hrv_source/peak_detector_architecture.vhd
add_fileset_file peak_detector_architecture.vhd.bak OTHER PATH hrv_source/peak_detector_architecture.vhd.bak
add_fileset_file peak_time.vhd.bak OTHER PATH hrv_source/peak_time.vhd.bak
add_fileset_file peak_time_architecture.vhd.bak OTHER PATH hrv_source/peak_time_architecture.vhd.bak
add_fileset_file rom.vhd VHDL PATH hrv_source/rom.vhd
add_fileset_file signal_filter.vhd.bak OTHER PATH hrv_source/signal_filter.vhd.bak
add_fileset_file signal_filter_architecture.vhd.bak OTHER PATH hrv_source/signal_filter_architecture.vhd.bak
add_fileset_file signal_generator.vhd VHDL PATH hrv_source/signal_generator.vhd
add_fileset_file signal_generator.vhd.bak OTHER PATH hrv_source/signal_generator.vhd.bak
add_fileset_file signal_smoother.vhd VHDL PATH hrv_source/signal_smoother.vhd
add_fileset_file signal_smoother.vhd.bak OTHER PATH hrv_source/signal_smoother.vhd.bak
add_fileset_file signal_smoother_architecture.vhd VHDL PATH hrv_source/signal_smoother_architecture.vhd
add_fileset_file signal_smoother_architecture.vhd.bak OTHER PATH hrv_source/signal_smoother_architecture.vhd.bak
add_fileset_file square_root_calculator.vhd VHDL PATH hrv_source/square_root_calculator.vhd
add_fileset_file synchronizer.vhd VHDL PATH hrv_source/synchronizer.vhd
add_fileset_file synchronizer_architecture.vhd VHDL PATH hrv_source/synchronizer_architecture.vhd
add_fileset_file synchronizer_architecture.vhd.bak OTHER PATH hrv_source/synchronizer_architecture.vhd.bak
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 50000000
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock csi_clock_clk clk Input 1
#
# connection point reset_reset
#
add_interface reset_reset reset end
set_interface_property reset_reset associatedClock clock
set_interface_property reset_reset synchronousEdges DEASSERT
set_interface_property reset_reset ENABLED true
set_interface_property reset_reset EXPORT_OF ""
set_interface_property reset_reset PORT_NAME_MAP ""
set_interface_property reset_reset CMSIS_SVD_VARIABLES ""
set_interface_property reset_reset SVD_ADDRESS_GROUP ""
add_interface_port reset_reset csi_reset_reset reset Input 1
#
# connection point stress_level
#
add_interface stress_level avalon end
set_interface_property stress_level addressUnits WORDS
set_interface_property stress_level associatedClock clock
set_interface_property stress_level associatedReset reset_reset
set_interface_property stress_level bitsPerSymbol 8
set_interface_property stress_level burstOnBurstBoundariesOnly false
set_interface_property stress_level burstcountUnits WORDS
set_interface_property stress_level explicitAddressSpan 0
set_interface_property stress_level holdTime 0
set_interface_property stress_level linewrapBursts false
set_interface_property stress_level maximumPendingReadTransactions 0
set_interface_property stress_level maximumPendingWriteTransactions 0
set_interface_property stress_level readLatency 0
set_interface_property stress_level readWaitTime 1
set_interface_property stress_level setupTime 0
set_interface_property stress_level timingUnits Cycles
set_interface_property stress_level writeWaitTime 0
set_interface_property stress_level ENABLED true
set_interface_property stress_level EXPORT_OF ""
set_interface_property stress_level PORT_NAME_MAP ""
set_interface_property stress_level CMSIS_SVD_VARIABLES ""
set_interface_property stress_level SVD_ADDRESS_GROUP ""
add_interface_port stress_level avs_stress_level_address address Input 2
add_interface_port stress_level avs_stress_level_readdata readdata Output 16
add_interface_port stress_level avs_stress_level_write write Input 1
add_interface_port stress_level avs_stress_level_writedata writedata Input 16
set_interface_assignment stress_level embeddedsw.configuration.isFlash 0
set_interface_assignment stress_level embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment stress_level embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment stress_level embeddedsw.configuration.isPrintableDevice 0
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock ""
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end LEDR readdata Output 16
add_interface_port conduit_end LEDG writeresponsevalid_n Output 1
add_interface_port conduit_end HEX0 readdata Output 7
add_interface_port conduit_end HEX1 readdata Output 7
add_interface_port conduit_end HEX2 readdata Output 7
#
# connection point I2C
#
add_interface I2C conduit end
set_interface_property I2C associatedClock clock
set_interface_property I2C associatedReset ""
set_interface_property I2C ENABLED true
set_interface_property I2C EXPORT_OF ""
set_interface_property I2C PORT_NAME_MAP ""
set_interface_property I2C CMSIS_SVD_VARIABLES ""
set_interface_property I2C SVD_ADDRESS_GROUP ""
add_interface_port I2C I2C_GPIO export Bidir 2
#
# connection point HEX0
#
add_interface HEX0 conduit end
set_interface_property HEX0 associatedClock clock
set_interface_property HEX0 associatedReset ""
set_interface_property HEX0 ENABLED true
set_interface_property HEX0 EXPORT_OF ""
set_interface_property HEX0 PORT_NAME_MAP ""
set_interface_property HEX0 CMSIS_SVD_VARIABLES ""
set_interface_property HEX0 SVD_ADDRESS_GROUP ""
add_interface_port HEX0 HEX0_signal readdata Output 7
#
# connection point HEX1
#
add_interface HEX1 conduit end
set_interface_property HEX1 associatedClock clock
set_interface_property HEX1 associatedReset ""
set_interface_property HEX1 ENABLED true
set_interface_property HEX1 EXPORT_OF ""
set_interface_property HEX1 PORT_NAME_MAP ""
set_interface_property HEX1 CMSIS_SVD_VARIABLES ""
set_interface_property HEX1 SVD_ADDRESS_GROUP ""
add_interface_port HEX1 HEX1_signal readdata Output 7
#
# connection point HEX2
#
add_interface HEX2 conduit end
set_interface_property HEX2 associatedClock clock
set_interface_property HEX2 associatedReset ""
set_interface_property HEX2 ENABLED true
set_interface_property HEX2 EXPORT_OF ""
set_interface_property HEX2 PORT_NAME_MAP ""
set_interface_property HEX2 CMSIS_SVD_VARIABLES ""
set_interface_property HEX2 SVD_ADDRESS_GROUP ""
add_interface_port HEX2 HEX2_signal readdata Output 7
#
# connection point LEDG
#
add_interface LEDG conduit end
set_interface_property LEDG associatedClock clock
set_interface_property LEDG associatedReset ""
set_interface_property LEDG ENABLED true
set_interface_property LEDG EXPORT_OF ""
set_interface_property LEDG PORT_NAME_MAP ""
set_interface_property LEDG CMSIS_SVD_VARIABLES ""
set_interface_property LEDG SVD_ADDRESS_GROUP ""
add_interface_port LEDG LEDG_signal writeresponsevalid_n Output 1
#
# connection point LEDR
#
add_interface LEDR conduit end
set_interface_property LEDR associatedClock clock
set_interface_property LEDR associatedReset reset_reset
set_interface_property LEDR ENABLED true
set_interface_property LEDR EXPORT_OF ""
set_interface_property LEDR PORT_NAME_MAP ""
set_interface_property LEDR CMSIS_SVD_VARIABLES ""
set_interface_property LEDR SVD_ADDRESS_GROUP ""