Merge pull request #367 from The-OpenROAD-Project/merge_openroad

Merge openroad

.clang-format

@@ -0,0 +1,32 @@
+---
+Language:        Cpp
+BasedOnStyle:  Google
+
+AlignConsecutiveAssignments: true
+AlignConsecutiveDeclarations: true
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortFunctionsOnASingleLine: InlineOnly
+AllowShortIfStatementsOnASingleLine: false
+AllowShortLoopsOnASingleLine: false
+BinPackArguments: false
+BinPackParameters: false
+BraceWrapping:   
+  AfterClass:            true
+  AfterControlStatement: false
+  AfterEnum:             true
+  AfterFunction:         true
+  AfterNamespace:        false
+  AfterObjCDeclaration:  false
+  AfterStruct:           true
+  AfterUnion:            true
+  AfterExternBlock:      false
+  BeforeCatch:           false
+  BeforeElse:            false
+  IndentBraces:          false
+  SplitEmptyFunction:    true
+  SplitEmptyRecord:      true
+  SplitEmptyNamespace:   true
+BreakBeforeBinaryOperators: All
+BreakBeforeBraces: Custom
+DerivePointerAlignment: false
+SpaceAfterCStyleCast: true

CMakeLists.txt

@@ -35,7 +35,7 @@ if(CMAKE_VERSION VERSION_GREATER_EQUAL 3.13)
 cmake_policy(SET CMP0077 NEW)
 endif()
 
-project(OpenROAD VERSION 1.1.0
+project(OpenROAD VERSION 0.9.0
   LANGUAGES CXX
 )
 

Dockerfile

@@ -3,7 +3,7 @@ LABEL maintainer="Abdelrahman Hosny <abdelrahman_hosny@brown.edu>"
 
 # Install dev and runtime dependencies
 RUN yum group install -y "Development Tools" \
-    && yum install -y https://centos7.iuscommunity.org/ius-release.rpm \
+    && yum install -y https://repo.ius.io/ius-release-el7.rpm \
     && yum install -y centos-release-scl \
     && yum install -y wget devtoolset-8 \
     devtoolset-8-libatomic-devel tcl-devel tcl tk libstdc++ tk-devel pcre-devel \
@@ -28,8 +28,8 @@ RUN wget https://dl.fedoraproject.org/pub/epel/epel-release-latest-7.noarch.rpm
     yum install -y epel-release-latest-7.noarch.rpm && rm -rf epel-release-latest-7.noarch.rpm  \
     && yum clean -y all
 
-# Install git from epel
-RUN yum -y remove git && yum install -y git2u
+# Install any git version > 2.6.5
+RUN yum remove -y git* && yum install -y git224
 
 # Install SWIG
 RUN yum remove -y swig \

README.md

@@ -226,29 +226,41 @@ set_wire_rc [-layer layer_name]
 	    [-capacitance cap]
 	    [-corner corner_name]
 ```
+
 The `set_wire_rc` command sets the resistance and capacitance used to
 estimate delay of routing wires.  Use `-layer` or `-resistance` and
 `-capacitance`.  If `-layer` is used, the LEF technology resistance
-and area/edge capacitance values for the layer are used.  The units
-for `-resistance` and `-capacitance` are from the first liberty file
-read, resistance_unit/distance_unit and liberty
-capacitance_unit/distance_unit. RC parasitics are added based on
-placed component pin locations. If there are no component locations no
-parasitics are added. The resistance and capacitance are per distance
-unit of a routing wire. Use the `set_units` command to check units or
-`set_cmd_units` to change units. They should represent "average"
-routing layer resistance and capacitance. If the set_wire_rc command
-is not called before resizing, the default_wireload model specified in
-the first liberty file or with the SDC set_wire_load command is used
-to make parasitics.
+and area/edge capacitance values for the layer are used for a minimum
+width wire on the layer.  The resistance and capacitance values per
+length of wire, not per square or per square micron.  The units for
+`-resistance` and `-capacitance` are from the first liberty file read,
+resistance_unit/distance_unit (typically kohms/micron) and liberty
+capacitance_unit/distance_unit (typically pf/micron or ff/micron).  If
+no distance units are not specied in the liberty file microns are
+used.
+
+```
+estimate_parasitics -placement
+```
+
+Estimate RC parasitics based on placed component pin locations. If
+there are no component locations no parasitics are added. The
+resistance and capacitance are per distance unit of a routing
+wire. Use the `set_units` command to check units or `set_cmd_units` to
+change units. They should represent "average" routing layer resistance
+and capacitance. If the set_wire_rc command is not called before
+resizing, the default_wireload model specified in the first liberty
+file or with the SDC set_wire_load command is used to make parasitics.
 
 ```
 set_dont_use lib_cells
 ```
 
-The `set_dont_use` command removes library cells from consideration by the
-resizer. `lib_cells` is a list of cells returned by `get_lib_cells` or
-a list of cell names (wildcards allowed).
+The `set_dont_use` command removes library cells from consideration by
+the resizer. `lib_cells` is a list of cells returned by
+`get_lib_cells` or a list of cell names (wildcards allowed). For
+example, `DLY*` says do not use cells with names that begin with `DLY`
+in all libraries.
 
 ```
 buffer_ports [-inputs]
@@ -260,9 +272,24 @@ its loads.  The `buffer_ports -outputs` adds a buffer between the port
 driver and the output port. If  The default behavior is
 `-inputs` and `-outputs` if neither is specified.
 
+```
+repair_design [-max_wire_length max_length]
+              -buffer_cell buffer_cell
+```
+
+The `repair_design` inserts buffers on nets to repair max slew, max
+capacitance, max fanout violations, and on long wires to reduce RC
+delay in the wire. Use `-max_wire_length` to specify the maximum lenth
+of wires.  The resistance/capacitance values in `set_wire_rc` are used
+to find the wire delays.
+
+Use the `set_max_fanout` SDC command to set the maximum fanout for the design.
+```
+set_max_fanout <fanout> [current_design]
+```
+
 ```
 resize [-libraries resize_libraries]
-       [-dont_use cells]
        [-max_utilization util]
 ```
 The `resize` command resizes gates to normalize slews.
@@ -272,40 +299,19 @@ resizing. `resize_libraries` defaults to all of the liberty libraries
 that have been read. Some designs have multiple libraries with
 different transistor thresholds (Vt) and are used to trade off power
 and speed. Chosing a low Vt library uses more power but results in a
-faster design after the resizing step. Use the `-dont_use` option to
-specify a list of patterns of cells to not use or the value returned
-by `get_lib_cells`. For example, `DLY*` says do not use cells with
-names that begin with `DLY` in all libraries.
-
-```
-repair_max_cap -buffer_cell buffer_cell
-               [-max_utilization util]
-repair_max_slew -buffer_cell buffer_cell
-                [-max_utilization util]
-```
-The `repair_max_cap` and `repair_max_slew` commands repair nets with
-maximum capacitance or slew violations by inserting buffers in the
-net.
+faster design after the resizing step.
 
 ```
-repair_max_fanout -max_fanout fanout
-                  -buffer_cell buffer_cell
-                  [-max_utilization util]
-```
-The `repair_max_fanout` command repairs nets with a fanout greater
-than `fanout` by inserting buffers between the driver and the loads.
-Buffers are located at the center of each group of loads.
-
-```
-repair_tie_fanout [-max_fanout fanout]
+repair_tie_fanout [-separation dist]
                   [-verbose]
                   lib_port
 ```
-The `repair_tie_fanout` command repairs tie high/low nets with fanout
-greater than `fanout` by cloning the tie high/low driver.
-`lib_port` is the tie high/low port, which can be a library/cell/port
-name or object returned by `get_lib_pins`. Clones are located at the
-center of each group of loads.
+
+The `repair_tie_fanout` command connects each tie high/low load to a
+copy of the tie high/low cell.  `lib_port` is the tie high/low port,
+which can be a library/cell/port name or object returned by
+`get_lib_pins`. The tie high/low instance is separaated from the load
+by `dist` (in liberty units, typically microns).
 
 ```
 repair_hold_violations -buffer_cell buffer_cell
@@ -339,13 +345,12 @@ set_wire_rc -layer metal2
 
 set buffer_cell BUF_X4
 set_dont_use {CLKBUF_* AOI211_X1 OAI211_X1}
-resize
+
 buffer_ports -buffer_cell $buffer_cell
-repair_max_cap -buffer_cell $buffer_cell
-repair_max_slew -buffer_cell $buffer_cell
-repair_max_fanout -max_fanout 100 -buffer_cell $buffer_cell
-repair_tie_fanout -max_fanout 100 LOGIC0_X1/Z
-repair_tie_fanout -max_fanout 100 LOGIC1_X1/Z
+repair_design -max_wire_length 100 -buffer_cell $buffer_cell
+resize
+repair_tie_fanout LOGIC0_X1/Z
+repair_tie_fanout LOGIC1_X1/Z
 repair_hold_violations -buffer_cell $buffer_cell
 resize
 ```
@@ -482,28 +487,28 @@ clock_tree_synthesis -buf_list <list_of_buffers> \
                      [-wire_unit <wire_unit>] \
                      [-clk_nets <list_of_clk_nets>] \
                      [-out_path <lut_path>] \
-                     [-only_characterization <enable>]
+                     [-characterization_only]
 ```
 
-- ```buf_list``` (mandatory) are the master cells (buffers) that will be considered when making the wire segments.
-- ``sqr_cap`` (mandatory) is the capacitance (in picofarad) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments. 
-- ``sqr_res`` (mandatory) is the resistance (in ohm) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments. 
-- ``root_buffer`` (optional) is the master cell of the buffer that serves as root for the clock tree. 
-If this parameter is omitted, the first master cell from ```buf_list``` is taken.
-- ``max_slew`` (optional) is the max slew value (in seconds) that the characterization will test. 
+- ``-buf_list`` are the master cells (buffers) that will be considered when making the wire segments.
+- ``-sqr_cap`` is the capacitance (in picofarad) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments. 
+- ``-sqr_res`` is the resistance (in ohm) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments. 
+- ``-root_buffer`` is the master cell of the buffer that serves as root for the clock tree. 
+If this parameter is omitted, the first master cell from ``-buf_list`` is taken.
+- ``-max_slew`` is the max slew value (in seconds) that the characterization will test. 
 If this parameter is omitted, the code tries to obtain the value from the liberty file.
-- ``max_cap`` (optional) is the max capacitance value (in farad) that the characterization will test. 
+- ``-max_cap`` is the max capacitance value (in farad) that the characterization will test. 
 If this parameter is omitted, the code tries to obtain the value from the liberty file.
-- ``slew_inter`` (optional) is the time value (in seconds) that the characterization will consider for results. 
+- ``-slew_inter`` is the time value (in seconds) that the characterization will consider for results. 
 If this parameter is omitted, the code gets the default value (5.0e-12). Be careful that this value can be quite low for bigger technologies (>65nm).
-- ``cap_inter`` (optional) is the capacitance value (in farad) that the characterization will consider for results. 
+- ``-cap_inter`` is the capacitance value (in farad) that the characterization will consider for results. 
 If this parameter is omitted, the code gets the default value (5.0e-15). Be careful that this value can be quite low for bigger technologies (>65nm).
-- ``wire_unit`` (optional) is the minimum unit distance between buffers for a specific wire. 
-If this parameter is omitted, the code gets the value from ten times the height of ``root_buffer``.
-- ``clk_nets`` (optional) is a string containing the names of the clock roots. 
+- ``-wire_unit`` is the minimum unit distance between buffers for a specific wire. 
+If this parameter is omitted, the code gets the value from ten times the height of ``-root_buffer``.
+- ``-clk_nets`` is a string containing the names of the clock roots. 
 If this parameter is omitted, TritonCTS looks for the clock roots automatically.
-- ``out_path`` (optional) is the output path (full) that the lut.txt and sol_list.txt files will be saved. This is used to load an existing characterization, without creating one from scratch.
-- ``only_characterization`` (optional), if true, makes so that the code exits after running the characterization.
+- ``-out_path`` is the output path (full) that the lut.txt and sol_list.txt files will be saved. This is used to load an existing characterization, without creating one from scratch.
+- ``-only_characterization`` is a flag that, when specified, makes so that only the library characterization step is run and no clock tree is inserted in the design.
 
 Instead of creating a characterization, you can use use the following parameters to load a characterization file.
 
@@ -514,16 +519,40 @@ clock_tree_synthesis -lut_file <lut_file> \
                      [-wire_unit <wire_unit>] \
                      [-clk_nets <list_of_clk_nets>] 
 ```
-- ```lut_file``` (mandatory) is the file containing delay, power and other metrics for each segment.
-- ``sol_list`` (mandatory) is the file containing the information on the topology of each segment (wirelengths and buffer masters).
-- ``sqr_res`` (mandatory) is the resistance (in ohm) per database units to be used in the wire segments. 
-- ``root_buffer`` (mandatory) is the master cell of the buffer that serves as root for the clock tree. 
-If this parameter is omitted, you can use the ```buf_list``` argument, using the first master cell. If both arguments are omitted, an error is raised.
-- ``wire_unit`` (optional) is the minimum unit distance between buffers for a specific wire, based on your ```lut_file```. 
-If this parameter is omitted, the code gets the value from the header of the ```lut_file```. For the old technology characterization, described [here](https://github.com/The-OpenROAD-Project/TritonCTS/blob/master/doc/Technology_characterization.md), this argument is mandatory, and omitting it raises an error.
-- ``clk_nets`` (optional) is a string containing the names of the clock roots. 
+
+- ``-lut_file`` (mandatory) is the file containing delay, power and other metrics for each segment.
+- ``-sol_list`` (mandatory) is the file containing the information on the topology of each segment (wirelengths and buffer masters).
+- ``-sqr_res`` (mandatory) is the resistance (in ohm) per database units to be used in the wire segments. 
+- ``-root_buffer`` (mandatory) is the master cell of the buffer that serves as root for the clock tree. 
+If this parameter is omitted, you can use the ``-buf_list`` argument, using the first master cell. If both arguments are omitted, an error is raised.
+- ``-wire_unit`` (optional) is the minimum unit distance between buffers for a specific wire, based on your ``-lut_file``. 
+If this parameter is omitted, the code gets the value from the header of the ``-lut_file``. For the old technology characterization, described [here](https://github.com/The-OpenROAD-Project/TritonCTS/blob/master/doc/Technology_characterization.md), this argument is mandatory, and omitting it raises an error.
+- ``-clk_nets`` (optional) is a string containing the names of the clock roots. 
 If this parameter is omitted, TritonCTS looks for the clock roots automatically.
 
+Another command available from TritonCTS is ``report_cts``. It is used to extract metrics after a successful ``clock_tree_synthesis`` run. These are: Number of Clock Roots, Number of Buffers Inserted, Number of Clock Subnets, and Number of Sinks.
+
+```
+read_lef "mylef.lef"
+read_liberty "myliberty.lib"
+read_def "mydef.def"
+read_verilog "myverilog.v"
+read_sdc "mysdc.sdc"
+
+report_checks
+
+clock_tree_synthesis -lut_file "lut.txt" \
+                     -sol_list "sol_list.txt" \
+                     -root_buf "BUF_X4" \
+                     -wire_unit 20 
+
+report_cts [-out_file "file.txt"]
+```
+
+- ``-out_file`` (optional) is the file containing the TritonCTS reports.
+If this parameter is omitted, the metrics are shown on the standard output.
+
+
 #### Global Routing
 
 FastRoute global route.

include/openroad/OpenRoad.hh

@@ -98,6 +98,11 @@ namespace pdnsim {
 class PDNSim;
 }
 
+namespace antenna_checker {
+class AntennaChecker;
+}
+
+
 namespace ord {
 
 using std::string;
@@ -128,6 +133,7 @@ public:
   replace::Replace* getReplace() { return replace_; }
   pdnsim::PDNSim* getPDNSim() { return pdnsim_; }
   FastRoute::FastRouteKernel* getFastRoute() { return fastRoute_; }
+  antenna_checker::AntennaChecker *getAntennaChecker(){ return antennaChecker_; }
   // Return the bounding box of the db rows.
   odb::Rect getCore();
   // Return true if the command units have been initialized.
@@ -186,6 +192,7 @@ private:
   TritonCTS::TritonCTSKernel *tritonCts_;
   tapcell::Tapcell *tapcell_;
   OpenRCX::Ext *extractor_;
+  antenna_checker::AntennaChecker *antennaChecker_;
 #ifdef BUILD_OPENPHYSYN
   psn::Psn *psn_;
 #endif
@@ -206,5 +213,9 @@ getCore(odb::dbBlock *block);
 odb::Point
 closestPtInRect(odb::Rect rect,
 		odb::Point pt);
+odb::Point
+closestPtInRect(odb::Rect rect,
+		int x,
+		int y);
 
 } // namespace

src/CMakeLists.txt

@@ -30,6 +30,7 @@ set(OPENRCX_HOME ${OPENROAD_HOME}/src/OpenRCX)
 set(MPLACE_HOME ${PROJECT_SOURCE_DIR}/src/TritonMacroPlace)
 set(OPENPHYSYN_HOME ${PROJECT_SOURCE_DIR}/src/OpenPhySyn)
 set(PDNSIM_HOME ${PROJECT_SOURCE_DIR}/src/PDNSim)
+set(ANTENNACHECKER_HOME ${PROJECT_SOURCE_DIR}/src/antennachecker)
 
 set(OPENROAD_TCL_INIT ${CMAKE_CURRENT_BINARY_DIR}/OpenRoadTclInitVar.cc)
 
@@ -220,6 +221,7 @@ add_subdirectory(tapcell)
 add_subdirectory(TritonMacroPlace)
 add_subdirectory(OpenRCX)
 add_subdirectory(PDNSim)
+add_subdirectory(antennachecker)
 
 if(BUILD_OPENPHYSYN)
   add_subdirectory(OpenPhySyn)
@@ -255,6 +257,7 @@ target_include_directories(openroad
   ${TAPCELL_HOME}/include
   ${OPENRCX_HOME}/include
   ${PDNSIM_HOME}/include
+  ${ANTENNACHECKER_HOME}/include
   ${TCL_INCLUDE_PATH}
   ${Boost_INCLUDE_DIRS}
   )
@@ -285,6 +288,7 @@ target_link_libraries(openroad
   defout
   lefin
   lefout
+  antennachecker
   zutil
   ${TCL_LIBRARY}
 )