-
Notifications
You must be signed in to change notification settings - Fork 2
/
Copy patharm-gen.c
2388 lines (2246 loc) · 59.7 KB
/
arm-gen.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* ARMv4 code generator for TCC
*
* Copyright (c) 2003 Daniel Glöckner
* Copyright (c) 2012 Thomas Preud'homme
*
* Based on i386-gen.c by Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifdef TARGET_DEFS_ONLY
#if defined(TCC_ARM_EABI) && !defined(TCC_ARM_VFP)
#error "Currently TinyCC only supports float computation with VFP instructions"
#endif
/* number of available registers */
#ifdef TCC_ARM_VFP
#define NB_REGS 13
#else
#define NB_REGS 9
#endif
#ifndef CONFIG_TCC_CPUVER
# define CONFIG_TCC_CPUVER 5
#endif
/* a register can belong to several classes. The classes must be
sorted from more general to more precise (see gv2() code which does
assumptions on it). */
#define RC_INT 0x0001 /* generic integer register */
#define RC_FLOAT 0x0002 /* generic float register */
#define RC_R0 0x0004
#define RC_R1 0x0008
#define RC_R2 0x0010
#define RC_R3 0x0020
#define RC_R12 0x0040
#define RC_F0 0x0080
#define RC_F1 0x0100
#define RC_F2 0x0200
#define RC_F3 0x0400
#ifdef TCC_ARM_VFP
#define RC_F4 0x0800
#define RC_F5 0x1000
#define RC_F6 0x2000
#define RC_F7 0x4000
#endif
#define RC_IRET RC_R0 /* function return: integer register */
#define RC_IRE2 RC_R1 /* function return: second integer register */
#define RC_FRET RC_F0 /* function return: float register */
/* pretty names for the registers */
enum {
TREG_R0 = 0,
TREG_R1,
TREG_R2,
TREG_R3,
TREG_R12,
TREG_F0,
TREG_F1,
TREG_F2,
TREG_F3,
#ifdef TCC_ARM_VFP
TREG_F4,
TREG_F5,
TREG_F6,
TREG_F7,
#endif
TREG_SP = 13,
TREG_LR,
};
#ifdef TCC_ARM_VFP
#define T2CPR(t) (((t) & VT_BTYPE) != VT_FLOAT ? 0x100 : 0)
#endif
/* return registers for function */
#define REG_IRET TREG_R0 /* single word int return register */
#define REG_IRE2 TREG_R1 /* second word return register (for long long) */
#define REG_FRET TREG_F0 /* float return register */
#ifdef TCC_ARM_EABI
#define TOK___divdi3 TOK___aeabi_ldivmod
#define TOK___moddi3 TOK___aeabi_ldivmod
#define TOK___udivdi3 TOK___aeabi_uldivmod
#define TOK___umoddi3 TOK___aeabi_uldivmod
#endif
/* defined if function parameters must be evaluated in reverse order */
#define INVERT_FUNC_PARAMS
/* defined if structures are passed as pointers. Otherwise structures
are directly pushed on stack. */
/* #define FUNC_STRUCT_PARAM_AS_PTR */
/* pointer size, in bytes */
#define PTR_SIZE 4
/* long double size and alignment, in bytes */
#ifdef TCC_ARM_VFP
#define LDOUBLE_SIZE 8
#endif
#ifndef LDOUBLE_SIZE
#define LDOUBLE_SIZE 8
#endif
#ifdef TCC_ARM_EABI
#define LDOUBLE_ALIGN 8
#else
#define LDOUBLE_ALIGN 4
#endif
/* maximum alignment (for aligned attribute support) */
#define MAX_ALIGN 8
#define CHAR_IS_UNSIGNED
#ifdef TCC_ARM_HARDFLOAT
# define ARM_FLOAT_ABI ARM_HARD_FLOAT
#else
# define ARM_FLOAT_ABI ARM_SOFTFP_FLOAT
#endif
/******************************************************/
#else /* ! TARGET_DEFS_ONLY */
/******************************************************/
#define USING_GLOBALS
#include "tcc.h"
ST_DATA const char * const target_machine_defs =
"__arm__\0"
"__arm\0"
"arm\0"
"__arm_elf__\0"
"__arm_elf\0"
"arm_elf\0"
"__ARM_ARCH_4__\0"
"__ARMEL__\0"
"__APCS_32__\0"
#if defined TCC_ARM_EABI
"__ARM_EABI__\0"
#endif
;
enum float_abi float_abi;
ST_DATA const int reg_classes[NB_REGS] = {
/* r0 */ RC_INT | RC_R0,
/* r1 */ RC_INT | RC_R1,
/* r2 */ RC_INT | RC_R2,
/* r3 */ RC_INT | RC_R3,
/* r12 */ RC_INT | RC_R12,
/* f0 */ RC_FLOAT | RC_F0,
/* f1 */ RC_FLOAT | RC_F1,
/* f2 */ RC_FLOAT | RC_F2,
/* f3 */ RC_FLOAT | RC_F3,
#ifdef TCC_ARM_VFP
/* d4/s8 */ RC_FLOAT | RC_F4,
/* d5/s10 */ RC_FLOAT | RC_F5,
/* d6/s12 */ RC_FLOAT | RC_F6,
/* d7/s14 */ RC_FLOAT | RC_F7,
#endif
};
static int func_sub_sp_offset, last_itod_magic;
static int leaffunc;
#if defined(CONFIG_TCC_BCHECK)
static addr_t func_bound_offset;
static unsigned long func_bound_ind;
ST_DATA int func_bound_add_epilog;
#endif
#if defined(TCC_ARM_EABI) && defined(TCC_ARM_VFP)
static CType float_type, double_type, func_float_type, func_double_type;
ST_FUNC void arm_init(struct TCCState *s)
{
float_type.t = VT_FLOAT;
double_type.t = VT_DOUBLE;
func_float_type.t = VT_FUNC;
func_float_type.ref = sym_push(SYM_FIELD, &float_type, FUNC_CDECL, FUNC_OLD);
func_double_type.t = VT_FUNC;
func_double_type.ref = sym_push(SYM_FIELD, &double_type, FUNC_CDECL, FUNC_OLD);
float_abi = s->float_abi;
#ifndef TCC_ARM_HARDFLOAT
// XXX: Works on OpenBSD
// # warning "soft float ABI currently not supported: default to softfp"
#endif
}
#else
#define func_float_type func_old_type
#define func_double_type func_old_type
#define func_ldouble_type func_old_type
ST_FUNC void arm_init(struct TCCState *s)
{
#if 0
#if !defined (TCC_ARM_VFP)
tcc_warning("Support for FPA is deprecated and will be removed in next"
" release");
#endif
#if !defined (TCC_ARM_EABI)
tcc_warning("Support for OABI is deprecated and will be removed in next"
" release");
#endif
#endif
}
#endif
#define CHECK_R(r) ((r) >= TREG_R0 && (r) <= TREG_LR)
static int two2mask(int a,int b) {
if (!CHECK_R(a) || !CHECK_R(b))
tcc_error("compiler error! registers %i,%i is not valid",a,b);
return (reg_classes[a]|reg_classes[b])&~(RC_INT|RC_FLOAT);
}
static int regmask(int r) {
if (!CHECK_R(r))
tcc_error("compiler error! register %i is not valid",r);
return reg_classes[r]&~(RC_INT|RC_FLOAT);
}
/******************************************************/
#if defined(TCC_ARM_EABI) && !defined(CONFIG_TCC_ELFINTERP)
const char *default_elfinterp(struct TCCState *s)
{
if (s->float_abi == ARM_HARD_FLOAT)
return "/lib/ld-linux-armhf.so.3";
else
return "/lib/ld-linux.so.3";
}
#endif
void o(uint32_t i)
{
/* this is a good place to start adding big-endian support*/
int ind1;
if (nocode_wanted)
return;
ind1 = ind + 4;
if (!cur_text_section)
tcc_error("compiler error! This happens f.ex. if the compiler\n"
"can't evaluate constant expressions outside of a function.");
if (ind1 > cur_text_section->data_allocated)
section_realloc(cur_text_section, ind1);
cur_text_section->data[ind++] = i&255;
i>>=8;
cur_text_section->data[ind++] = i&255;
i>>=8;
cur_text_section->data[ind++] = i&255;
i>>=8;
cur_text_section->data[ind++] = i;
}
static uint32_t stuff_const(uint32_t op, uint32_t c)
{
int try_neg=0;
uint32_t nc = 0, negop = 0;
switch(op&0x1F00000)
{
case 0x800000: //add
case 0x400000: //sub
try_neg=1;
negop=op^0xC00000;
nc=-c;
break;
case 0x1A00000: //mov
case 0x1E00000: //mvn
try_neg=1;
negop=op^0x400000;
nc=~c;
break;
case 0x200000: //xor
if(c==~0)
return (op&0xF010F000)|((op>>16)&0xF)|0x1E00000;
break;
case 0x0: //and
if(c==~0)
return (op&0xF010F000)|((op>>16)&0xF)|0x1A00000;
case 0x1C00000: //bic
try_neg=1;
negop=op^0x1C00000;
nc=~c;
break;
case 0x1800000: //orr
if(c==~0)
return (op&0xFFF0FFFF)|0x1E00000;
break;
}
do {
uint32_t m;
int i;
if(c<256) /* catch undefined <<32 */
return op|c;
for(i=2;i<32;i+=2) {
m=(0xff>>i)|(0xff<<(32-i));
if(!(c&~m))
return op|(i<<7)|(c<<i)|(c>>(32-i));
}
op=negop;
c=nc;
} while(try_neg--);
return 0;
}
//only add,sub
void stuff_const_harder(uint32_t op, uint32_t v) {
uint32_t x;
x=stuff_const(op,v);
if(x)
o(x);
else {
uint32_t a[16], nv, no, o2, n2;
int i,j,k;
a[0]=0xff;
o2=(op&0xfff0ffff)|((op&0xf000)<<4);;
for(i=1;i<16;i++)
a[i]=(a[i-1]>>2)|(a[i-1]<<30);
for(i=0;i<12;i++)
for(j=i<4?i+12:15;j>=i+4;j--)
if((v&(a[i]|a[j]))==v) {
o(stuff_const(op,v&a[i]));
o(stuff_const(o2,v&a[j]));
return;
}
no=op^0xC00000;
n2=o2^0xC00000;
nv=-v;
for(i=0;i<12;i++)
for(j=i<4?i+12:15;j>=i+4;j--)
if((nv&(a[i]|a[j]))==nv) {
o(stuff_const(no,nv&a[i]));
o(stuff_const(n2,nv&a[j]));
return;
}
for(i=0;i<8;i++)
for(j=i+4;j<12;j++)
for(k=i<4?i+12:15;k>=j+4;k--)
if((v&(a[i]|a[j]|a[k]))==v) {
o(stuff_const(op,v&a[i]));
o(stuff_const(o2,v&a[j]));
o(stuff_const(o2,v&a[k]));
return;
}
no=op^0xC00000;
nv=-v;
for(i=0;i<8;i++)
for(j=i+4;j<12;j++)
for(k=i<4?i+12:15;k>=j+4;k--)
if((nv&(a[i]|a[j]|a[k]))==nv) {
o(stuff_const(no,nv&a[i]));
o(stuff_const(n2,nv&a[j]));
o(stuff_const(n2,nv&a[k]));
return;
}
o(stuff_const(op,v&a[0]));
o(stuff_const(o2,v&a[4]));
o(stuff_const(o2,v&a[8]));
o(stuff_const(o2,v&a[12]));
}
}
uint32_t encbranch(int pos, int addr, int fail)
{
addr-=pos+8;
addr/=4;
if(addr>=0x1000000 || addr<-0x1000000) {
if(fail)
tcc_error("FIXME: function bigger than 32MB");
return 0;
}
return 0x0A000000|(addr&0xffffff);
}
int decbranch(int pos)
{
int x;
x=*(uint32_t *)(cur_text_section->data + pos);
x&=0x00ffffff;
if(x&0x800000)
x-=0x1000000;
return x*4+pos+8;
}
/* output a symbol and patch all calls to it */
void gsym_addr(int t, int a)
{
uint32_t *x;
int lt;
while(t) {
x=(uint32_t *)(cur_text_section->data + t);
t=decbranch(lt=t);
if(a==lt+4)
*x=0xE1A00000; // nop
else {
*x &= 0xff000000;
*x |= encbranch(lt,a,1);
}
}
}
#ifdef TCC_ARM_VFP
static uint32_t vfpr(int r)
{
if(r<TREG_F0 || r>TREG_F7)
tcc_error("compiler error! register %i is no vfp register",r);
return r - TREG_F0;
}
#else
static uint32_t fpr(int r)
{
if(r<TREG_F0 || r>TREG_F3)
tcc_error("compiler error! register %i is no fpa register",r);
return r - TREG_F0;
}
#endif
static uint32_t intr(int r)
{
if(r == TREG_R12)
return 12;
if(r >= TREG_R0 && r <= TREG_R3)
return r - TREG_R0;
if (!(r >= TREG_SP && r <= TREG_LR))
tcc_error("compiler error! register %i is no int register",r);
return r + (13 - TREG_SP);
}
static void calcaddr(uint32_t *base, int *off, int *sgn, int maxoff, unsigned shift)
{
if(*off>maxoff || *off&((1<<shift)-1)) {
uint32_t x, y;
x=0xE280E000;
if(*sgn)
x=0xE240E000;
x|=(*base)<<16;
*base=14; // lr
y=stuff_const(x,*off&~maxoff);
if(y) {
o(y);
*off&=maxoff;
return;
}
y=stuff_const(x,(*off+maxoff)&~maxoff);
if(y) {
o(y);
*sgn=!*sgn;
*off=((*off+maxoff)&~maxoff)-*off;
return;
}
stuff_const_harder(x,*off&~maxoff);
*off&=maxoff;
}
}
static uint32_t mapcc(int cc)
{
switch(cc)
{
case TOK_ULT:
return 0x30000000; /* CC/LO */
case TOK_UGE:
return 0x20000000; /* CS/HS */
case TOK_EQ:
return 0x00000000; /* EQ */
case TOK_NE:
return 0x10000000; /* NE */
case TOK_ULE:
return 0x90000000; /* LS */
case TOK_UGT:
return 0x80000000; /* HI */
case TOK_Nset:
return 0x40000000; /* MI */
case TOK_Nclear:
return 0x50000000; /* PL */
case TOK_LT:
return 0xB0000000; /* LT */
case TOK_GE:
return 0xA0000000; /* GE */
case TOK_LE:
return 0xD0000000; /* LE */
case TOK_GT:
return 0xC0000000; /* GT */
}
tcc_error("unexpected condition code");
return 0xE0000000; /* AL */
}
static int negcc(int cc)
{
switch(cc)
{
case TOK_ULT:
return TOK_UGE;
case TOK_UGE:
return TOK_ULT;
case TOK_EQ:
return TOK_NE;
case TOK_NE:
return TOK_EQ;
case TOK_ULE:
return TOK_UGT;
case TOK_UGT:
return TOK_ULE;
case TOK_Nset:
return TOK_Nclear;
case TOK_Nclear:
return TOK_Nset;
case TOK_LT:
return TOK_GE;
case TOK_GE:
return TOK_LT;
case TOK_LE:
return TOK_GT;
case TOK_GT:
return TOK_LE;
}
tcc_error("unexpected condition code");
return TOK_NE;
}
/* Load value into register r.
Use relative/got addressing to avoid setting DT_TEXTREL */
static void load_value(SValue *sv, int r)
{
#if CONFIG_TCC_CPUVER >= 7
if (!(sv->r & VT_SYM)) {
unsigned x=sv->c.i;
o(0xE3000000|intr(r)<<12|(x&0xFFF)|(x<<4&0xF0000)); /* movw rx,#x(lo) */
if (x&0xFFFF0000)
o(0xE3400000|intr(r)<<12|(x>>16&0xFFF)|(x>>12&0xF0000)); /* movt rx,#x(hi) */
return;
}
#endif
o(0xE59F0000|(intr(r)<<12)); /* ldr r, [pc] */
o(0xEA000000); /* b $+4 */
#ifndef CONFIG_TCC_PIC
if(sv->r & VT_SYM)
greloc(cur_text_section, sv->sym, ind, R_ARM_ABS32);
o(sv->c.i);
#else
if(sv->r & VT_SYM) {
if (sv->sym->type.t & VT_STATIC) {
greloc(cur_text_section, sv->sym, ind, R_ARM_REL32);
o(sv->c.i - 12);
o(0xe080000f | (intr(r)<<12) | (intr(r)<<16)); // add rx,rx,pc
}
else {
greloc(cur_text_section, sv->sym, ind, R_ARM_GOT_PREL);
o(-12);
o(0xe080000f | (intr(r)<<12) | (intr(r)<<16)); // add rx,rx,pc
o(0xe5900000 | (intr(r)<<12) | (intr(r)<<16)); // ldr rx,[rx]
if (sv->c.i)
stuff_const_harder(0xe2800000 | (intr(r)<<12) | (intr(r)<<16),
sv->c.i);
}
}
else
o(sv->c.i);
#endif
}
/* load 'r' from value 'sv' */
void load(int r, SValue *sv)
{
int v, ft, fc, fr, sign;
uint32_t op;
SValue v1;
fr = sv->r;
ft = sv->type.t;
fc = sv->c.i;
if(fc>=0)
sign=0;
else {
sign=1;
fc=-fc;
}
v = fr & VT_VALMASK;
if (fr & VT_LVAL) {
uint32_t base = 0xB; // fp
if(v == VT_LLOCAL) {
v1.type.t = VT_PTR;
v1.r = VT_LOCAL | VT_LVAL;
v1.c.i = sv->c.i;
load(TREG_LR, &v1);
base = 14; /* lr */
fc=sign=0;
v=VT_LOCAL;
} else if(v == VT_CONST) {
v1.type.t = VT_PTR;
v1.r = fr&~VT_LVAL;
v1.c.i = sv->c.i;
v1.sym=sv->sym;
load(TREG_LR, &v1);
base = 14; /* lr */
fc=sign=0;
v=VT_LOCAL;
} else if(v < VT_CONST) {
base=intr(v);
fc=sign=0;
v=VT_LOCAL;
}
if(v == VT_LOCAL) {
if(is_float(ft)) {
calcaddr(&base,&fc,&sign,1020,2);
#ifdef TCC_ARM_VFP
op=0xED100A00; /* flds */
if(!sign)
op|=0x800000;
if ((ft & VT_BTYPE) != VT_FLOAT)
op|=0x100; /* flds -> fldd */
o(op|(vfpr(r)<<12)|(fc>>2)|(base<<16));
#else
op=0xED100100;
if(!sign)
op|=0x800000;
#if LDOUBLE_SIZE == 8
if ((ft & VT_BTYPE) != VT_FLOAT)
op|=0x8000;
#else
if ((ft & VT_BTYPE) == VT_DOUBLE)
op|=0x8000;
else if ((ft & VT_BTYPE) == VT_LDOUBLE)
op|=0x400000;
#endif
o(op|(fpr(r)<<12)|(fc>>2)|(base<<16));
#endif
} else if((ft & (VT_BTYPE|VT_UNSIGNED)) == VT_BYTE
|| (ft & VT_BTYPE) == VT_SHORT) {
calcaddr(&base,&fc,&sign,255,0);
op=0xE1500090;
if ((ft & VT_BTYPE) == VT_SHORT)
op|=0x20;
if ((ft & VT_UNSIGNED) == 0)
op|=0x40;
if(!sign)
op|=0x800000;
o(op|(intr(r)<<12)|(base<<16)|((fc&0xf0)<<4)|(fc&0xf));
} else {
calcaddr(&base,&fc,&sign,4095,0);
op=0xE5100000;
if(!sign)
op|=0x800000;
if ((ft & VT_BTYPE) == VT_BYTE || (ft & VT_BTYPE) == VT_BOOL)
op|=0x400000;
o(op|(intr(r)<<12)|fc|(base<<16));
}
return;
}
} else {
if (v == VT_CONST) {
op=stuff_const(0xE3A00000|(intr(r)<<12),sv->c.i);
if (fr & VT_SYM || !op)
load_value(sv, r);
else
o(op);
return;
} else if (v == VT_LOCAL) {
op=stuff_const(0xE28B0000|(intr(r)<<12),sv->c.i);
if (fr & VT_SYM || !op) {
load_value(sv, r);
o(0xE08B0000|(intr(r)<<12)|intr(r));
} else
o(op);
return;
} else if(v == VT_CMP) {
o(mapcc(sv->c.i)|0x3A00001|(intr(r)<<12));
o(mapcc(negcc(sv->c.i))|0x3A00000|(intr(r)<<12));
return;
} else if (v == VT_JMP || v == VT_JMPI) {
int t;
t = v & 1;
o(0xE3A00000|(intr(r)<<12)|t);
o(0xEA000000);
gsym(sv->c.i);
o(0xE3A00000|(intr(r)<<12)|(t^1));
return;
} else if (v < VT_CONST) {
if(is_float(ft))
#ifdef TCC_ARM_VFP
o(0xEEB00A40|(vfpr(r)<<12)|vfpr(v)|T2CPR(ft)); /* fcpyX */
#else
o(0xEE008180|(fpr(r)<<12)|fpr(v));
#endif
else
o(0xE1A00000|(intr(r)<<12)|intr(v));
return;
}
}
tcc_error("load unimplemented!");
}
/* store register 'r' in lvalue 'v' */
void store(int r, SValue *sv)
{
SValue v1;
int v, ft, fc, fr, sign;
uint32_t op;
fr = sv->r;
ft = sv->type.t;
fc = sv->c.i;
if(fc>=0)
sign=0;
else {
sign=1;
fc=-fc;
}
v = fr & VT_VALMASK;
if (fr & VT_LVAL || fr == VT_LOCAL) {
uint32_t base = 0xb; /* fp */
if(v < VT_CONST) {
base=intr(v);
v=VT_LOCAL;
fc=sign=0;
} else if(v == VT_CONST) {
v1.type.t = ft;
v1.r = fr&~VT_LVAL;
v1.c.i = sv->c.i;
v1.sym=sv->sym;
load(TREG_LR, &v1);
base = 14; /* lr */
fc=sign=0;
v=VT_LOCAL;
}
if(v == VT_LOCAL) {
if(is_float(ft)) {
calcaddr(&base,&fc,&sign,1020,2);
#ifdef TCC_ARM_VFP
op=0xED000A00; /* fsts */
if(!sign)
op|=0x800000;
if ((ft & VT_BTYPE) != VT_FLOAT)
op|=0x100; /* fsts -> fstd */
o(op|(vfpr(r)<<12)|(fc>>2)|(base<<16));
#else
op=0xED000100;
if(!sign)
op|=0x800000;
#if LDOUBLE_SIZE == 8
if ((ft & VT_BTYPE) != VT_FLOAT)
op|=0x8000;
#else
if ((ft & VT_BTYPE) == VT_DOUBLE)
op|=0x8000;
if ((ft & VT_BTYPE) == VT_LDOUBLE)
op|=0x400000;
#endif
o(op|(fpr(r)<<12)|(fc>>2)|(base<<16));
#endif
return;
} else if((ft & VT_BTYPE) == VT_SHORT) {
calcaddr(&base,&fc,&sign,255,0);
op=0xE14000B0;
if(!sign)
op|=0x800000;
o(op|(intr(r)<<12)|(base<<16)|((fc&0xf0)<<4)|(fc&0xf));
} else {
calcaddr(&base,&fc,&sign,4095,0);
op=0xE5000000;
if(!sign)
op|=0x800000;
if ((ft & VT_BTYPE) == VT_BYTE || (ft & VT_BTYPE) == VT_BOOL)
op|=0x400000;
o(op|(intr(r)<<12)|fc|(base<<16));
}
return;
}
}
tcc_error("store unimplemented");
}
static void gadd_sp(int val)
{
stuff_const_harder(0xE28DD000,val);
}
/* 'is_jmp' is '1' if it is a jump */
static void gcall_or_jmp(int is_jmp)
{
int r;
uint32_t x;
if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
/* constant case */
if(vtop->r & VT_SYM){
x=encbranch(ind,ind+vtop->c.i,0);
if(x) {
/* relocation case */
greloc(cur_text_section, vtop->sym, ind, R_ARM_PC24);
o(x|(is_jmp?0xE0000000:0xE1000000));
} else {
r = TREG_LR;
load_value(vtop, r);
if(is_jmp)
o(0xE1A0F000 | intr(r)); // mov pc, r
else
o(0xe12fff30 | intr(r)); // blx r
}
}else{
if(!is_jmp)
o(0xE28FE004); // add lr,pc,#4
o(0xE51FF004); // ldr pc,[pc,#-4]
o(vtop->c.i);
}
} else {
/* otherwise, indirect call */
#ifdef CONFIG_TCC_BCHECK
vtop->r &= ~VT_MUSTBOUND;
#endif
r = gv(RC_INT);
if(!is_jmp)
o(0xE1A0E00F); // mov lr,pc
o(0xE1A0F000|intr(r)); // mov pc,r
}
}
#if defined(CONFIG_TCC_BCHECK)
static void gen_bounds_call(int v)
{
Sym *sym = external_helper_sym(v);
greloc(cur_text_section, sym, ind, R_ARM_PC24);
o(0xebfffffe);
}
static void gen_bounds_prolog(void)
{
/* leave some room for bound checking code */
func_bound_offset = lbounds_section->data_offset;
func_bound_ind = ind;
func_bound_add_epilog = 0;
o(0xe1a00000); /* ld r0,lbounds_section->data_offset */
o(0xe1a00000);
o(0xe1a00000);
o(0xe1a00000);
o(0xe1a00000); /* call __bound_local_new */
}
static void gen_bounds_epilog(void)
{
addr_t saved_ind;
addr_t *bounds_ptr;
Sym *sym_data;
int offset_modified = func_bound_offset != lbounds_section->data_offset;
if (!offset_modified && !func_bound_add_epilog)
return;
/* add end of table info */
bounds_ptr = section_ptr_add(lbounds_section, sizeof(addr_t));
*bounds_ptr = 0;
sym_data = get_sym_ref(&char_pointer_type, lbounds_section,
func_bound_offset, PTR_SIZE);
/* generate bound local allocation */
if (offset_modified) {
saved_ind = ind;
ind = func_bound_ind;
o(0xe59f0000); /* ldr r0, [pc] */
o(0xea000000); /* b $+4 */
greloc(cur_text_section, sym_data, ind, R_ARM_REL32);
o(-12); /* lbounds_section->data_offset */
o(0xe080000f); /* add r0,r0,pc */
gen_bounds_call(TOK___bound_local_new);
ind = saved_ind;
}
/* generate bound check local freeing */
o(0xe92d0003); /* push {r0,r1} */
o(0xed2d0b04); /* vpush {d0,d1} */
o(0xe59f0000); /* ldr r0, [pc] */
o(0xea000000); /* b $+4 */
greloc(cur_text_section, sym_data, ind, R_ARM_REL32);
o(-12); /* lbounds_section->data_offset */
o(0xe080000f); /* add r0,r0,pc */
gen_bounds_call(TOK___bound_local_delete);
o(0xecbd0b04); /* vpop {d0,d1} */
o(0xe8bd0003); /* pop {r0,r1} */
}
#endif
static int unalias_ldbl(int btype)
{
#if LDOUBLE_SIZE == 8
if (btype == VT_LDOUBLE)
btype = VT_DOUBLE;
#endif
return btype;
}
/* Return whether a structure is an homogeneous float aggregate or not.
The answer is true if all the elements of the structure are of the same
primitive float type and there is less than 4 elements.
type: the type corresponding to the structure to be tested */
static int is_hgen_float_aggr(CType *type)
{
if ((type->t & VT_BTYPE) == VT_STRUCT) {
struct Sym *ref;
int btype, nb_fields = 0;
ref = type->ref->next;
if (ref) {
btype = unalias_ldbl(ref->type.t & VT_BTYPE);
if (btype == VT_FLOAT || btype == VT_DOUBLE) {
for(; ref && btype == unalias_ldbl(ref->type.t & VT_BTYPE); ref = ref->next, nb_fields++);
return !ref && nb_fields <= 4;
}
}
}
return 0;
}
struct avail_regs {
signed char avail[3]; /* 3 holes max with only float and double alignments */
int first_hole; /* first available hole */
int last_hole; /* last available hole (none if equal to first_hole) */
int first_free_reg; /* next free register in the sequence, hole excluded */
};
/* Find suitable registers for a VFP Co-Processor Register Candidate (VFP CPRC
param) according to the rules described in the procedure call standard for
the ARM architecture (AAPCS). If found, the registers are assigned to this
VFP CPRC parameter. Registers are allocated in sequence unless a hole exists
and the parameter is a single float.
avregs: opaque structure to keep track of available VFP co-processor regs
align: alignment constraints for the param, as returned by type_size()
size: size of the parameter, as returned by type_size() */
int assign_vfpreg(struct avail_regs *avregs, int align, int size)
{
int first_reg = 0;
if (avregs->first_free_reg == -1)
return -1;
if (align >> 3) { /* double alignment */
first_reg = avregs->first_free_reg;
/* alignment constraint not respected so use next reg and record hole */
if (first_reg & 1)
avregs->avail[avregs->last_hole++] = first_reg++;
} else { /* no special alignment (float or array of float) */
/* if single float and a hole is available, assign the param to it */
if (size == 4 && avregs->first_hole != avregs->last_hole)
return avregs->avail[avregs->first_hole++];
else
first_reg = avregs->first_free_reg;
}
if (first_reg + size / 4 <= 16) {
avregs->first_free_reg = first_reg + size / 4;
return first_reg;
}
avregs->first_free_reg = -1;
return -1;
}
/* Returns whether all params need to be passed in core registers or not.
This is the case for function part of the runtime ABI. */
int floats_in_core_regs(SValue *sval)
{
if (!sval->sym)
return 0;
switch (sval->sym->v) {
case TOK___floatundisf:
case TOK___floatundidf:
case TOK___fixunssfdi:
case TOK___fixunsdfdi:
#ifndef TCC_ARM_VFP
case TOK___fixunsxfdi:
#endif
case TOK___floatdisf:
case TOK___floatdidf:
case TOK___fixsfdi:
case TOK___fixdfdi:
return 1;