Full SME(1) instruction support and STREAMING Groups #415
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Some comments and I agree with several of Alex's comments. I think it would be good to get the ARM SME/SVE loops as part of our functional verification checks to help test these new instructions. I assume it would have to be done somewhere private though (not sure if we already have that guarantee in the upcoming CI/CD pipelines)?
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Now outdated as STREAMING groups logic removed which was the only cause for slowdown.
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…ssion test (B, H, S, D)
…ion test (B, H, S, D)
…n alias and regression tests (B, H, S, D)
…uctions and aliases and regression tests (B, H, S, D)
…regression tests.
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I assume that it has been checked, but a reminder of the SME loops comment in #415 (review)
This PR doesn't add support for many of those loops (most LD/STR instructions still missing as need newer ISA version than this PR targets). Without access to physical hardware (i.e. an Apple M4) where we can generate small tests and verify the output against our current regression tests for these instructions, there currently aren't any binaries that we could run to ensure validity of most instructions added in this PR. For PR #439, the loops would be able to be used (as that PR targets them) but still need to be done privately. |
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This PR implements all available SME (version 1) instructions that are contained within LLVM 14.0.5. Specifically, this is Version 2021-06 of the Armv9-A A64 ISA.
No FP16 or BF16 instructions have been supported due to lacking C++17 types. All Quad-Word instruction variants have been emulated using 64-bit data-types.
In addition to this, new STREAMING_SVE and STREAMING_PREDICATE groups have been introduced (along with corresponding decode logic) to allow for a different pipeline / latency configuration for these instructions when SVE Streaming Mode (the context mode which SME instructions are executed in) is enabled. This can allow for a co-processor style implementation of SME to be implemented within SimEng; with additional latency / reduced throughput being configured to mimic an offload penalty, and different execution or LD/STR hardware being modelled for said co-processor compared to the main core.