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25 Open 245 Closed
25 Open 245 Closed
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Issues list

[DesignTools] createMissingSitePinInsts() Out Of Memory
#1202 opened May 28, 2025 by coherent17
4
PolynomialGenerator not generating correct hardware
#1195 opened May 21, 2025 by clavin-xlnx
@clavin-xlnx
Cell properties not propagated in macro cells to child instances enhancement
#1069 opened Sep 24, 2024 by clavin-xlnx
@clavin-xlnx
LUTTools.swapSingleLutPins() cannot swap H[1-6] when used as WA enhancement
#901 opened Nov 29, 2023 by eddieh-xlnx
GlobalSignalRouting.getLCBPinMappings() fails for some pins bug
#756 opened Jul 17, 2023 by eddieh-xlnx
@eddieh-xlnx
[Interchange] EnumerateCellBelMapping Speedup Opportunity enhancement
#659 opened Apr 28, 2023 by clavin-xlnx
Speedup interchange.DeviceResourcesExample enhancement
#625 opened Mar 10, 2023 by eddieh-xlnx
Trimming PIPs of pins on net one-at-a-time may not work bug
#485 opened Jul 26, 2022 by eddieh-xlnx
ModuleInst.place() does not check for overlap
#478 opened Jul 19, 2022 by clavin-xlnx
" Too many words to allocate: 333129474" beyond the limit of capnp?
#410 opened May 7, 2022 by the-centry
1
RapidWright should track in the netlist if macros have been expanded or collapsed
#388 opened Apr 15, 2022 by clavin-xlnx
2
Provide the equivalent of write_checkpoint -cell in RapidWright enhancement
#386 opened Apr 13, 2022 by clavin-xlnx
Adding an API to insert a buffer cell (LUT1 or FF) on a module's ports enhancement
#356 opened Mar 4, 2022 by clavin-xlnx
DesignTools.copyImplementation() not reproducing SitePinInst objects on copied nets correctly bug
#347 opened Feb 23, 2022 by clavin-xlnx
1
Add equivalent lock_design APIs enhancement
#314 opened Dec 16, 2021 by clavin-xlnx
ModuleImpls requires pointer identical netlist for Modules enhancement
#301 opened Dec 2, 2021 by clavin-xlnx
DRC to identify missing SitePinInst-s in a design enhancement
#282 opened Nov 2, 2021 by eddieh-xlnx
DRC for in-context module site routing conflicts enhancement
#281 opened Nov 2, 2021 by eddieh-xlnx
Standardize and make clear when to unique-ify cell names enhancement
#278 opened Oct 29, 2021 by clavin-xlnx
Add examples to :/test to be run during CI enhancement help wanted
#247 opened Sep 28, 2021 by eddieh-xlnx
ModuleInstanceScene does not deal with relocation correctly help wanted
#230 opened Sep 17, 2021 by jakobwenzel
1
Overlapped modules
#123 opened Jan 20, 2021 by ElaHobby
6
Wire w/ Null Tile included in tile.getWireConnections(wire) for Wires with FAKE_SM_VALUE Speed Model
#80 opened Sep 28, 2020 by GTRI-Dallon
@clavin-xlnx
3
EDIFCellInst.equals() returns True for instances of different type in different parents enhancement
#42 opened Jul 25, 2019 by cfib
2
Contributing to documentation (rapidwright.io/docs)
#18 opened Feb 5, 2019 by HarrisonMc555
@clavin-xlnx
1
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