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| 1 | +/* |
| 2 | + * This is a small example showing howto connect an RTL UMI Device |
| 3 | + * to a SystemC/TLM simulation using the TLM-2-UMI bridge. |
| 4 | + * |
| 5 | + * Copyright (c) 2024 Zero ASIC. |
| 6 | + * Written by Edgar E. Iglesias |
| 7 | + * |
| 8 | + * SPDX-License-Identifier: MIT |
| 9 | + */ |
| 10 | + |
| 11 | +#include <sstream> |
| 12 | + |
| 13 | +#define SC_INCLUDE_DYNAMIC_PROCESSES |
| 14 | + |
| 15 | +#include "systemc" |
| 16 | +using namespace sc_core; |
| 17 | +using namespace sc_dt; |
| 18 | +using namespace std; |
| 19 | + |
| 20 | +#include "tlm.h" |
| 21 | +#include "tlm_utils/simple_initiator_socket.h" |
| 22 | +#include "tlm_utils/simple_target_socket.h" |
| 23 | + |
| 24 | +#include "tlm-bridges/tlm2umi-bridge.h" |
| 25 | +#include "tlm-bridges/umi2tlm-bridge.h" |
| 26 | +#include "tlm-modules/tlm-splitter.h" |
| 27 | +#include "traffic-generators/tg-tlm.h" |
| 28 | +#include "traffic-generators/random-traffic.h" |
| 29 | + |
| 30 | +#include "test-modules/signals-umi.h" |
| 31 | +#include "test-modules/memory.h" |
| 32 | +#include "trace/trace.h" |
| 33 | + |
| 34 | +#define RAM_SIZE (64 * 1024) |
| 35 | +#ifndef DW |
| 36 | +#define DW 256 |
| 37 | +#endif |
| 38 | + |
| 39 | +SC_MODULE(Top) |
| 40 | +{ |
| 41 | + sc_clock clk; |
| 42 | + sc_signal<bool> rst; |
| 43 | + |
| 44 | + TLMTrafficGenerator tg; |
| 45 | + UMISignals<DW> signals_req; |
| 46 | + UMISignals<DW> signals_resp; |
| 47 | + tlm2umi_bridge<DW> tlm2umi; |
| 48 | + umi2tlm_bridge<DW> umi2tlm; |
| 49 | + tlm_splitter<2> splitter; |
| 50 | + memory mem; |
| 51 | + memory ref_mem; |
| 52 | + RandomTraffic transfers; |
| 53 | + |
| 54 | + void do_reset(void) { |
| 55 | + int i; |
| 56 | + |
| 57 | + rst.write(false); |
| 58 | + for (i = 0; i < 2; i++) { |
| 59 | + wait(clk.posedge_event()); |
| 60 | + } |
| 61 | + rst.write(true); |
| 62 | + for (i = 0; i < 4; i++) { |
| 63 | + wait(clk.posedge_event()); |
| 64 | + } |
| 65 | + rst.write(false); |
| 66 | + } |
| 67 | + |
| 68 | + SC_HAS_PROCESS(Top); |
| 69 | + Top(sc_module_name name) : |
| 70 | + clk("clk", sc_time(1, SC_US)), |
| 71 | + rst("rst"), |
| 72 | + tg("traffic_generator"), |
| 73 | + signals_req("signals_req"), |
| 74 | + signals_resp("signals_resp"), |
| 75 | + tlm2umi("tlm2umi"), |
| 76 | + umi2tlm("umi2tlm"), |
| 77 | + splitter("splitter", true), |
| 78 | + mem("mem", sc_time(10, SC_NS), RAM_SIZE), |
| 79 | + ref_mem("ref_mem", sc_time(10, SC_NS), RAM_SIZE), |
| 80 | + transfers(0, RAM_SIZE - DW/8, (~(DW/8 - 1)), 1, DW/8, 0, 2 * 1024) |
| 81 | + { |
| 82 | + SC_THREAD(do_reset); |
| 83 | + |
| 84 | + // Configure the Traffic generator. |
| 85 | + transfers.setMaxStreamingWidthLen(0); |
| 86 | + tg.setStartDelay(sc_time(8, SC_US)); |
| 87 | + tg.enableDebug(); |
| 88 | + tg.addTransfers(transfers); |
| 89 | + tg.socket.bind(splitter.target_socket); |
| 90 | + |
| 91 | + // Wire up the clock and reset signals. |
| 92 | + tlm2umi.clk(clk); |
| 93 | + tlm2umi.rst(rst); |
| 94 | + umi2tlm.clk(clk); |
| 95 | + umi2tlm.rst(rst); |
| 96 | + |
| 97 | + // Wire-up the bridges. |
| 98 | + signals_req.connect(tlm2umi, "req_"); |
| 99 | + signals_resp.connect(tlm2umi, "resp_"); |
| 100 | + signals_req.connect(umi2tlm, "req_"); |
| 101 | + signals_resp.connect(umi2tlm, "resp_"); |
| 102 | + |
| 103 | + // Splitter |
| 104 | + splitter.i_sk[1]->bind(tlm2umi.socket); |
| 105 | + umi2tlm.socket.bind(mem.socket); |
| 106 | + splitter.i_sk[0]->bind(ref_mem.socket); |
| 107 | + } |
| 108 | +}; |
| 109 | + |
| 110 | +int sc_main(int argc, char *argv[]) |
| 111 | +{ |
| 112 | + Top top("Top"); |
| 113 | + |
| 114 | + // You must do one evaluation before enabling waves, in order to allow |
| 115 | + // SystemC to interconnect everything for testing. |
| 116 | + sc_start(SC_ZERO_TIME); |
| 117 | + |
| 118 | + sc_trace_file *trace_fp = sc_create_vcd_trace_file(argv[0]); |
| 119 | + trace(trace_fp, top, "top"); |
| 120 | + |
| 121 | + sc_start(10, SC_MS); |
| 122 | + sc_stop(); |
| 123 | + |
| 124 | + if (trace_fp) { |
| 125 | + sc_close_vcd_trace_file(trace_fp); |
| 126 | + } |
| 127 | + return 0; |
| 128 | +} |
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