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tests: tg: Add UMI test-cases
Signed-off-by: Edgar E. Iglesias <edgar@zeroasic.com>
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tests/Makefile

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@@ -36,6 +36,7 @@ SUBDIRS += traffic-generators/axis/
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SUBDIRS += traffic-generators/ace/
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SUBDIRS += traffic-generators/chi/
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SUBDIRS += traffic-generators/ccix/
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SUBDIRS += traffic-generators/umi/
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SUBDIRS += checkers/axi
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SUBDIRS += checkers/axilite
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SUBDIRS += checkers/ace

tests/traffic-generators/umi/Makefile

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#
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# Copyright (c) 2024 Zero ASIC.
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# Written by Edgar E. Iglesias.
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#
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# SPDX-License-Identifier: MIT
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-include ../../../.config.mk
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include ../../Rules.mk
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CPPFLAGS += -I ../../../ -I ../../ -I .
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CXXFLAGS += -O3 -g
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OBJS_COMMON += ../../../trace/trace.o
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OBJS_COMMON += ../../test-modules/memory.o
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ALL_OBJS += $(OBJS_COMMON) test-umi.o
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TARGETS += test-umi-dw32 \
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test-umi-dw64 \
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test-umi-dw128 \
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test-umi-dw256 \
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test-umi-dw512 \
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test-umi-dw1024
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all: $(TARGETS)
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## Dep generation ##
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-include $(ALL_OBJS:.o=.d)
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test-umi-%: test-umi.cc $(OBJS_COMMON)
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$(CXX) $(CPPFLAGS) $(CXXFLAGS) -DDW=$(subst test-umi-dw,,$@) $^ -o $@ $(LDFLAGS) $(LDLIBS)
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clean:
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$(RM) $(ALL_OBJS) $(ALL_OBJS:.o=.d)
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$(RM) $(TARGETS)
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$(RM) $(TARGETS:=.d)
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/*
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* This is a small example showing howto connect an RTL UMI Device
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* to a SystemC/TLM simulation using the TLM-2-UMI bridge.
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*
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* Copyright (c) 2024 Zero ASIC.
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* Written by Edgar E. Iglesias
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*
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* SPDX-License-Identifier: MIT
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*/
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#include <sstream>
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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#include "systemc"
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using namespace sc_core;
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using namespace sc_dt;
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using namespace std;
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#include "tlm.h"
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#include "tlm_utils/simple_initiator_socket.h"
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#include "tlm_utils/simple_target_socket.h"
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#include "tlm-bridges/tlm2umi-bridge.h"
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#include "tlm-bridges/umi2tlm-bridge.h"
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#include "tlm-modules/tlm-splitter.h"
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#include "traffic-generators/tg-tlm.h"
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#include "traffic-generators/random-traffic.h"
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#include "test-modules/signals-umi.h"
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#include "test-modules/memory.h"
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#include "trace/trace.h"
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#define RAM_SIZE (64 * 1024)
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#ifndef DW
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#define DW 256
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#endif
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SC_MODULE(Top)
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{
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sc_clock clk;
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sc_signal<bool> rst;
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TLMTrafficGenerator tg;
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UMISignals<DW> signals_req;
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UMISignals<DW> signals_resp;
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tlm2umi_bridge<DW> tlm2umi;
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umi2tlm_bridge<DW> umi2tlm;
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tlm_splitter<2> splitter;
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memory mem;
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memory ref_mem;
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RandomTraffic transfers;
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void do_reset(void) {
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int i;
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rst.write(false);
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for (i = 0; i < 2; i++) {
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wait(clk.posedge_event());
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}
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rst.write(true);
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for (i = 0; i < 4; i++) {
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wait(clk.posedge_event());
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}
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rst.write(false);
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}
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SC_HAS_PROCESS(Top);
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Top(sc_module_name name) :
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clk("clk", sc_time(1, SC_US)),
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rst("rst"),
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tg("traffic_generator"),
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signals_req("signals_req"),
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signals_resp("signals_resp"),
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tlm2umi("tlm2umi"),
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umi2tlm("umi2tlm"),
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splitter("splitter", true),
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mem("mem", sc_time(10, SC_NS), RAM_SIZE),
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ref_mem("ref_mem", sc_time(10, SC_NS), RAM_SIZE),
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transfers(0, RAM_SIZE - DW/8, (~(DW/8 - 1)), 1, DW/8, 0, 2 * 1024)
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{
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SC_THREAD(do_reset);
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// Configure the Traffic generator.
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transfers.setMaxStreamingWidthLen(0);
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tg.setStartDelay(sc_time(8, SC_US));
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tg.enableDebug();
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tg.addTransfers(transfers);
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tg.socket.bind(splitter.target_socket);
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// Wire up the clock and reset signals.
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tlm2umi.clk(clk);
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tlm2umi.rst(rst);
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umi2tlm.clk(clk);
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umi2tlm.rst(rst);
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// Wire-up the bridges.
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signals_req.connect(tlm2umi, "req_");
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signals_resp.connect(tlm2umi, "resp_");
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signals_req.connect(umi2tlm, "req_");
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signals_resp.connect(umi2tlm, "resp_");
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// Splitter
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splitter.i_sk[1]->bind(tlm2umi.socket);
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umi2tlm.socket.bind(mem.socket);
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splitter.i_sk[0]->bind(ref_mem.socket);
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}
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};
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int sc_main(int argc, char *argv[])
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{
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Top top("Top");
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// You must do one evaluation before enabling waves, in order to allow
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// SystemC to interconnect everything for testing.
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sc_start(SC_ZERO_TIME);
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sc_trace_file *trace_fp = sc_create_vcd_trace_file(argv[0]);
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trace(trace_fp, top, "top");
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sc_start(10, SC_MS);
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sc_stop();
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if (trace_fp) {
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sc_close_vcd_trace_file(trace_fp);
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}
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return 0;
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}

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