Merge pull request #263 from abs-tudelft/write-response-channel

Add write response channel & synchronization support
abs-tudelft · Jan 12, 2021 · 4a93cf6 · 4a93cf6
2 parents c878fcc + 82daca5
commit 4a93cf6
Show file tree

Hide file tree

Showing 39 changed files with 1,373 additions and 412 deletions.
diff --git a/codegen/cpp/fletchgen/src/fletchgen/bus.cc b/codegen/cpp/fletchgen/src/fletchgen/bus.cc
@@ -37,6 +37,7 @@ using cerata::parameter;
 using cerata::stream;
 using cerata::field;
 using cerata::vector;
+using cerata::bit;
 
 PARAM_FACTORY(bus_addr_width)
 PARAM_FACTORY(bus_data_width)
@@ -61,17 +62,21 @@ std::shared_ptr<Type> bus_write(const std::shared_ptr<Node> &addr_width,
                                 const std::shared_ptr<Node> &data_width,
                                 const std::shared_ptr<Node> &len_width) {
   auto wreq = stream(record("", {field("addr", vector(addr_width)),
-                                 field("len", vector(len_width))}));
+                                 field("len", vector(len_width)),
+                                 field("last", last())}));
   auto wdat = stream(record("", {field("data", vector(data_width)),
                                  field("strobe", vector(data_width / 8)),
                                  field("last", last())}));
+  auto wrep = stream(record("", {field("ok", bit())}));
   auto result = record("", {field("wreq", wreq),
-                            field("wdat", wdat)});
+                            field("wdat", wdat),
+                            field("wrep", wrep)->Reverse()});
   return result;
 }
 
 static std::string GetBusArbiterName(BusFunction function) {
-  return std::string("Bus") + (function == BusFunction::READ ? "Read" : "Write") + "ArbiterVec";
+  return std::string("Bus") + (function == BusFunction::READ ? "Read" : "Write")
+      + "ArbiterVec";
 }
 
 Component *bus_arbiter(BusFunction function) {

diff --git a/codegen/cpp/fletchgen/src/fletchgen/top/axi.cc b/codegen/cpp/fletchgen/src/fletchgen/top/axi.cc
@@ -125,22 +125,32 @@ std::string GenerateAXITop(const Mantle &mantle,
               "      wr_mst_wreq_ready        : in std_logic;\n"
               "      wr_mst_wreq_addr         : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
               "      wr_mst_wreq_len          : out std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
+              "      wr_mst_wreq_last         : out std_logic;\n"
               "      wr_mst_wdat_valid        : out std_logic;\n"
               "      wr_mst_wdat_ready        : in std_logic;\n"
               "      wr_mst_wdat_data         : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
               "      wr_mst_wdat_strobe       : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
-              "      wr_mst_wdat_last         : out std_logic;");
+              "      wr_mst_wdat_last         : out std_logic;"
+              "      wr_mst_wrep_valid        : in  std_logic;"
+              "      wr_mst_wrep_ready        : out std_logic;"
+              "      wr_mst_wrep_ok           : in  std_logic;"
+    );
 
     t.Replace("MST_WREQ_INSTANTIATE",
               "      wr_mst_wreq_valid         => wr_mst_wreq_valid,\n"
               "      wr_mst_wreq_ready         => wr_mst_wreq_ready,\n"
               "      wr_mst_wreq_addr          => wr_mst_wreq_addr,\n"
               "      wr_mst_wreq_len           => wr_mst_wreq_len,\n"
+              "      wr_mst_wreq_last          => wr_mst_wreq_last,\n"
               "      wr_mst_wdat_valid         => wr_mst_wdat_valid,\n"
               "      wr_mst_wdat_ready         => wr_mst_wdat_ready,\n"
               "      wr_mst_wdat_data          => wr_mst_wdat_data,\n"
               "      wr_mst_wdat_strobe        => wr_mst_wdat_strobe,\n"
-              "      wr_mst_wdat_last          => wr_mst_wdat_last,");
+              "      wr_mst_wdat_last          => wr_mst_wdat_last,\n"
+              "      wr_mst_wrep_valid         => wr_mst_wrep_valid,\n"
+              "      wr_mst_wrep_ready         => wr_mst_wrep_ready,\n"
+              "      wr_mst_wrep_ok            => wr_mst_wrep_ok,");
+
     t.Replace("AXI_WRITE_CONVERTER",
               "  -----------------------------------------------------------------------------\n"
               "  -- AXI write converter\n"
@@ -168,21 +178,29 @@ std::string GenerateAXITop(const Mantle &mantle,
               "      slv_bus_wreq_len          => wr_mst_wreq_len,\n"
               "      slv_bus_wreq_valid        => wr_mst_wreq_valid,\n"
               "      slv_bus_wreq_ready        => wr_mst_wreq_ready,\n"
+              "      slv_bus_wreq_last         => wr_mst_wreq_last,\n"
               "      slv_bus_wdat_data         => wr_mst_wdat_data,\n"
               "      slv_bus_wdat_strobe       => wr_mst_wdat_strobe,\n"
               "      slv_bus_wdat_last         => wr_mst_wdat_last,\n"
               "      slv_bus_wdat_valid        => wr_mst_wdat_valid,\n"
               "      slv_bus_wdat_ready        => wr_mst_wdat_ready,\n"
+              "      slv_bus_wrep_valid        => wr_mst_wrep_valid,\n"
+              "      slv_bus_wrep_ready        => wr_mst_wrep_ready,\n"
+              "      slv_bus_wrep_ok           => wr_mst_wrep_ok,\n"
               "      m_axi_awaddr              => m_axi_awaddr,\n"
               "      m_axi_awlen               => m_axi_awlen,\n"
               "      m_axi_awvalid             => m_axi_awvalid,\n"
               "      m_axi_awready             => m_axi_awready,\n"
               "      m_axi_awsize              => m_axi_awsize,\n"
+              "      m_axi_awuser              => m_axi_awuser,\n"
               "      m_axi_wdata               => m_axi_wdata,\n"
               "      m_axi_wstrb               => m_axi_wstrb,\n"
               "      m_axi_wlast               => m_axi_wlast,\n"
               "      m_axi_wvalid              => m_axi_wvalid,\n"
-              "      m_axi_wready              => m_axi_wready\n"
+              "      m_axi_wready              => m_axi_wready,\n"
+              "      m_axi_bvalid              => m_axi_bvalid,\n"
+              "      m_axi_bready              => m_axi_bready,\n"
+              "      m_axi_bresp               => m_axi_bresp\n"
               "    );");
   } else {
     t.Replace("MST_WREQ_DECLARE", "");

diff --git a/codegen/cpp/fletchgen/src/fletchgen/top/axi_template.h b/codegen/cpp/fletchgen/src/fletchgen/top/axi_template.h
@@ -100,6 +100,7 @@ static char axi_source[] =
     "    m_axi_awaddr                : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
     "    m_axi_awlen                 : out std_logic_vector(7 downto 0);\n"
     "    m_axi_awsize                : out std_logic_vector(2 downto 0);\n"
+    "    m_axi_awuser                : out std_logic_vector(0 downto 0);\n"
     "\n"
     "    -- Write data channel\n"
     "    m_axi_wvalid                : out std_logic := '0';\n"
@@ -108,6 +109,10 @@ static char axi_source[] =
     "    m_axi_wlast                 : out std_logic;\n"
     "    m_axi_wstrb                 : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
     "\n"
+    "    -- Write response channel\n"
+    "    m_axi_bvalid                : in  std_logic;\n"
+    "    m_axi_bready                : out std_logic;\n"
+    "    m_axi_bresp                 : in  std_logic_vector(1 downto 0);\n"
     "    ---------------------------------------------------------------------------\n"
     "    -- AXI4-lite Slave as MMIO interface\n"
     "    ---------------------------------------------------------------------------\n"
@@ -165,11 +170,16 @@ static char axi_source[] =
     "  signal wr_mst_wreq_ready      : std_logic;\n"
     "  signal wr_mst_wreq_addr       : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
     "  signal wr_mst_wreq_len        : std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
+    "  signal wr_mst_wreq_last       : std_logic;\n"
     "  signal wr_mst_wdat_valid      : std_logic;\n"
     "  signal wr_mst_wdat_ready      : std_logic;\n"
     "  signal wr_mst_wdat_data       : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
     "  signal wr_mst_wdat_strobe     : std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
     "  signal wr_mst_wdat_last       : std_logic;\n"
+    "  signal wr_mst_wrep_valid      : std_logic;\n"
+    "  signal wr_mst_wrep_ready      : std_logic;\n"
+    "  signal wr_mst_wrep_ok         : std_logic;\n"
+    "\n"
     "begin\n"
     "\n"
     "  -- Active low reset\n"

diff --git a/codegen/cpp/fletchgen/src/fletchgen/top/sim.cc b/codegen/cpp/fletchgen/src/fletchgen/top/sim.cc
@@ -266,34 +266,46 @@ std::string GenerateSimTop(const Design &design,
                     "    wreq_ready                  => bus_wreq_ready,\n"
                     "    wreq_addr                   => bus_wreq_addr,\n"
                     "    wreq_len                    => bus_wreq_len,\n"
+                    "    wreq_last                   => bus_wreq_last,\n"
                     "    wdat_valid                  => bus_wdat_valid,\n"
                     "    wdat_ready                  => bus_wdat_ready,\n"
                     "    wdat_data                   => bus_wdat_data,\n"
                     "    wdat_strobe                 => bus_wdat_strobe,\n"
-                    "    wdat_last                   => bus_wdat_last\n"
+                    "    wdat_last                   => bus_wdat_last,\n"
+                    "    wrep_valid                  => bus_wrep_valid,\n"
+                    "    wrep_ready                  => bus_wrep_ready,\n"
+                    "    wrep_ok                     => bus_wrep_ok\n"
                     "  );");
 
     t.Replace("MST_WREQ_DECLARE",
               "      wr_mst_wreq_valid         : out std_logic;\n"
               "      wr_mst_wreq_ready         : in std_logic;\n"
               "      wr_mst_wreq_addr          : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
               "      wr_mst_wreq_len           : out std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
+              "      wr_mst_wreq_last          : out std_logic;\n"
               "      wr_mst_wdat_valid         : out std_logic;\n"
               "      wr_mst_wdat_ready         : in std_logic;\n"
               "      wr_mst_wdat_data          : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
               "      wr_mst_wdat_strobe        : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
-              "      wr_mst_wdat_last          : out std_logic;");
+              "      wr_mst_wdat_last          : out std_logic;"
+              "      wr_mst_wrep_valid         : in  std_logic;\n"
+              "      wr_mst_wrep_ready         : out std_logic;\n"
+              "      wr_mst_wrep_ok            : in  std_logic;\n");
 
     t.Replace("MST_WREQ_INSTANTIATE",
               "      wr_mst_wreq_valid         => bus_wreq_valid,\n"
               "      wr_mst_wreq_ready         => bus_wreq_ready,\n"
               "      wr_mst_wreq_addr          => bus_wreq_addr,\n"
               "      wr_mst_wreq_len           => bus_wreq_len,\n"
+              "      wr_mst_wreq_last          => bus_wreq_last,\n"
               "      wr_mst_wdat_valid         => bus_wdat_valid,\n"
               "      wr_mst_wdat_ready         => bus_wdat_ready,\n"
               "      wr_mst_wdat_data          => bus_wdat_data,\n"
               "      wr_mst_wdat_strobe        => bus_wdat_strobe,\n"
-              "      wr_mst_wdat_last          => bus_wdat_last,");
+              "      wr_mst_wdat_last          => bus_wdat_last,\n"
+              "      wr_mst_wrep_valid         => bus_wrep_valid,\n"
+              "      wr_mst_wrep_ready         => bus_wrep_ready,\n"
+              "      wr_mst_wrep_ok            => bus_wrep_ok,");
   } else {
     t.Replace("BUS_WRITE_SLAVE_MOCK", "");
     t.Replace("MST_WREQ_DECLARE", "");

diff --git a/codegen/cpp/fletchgen/src/fletchgen/top/sim_template.h b/codegen/cpp/fletchgen/src/fletchgen/top/sim_template.h
@@ -157,6 +157,7 @@ static char sim_source[] =
     "  signal bus_rdat_valid         : std_logic;\n"
     "  signal bus_rdat_ready         : std_logic;\n"
     "  signal bus_wreq_addr          : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
+    "  signal bus_wreq_last          : std_logic;\n"
     "  signal bus_wreq_len           : std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
     "  signal bus_wreq_valid         : std_logic;\n"
     "  signal bus_wreq_ready         : std_logic;\n"
@@ -165,6 +166,9 @@ static char sim_source[] =
     "  signal bus_wdat_last          : std_logic;\n"
     "  signal bus_wdat_valid         : std_logic;\n"
     "  signal bus_wdat_ready         : std_logic;\n"
+    "  signal bus_wrep_ok            : std_logic;\n"
+    "  signal bus_wrep_valid         : std_logic;\n"
+    "  signal bus_wrep_ready         : std_logic;\n"
     "\n"
     "  procedure mmio_write32 (constant idx    : in  natural;\n"
     "                          constant data   : in  std_logic_vector(31 downto 0);\n"

diff --git a/codegen/test/primmap/Makefile b/codegen/test/primmap/Makefile
@@ -1,7 +1,8 @@
 .PHONY: clean sim
 
 all:
-	fletchgen -r twoprimread.rb -i twoprimwrite.as -s memory.srec -l dot vhdl --sim --regs c:8:add:0x01 s:32:sum
+	python3 generate-input.py
+	fletchgen -r in.rb -i out.as -s memory.srec -l vhdl dot --sim --regs c:8:add:0x01 s:32:sum
 
 sim:
 	rm -f vhdl/Kernel.gen.vhd

diff --git a/codegen/test/primmap/generate-input.py b/codegen/test/primmap/generate-input.py
@@ -0,0 +1,21 @@
+import pyarrow as pa
+
+# Create a field that can be interpreted as a "listprim" ArrayReader/Writer
+input_schema = pa.schema([pa.field('A', pa.int8(), nullable=False),
+                          pa.field('B', pa.int8(), nullable=False)])
+input_schema = input_schema.with_metadata({b'fletcher_mode': b'read', b'fletcher_name': b'R'})
+
+output_schema = pa.schema([pa.field('C', pa.int8(), nullable=False),
+                           pa.field('D', pa.int8(), nullable=False)])
+output_schema = output_schema.with_metadata({b'fletcher_mode': b'write', b'fletcher_name': b'W'})
+
+batch_data = [pa.array([1, -3, 3, -7], pa.int8()),
+              pa.array([4, 2, -6, -9], pa.int8())]
+
+input_batch = pa.RecordBatch.from_arrays(batch_data, schema=input_schema)
+writer_in = pa.RecordBatchFileWriter('in.rb', input_schema)
+writer_in.write(input_batch)
+writer_in.close()
+
+serialized_out_schema = output_schema.serialize()
+pa.output_stream('out.as').write(serialized_out_schema)
diff --git a/codegen/test/primmap/in.rb b/codegen/test/primmap/in.rb
diff --git a/codegen/test/primmap/out.as b/codegen/test/primmap/out.as
diff --git a/codegen/test/primmap/twoprimread.rb b/codegen/test/primmap/twoprimread.rb
diff --git a/codegen/test/primmap/twoprimwrite.as b/codegen/test/primmap/twoprimwrite.as
diff --git a/codegen/test/primmap_simple/.gitignore b/codegen/test/primmap_simple/.gitignore
@@ -0,0 +1,11 @@
+work
+vsim.wlf
+transcript
+dot/
+vhdmmio-doc/
+*.gen.*
+fletchgen.mmio.yaml
+memory.srec
+vhdmmio.log
+in.rb
+out.as
diff --git a/codegen/test/primmap_simple/generate-input.py b/codegen/test/primmap_simple/generate-input.py
@@ -0,0 +1,18 @@
+import pyarrow as pa
+
+# Input schema and batch
+in_schema = pa.schema([pa.field('number', pa.int64(), nullable=False)])
+in_schema = in_schema.with_metadata({b'fletcher_mode': b'read',
+                                     b'fletcher_name': b'in'})
+in_data = [pa.array([1, -3, 3, -7])]
+in_batch = pa.RecordBatch.from_arrays(in_data, schema=in_schema)
+# Create an Arrow RecordBatchFileWriter.
+writer = pa.RecordBatchFileWriter('in.rb', in_schema)
+writer.write(in_batch)
+writer.close()
+
+# Output schema and batch
+out_schema = pa.schema([pa.field('number', pa.int64(), nullable=False)])
+out_schema = out_schema.with_metadata({b'fletcher_mode': b'write',
+                                       b'fletcher_name': b'out'})
+pa.output_stream('out.as').write(out_schema.serialize())
diff --git a/examples/stringwrite/hardware/Makefile b/examples/stringwrite/hardware/Makefile
@@ -1,7 +1,7 @@
 .PHONY: sim clean
 
 all:
-	python generate-schema.py
+	python3 generate-input.py
 	fletchgen -i stringwrite.as -t memory.srec -l vhdl dot --sim --regs c:32:strlen_min c:32:strlen_mask
 
 sim:

diff --git a/...s/stringwrite/hardware/generate-schema.py → ...es/stringwrite/hardware/generate-input.py b/...s/stringwrite/hardware/generate-schema.py → ...es/stringwrite/hardware/generate-input.py