Write a System Verilog code to implement a 10 bit carry look ahead adder

[cuber2116]

Write a code in final_adder.sv to implement a 10 bit CLA which is to be used for a 5x5 Multiplier.
Implementing adder+Working Test bench = 50 points

[Ruchavw]

can you please assign

[cuber2116]

!assign @Ruchavw 45m

[Sami9692]

can u pls assign

[cuber2116]

!assign @Sami9692 60

[cuber2116]

@Sami9692 PR after finishing, you have 60 mins

[bunsamosa-bot]

Hey @cuber2116! The timer for the @Sami9692 to work on the issue has finished, deassign and assign a new contributor or extend the current timer. Contact maintainer leads if inactive @DedLad @polarhive @achyuthcodes30

[cuber2116]

@Sami9692 you have 15 more mins

[cuber2116]

!assign @Sami9692 15

[Sami9692]

I have PR ed alreadyy

[cuber2116]

checking now

[cuber2116]

@Sami9692 can you come to class 004?

[Sami9692]

sure..

[Ruchavw]

can I get assigned?

[aakanksha-p-3]

can i get assigned

[cuber2116]

@aakanksha-p-3 please try #1 or #2, this has already been solved

[cuber2116]

#1 or #3*