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‎README.md

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@@ -16,20 +16,6 @@ Portable C implementations of the [AEGIS](https://datatracker.ietf.org/doc/draft
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- Unauthenticated encryption and decryption (not recommended - only implemented for specific protocols)
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- Deterministic pseudorandom stream generation.
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## Key differences between AEGIS variants
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| **Feature** | **AEGIS-128L** | **AEGIS-256** | **AEGIS-128X2** | **AEGIS-128X4** | **AEGIS-256X2** | **AEGIS-256X4** |
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| -------------------- | --------------------------------------------------------------------- | -------------------------------------------- | ----------------------------------------------- | ----------------------------------------------- | ----------------------------------------------- | ----------------------------------------------- |
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| **Key Length** | 128 bits | 256 bits | 128 bits | 128 bits | 256 bits | 256 bits |
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| **Nonce Length** | 128 bits | 256 bits | 128 bits | 128 bits | 256 bits | 256 bits |
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| **State Size** | 1024 bits (8 x 128-bit blocks) | 768 bits (6 x 128-bit blocks) | 2048 bits (2 x 1024-bit states) | 4096 bits (4 x 1024-bit states) | 1536 bits (2 x 768-bit states) | 3072 bits (4 x 768-bit states) |
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| **Input Rate** | 256 bits per update | 128 bits per update | 512 bits per update | 1024 bits per update | 256 bits per update | 512 bits per update |
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| **Parallelism** | None | None | 2 parallel lanes | 4 parallel lanes | 2 parallel lanes | 4 parallel lanes |
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| **Performance** | High on standard CPUs | High on standard CPUs | Higher on CPUs with AVX2 | Higher on CPUs with AVX-512 | Higher on CPUs with AVX2 | Higher on CPUs with AVX-512 |
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| **Target Use Case** | Standard applications | Applications requiring higher security | High-throughput applications on modern hardware | High-throughput applications on modern hardware | High-security applications with modern hardware | High-security applications with modern hardware |
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| **Security Level** | 128-bit security | 256-bit security | 128-bit security | 128-bit security | 256-bit security | 256-bit security |
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| **Special Features** | Optimized for high performance on standard CPUs with AES instructions | Optimized for high security with larger keys | Parallelized version of AEGIS-128L | Parallelized version of AEGIS-128L | Parallelized version of AEGIS-256 | Parallelized version of AEGIS-256 |
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## Installation
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Note that the compiler makes a difference. Zig (or a recent `clang` with target-specific options such as `-march=native`) produces more efficient code than `gcc`.
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[Other AEGIS implementations](https://github.com/cfrg/draft-irtf-cfrg-aegis-aead?tab=readme-ov-file#known-implementations) are also available for most programming languages.
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## Key differences between AEGIS variants
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| **Feature** | **AEGIS-128L** | **AEGIS-256** | **AEGIS-128X2** | **AEGIS-128X4** | **AEGIS-256X2** | **AEGIS-256X4** |
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| -------------------- | --------------------------------------------------------------------- | -------------------------------------------- | ----------------------------------------------- | ----------------------------------------------- | ----------------------------------------------- | ----------------------------------------------- |
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| **Key Length** | 128 bits | 256 bits | 128 bits | 128 bits | 256 bits | 256 bits |
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| **Nonce Length** | 128 bits | 256 bits | 128 bits | 128 bits | 256 bits | 256 bits |
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| **State Size** | 1024 bits (8 x 128-bit blocks) | 768 bits (6 x 128-bit blocks) | 2048 bits (2 x 1024-bit states) | 4096 bits (4 x 1024-bit states) | 1536 bits (2 x 768-bit states) | 3072 bits (4 x 768-bit states) |
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| **Input Rate** | 256 bits per update | 128 bits per update | 512 bits per update | 1024 bits per update | 256 bits per update | 512 bits per update |
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| **Parallelism** | None | None | 2 parallel lanes | 4 parallel lanes | 2 parallel lanes | 4 parallel lanes |
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| **Performance** | High on standard CPUs | High on standard CPUs | Higher on CPUs with AVX2 | Higher on CPUs with AVX-512 | Higher on CPUs with AVX2 | Higher on CPUs with AVX-512 |
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| **Target Use Case** | Standard applications | Applications requiring higher security | High-throughput applications on modern hardware | High-throughput applications on modern hardware | High-security applications with modern hardware | High-security applications with modern hardware |
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| **Security Level** | 128-bit security | 256-bit security | 128-bit security | 128-bit security | 256-bit security | 256-bit security |
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| **Special Features** | Optimized for high performance on standard CPUs with AES instructions | Optimized for high security with larger keys | Parallelized version of AEGIS-128L | Parallelized version of AEGIS-128L | Parallelized version of AEGIS-256 | Parallelized version of AEGIS-256 |
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## Benchmark results
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AEGIS is very fast on CPUs with parallel execution pipelines and AES support.

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