From 17fbe5ba4a1b94155dc6231a07db46036cefe4c4 Mon Sep 17 00:00:00 2001
From: Salvatore Dipietro <dipiets@amazon.com>
Date: Tue, 20 May 2025 14:46:56 -0700
Subject: [PATCH] Adding 'sb' instruction to spin_delay() for ARM v8.5 onward

---
 src/include/aerospike/as_arch.h | 34 ++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/src/include/aerospike/as_arch.h b/src/include/aerospike/as_arch.h
index 82ac1098..c6bcf4f5 100644
--- a/src/include/aerospike/as_arch.h
+++ b/src/include/aerospike/as_arch.h
@@ -34,7 +34,39 @@
 
 #elif defined __aarch64__
 
-#define as_arch_pause() asm volatile("isb" : : : "memory")
+#if defined(__linux__) && (defined(__GNUC__) || defined(__clang__))
+#include <sys/auxv.h>
+
+#ifndef HWCAP_SB
+#define HWCAP_SB		(1 << 29)
+#endif  // HWCAP_SB
+
+static inline void as_arch_pause(void)
+{
+    static int use_spin_delay_sb = -1;
+
+	if (__builtin_expect(use_spin_delay_sb == 1, 1)) {
+		asm volatile(".inst 0xd50330ff" : : : "memory");  // SB instruction encoding
+	}
+	else if (use_spin_delay_sb == 0) {
+		asm volatile("isb" : : : "memory");
+	}
+	else {
+		// Initialize variable and check if SB is supported
+		if (getauxval(AT_HWCAP) & HWCAP_SB)
+			use_spin_delay_sb = 1;
+		else 
+			use_spin_delay_sb = 0;
+	}
+}
+#else
+static inline void as_arch_pause(void)
+{
+    asm volatile("isb" : : : "memory");
+}
+#endif  // __linux__ __GNUC__ __clang__
+
+#define as_arch_pause() as_arch_pause()
 
 #endif