axis_ll_bridge.v has some problems

[deleteTh]

Hi,Alex.I'm a little confused. In this code, the timing logic uses blocking assignments.

[deleteTh]

always @(posedge clk) begin
if (rst) begin
last_tlast = 1'b1;
end else begin
if (s_axis_tvalid && s_axis_tready) last_tlast = s_axis_tlast;
end
end