RTL Linting with Verilator -Wall

[chili-chips-ba]

chili-chips-ba/wireguard-fpga#14 (comment)

[alexforencich]

FYI this library is being deprecated, to be superseded by https://github.com/fpganinja/taxi . Note that the license is different (CERN OHL strongly reciprocal with an option for a commercial license, instead of MIT/BSD). Since it's written in System Verilog and I'm using Verilator as the simulator, many of these lint issues have already been fixed.