GitHub - allanliyang/Verilog-Code-374: Verilog code written for a mini-RISC style CPU as part of a school project

Name		Name	Last commit message	Last commit date
Latest commit History 182 Commits
CPUPhase1		CPUPhase1
CPUPhase2		CPUPhase2
CPUPhase3		CPUPhase3
Tutorial		Tutorial
db		db
incremental_db		incremental_db
output_files		output_files
ALU.v		ALU.v
Bus.v		Bus.v
CPUPhase4.qpf		CPUPhase4.qpf
CPUPhase4.qsf		CPUPhase4.qsf
CPUPhase4.qws		CPUPhase4.qws
CPUPhase4_nativelink_simulation.rpt		CPUPhase4_nativelink_simulation.rpt
ClockDivider.v		ClockDivider.v
ConFFLogic.v		ConFFLogic.v
ControlUnit.v		ControlUnit.v
Datapath.v		Datapath.v
InPort.v		InPort.v
MAR.v		MAR.v
MDR.v		MDR.v
R0.v		R0.v
RAM.v		RAM.v
RAMoutput.txt		RAMoutput.txt
SelectEncode.v		SelectEncode.v
SevenSegmentEncoder.v		SevenSegmentEncoder.v
datapath_tb.v		datapath_tb.v
opcode.txt		opcode.txt
ram_FP.txt		ram_FP.txt
register32bit.v		register32bit.v