From c61ecfe5cfdcea111e343e76df31a1bd9b5ecd5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tobias=20M=C3=BCller?= Date: Fri, 26 Mar 2021 09:54:58 +0100 Subject: [PATCH] Add RGMIIResource --- nmigen_boards/resources/interface.py | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/nmigen_boards/resources/interface.py b/nmigen_boards/resources/interface.py index 0e0118ae..5a9347ef 100644 --- a/nmigen_boards/resources/interface.py +++ b/nmigen_boards/resources/interface.py @@ -3,7 +3,7 @@ __all__ = [ "UARTResource", "IrDAResource", "SPIResource", "I2CResource", - "DirectUSBResource", "ULPIResource" + "DirectUSBResource", "ULPIResource", "RGMIIResource" ] @@ -130,3 +130,20 @@ def ULPIResource(*args, data, clk, dir, nxt, stp, rst=None, if attrs is not None: io.append(attrs) return Resource.family(*args, default_name="usb", ios=io) + + +def RGMIIResource(*args, txc, txd, tx_ctl, rxc, rxd, rx_ctl, mdc, mdio, attrs=None, conn=None): + io = [] + + io.append(Subsignal("txc", Pins(txc, dir="o", conn=conn, assert_width=1))) + io.append(Subsignal("txd", Pins(txd, dir="o", conn=conn, assert_width=4))) + io.append(Subsignal("tx_ctl", Pins(txc, dir="o", conn=conn, assert_width=1))) + io.append(Subsignal("rxc", Pins(rxc, dir="i", conn=conn, assert_width=1))) + io.append(Subsignal("rxd", Pins(rxd, dir="i", conn=conn, assert_width=4))) + io.append(Subsignal("rx_ctl", Pins(txc, dir="i", conn=conn, assert_width=1))) + io.append(Subsignal("mdc", Pins(mdc, dir="o", conn=conn, assert_width=1))) + io.append(Subsignal("mdio", Pins(mdio, dir="io", conn=conn, assert_width=1))) + + if attrs is not None: + io.append(attrs) + return Resource.family(*args, default_name="rgmii", ios=io) \ No newline at end of file