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library: intel: avl_dacfifo: Make avl interface parametrizable
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
1 parent b2e4059 commit 27599bd

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+38
-25
lines changed

4 files changed

+38
-25
lines changed

‎library/intel/avl_dacfifo/avl_dacfifo.v

Lines changed: 19 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -36,7 +36,7 @@
3636
`timescale 1ns/100ps
3737

3838
module avl_dacfifo #(
39-
39+
parameter ACTIVE_LOW_RESET = 0,
4040
parameter DAC_DATA_WIDTH = 64,
4141
parameter DAC_MEM_ADDRESS_WIDTH = 8,
4242
parameter DMA_DATA_WIDTH = 64,
@@ -102,9 +102,9 @@ module avl_dacfifo #(
102102
wire dma_ready_bypass_s;
103103
wire avl_read_s;
104104
wire avl_write_s;
105-
wire [ 24:0] avl_wr_address_s;
106-
wire [ 24:0] avl_rd_address_s;
107-
wire [ 24:0] avl_last_address_s;
105+
wire [(AVL_ADDRESS_WIDTH-1):0] avl_wr_address_s;
106+
wire [(AVL_ADDRESS_WIDTH-1):0] avl_rd_address_s;
107+
wire [(AVL_ADDRESS_WIDTH-1):0] avl_last_address_s;
108108
wire [ 6:0] avl_last_burstcount_s;
109109
wire [ 7:0] dma_last_beats_s;
110110
wire [ 6:0] avl_wr_burstcount_s;
@@ -120,9 +120,19 @@ module avl_dacfifo #(
120120
wire dac_dunf_fifo_s;
121121
wire dac_dunf_bypass_s;
122122

123+
wire avl_reset_s;
124+
125+
generate if (ACTIVE_LOW_RESET == 1) begin
126+
assign avl_reset_s = ~avl_reset;
127+
end else begin
128+
assign avl_reset_s = avl_reset;
129+
end
130+
endgenerate
131+
123132
avl_dacfifo_wr #(
124133
.AVL_DATA_WIDTH (AVL_DATA_WIDTH),
125134
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
135+
.AVL_ADDRESS_WIDTH (AVL_ADDRESS_WIDTH),
126136
.AVL_DDR_BASE_ADDRESS (AVL_BASE_ADDRESS),
127137
.DMA_MEM_ADDRESS_WIDTH(DMA_MEM_ADDRESS_WIDTH),
128138
.AVL_BURST_LENGTH (AVL_BURST_LENGTH)
@@ -138,7 +148,7 @@ module avl_dacfifo #(
138148
.avl_last_address (avl_last_address_s),
139149
.avl_last_burstcount (avl_last_burstcount_s),
140150
.avl_clk (avl_clk),
141-
.avl_reset (avl_reset),
151+
.avl_reset (avl_reset_s),
142152
.avl_address (avl_wr_address_s),
143153
.avl_burstcount (avl_wr_burstcount_s),
144154
.avl_byteenable (avl_wr_byteenable_s),
@@ -151,6 +161,7 @@ module avl_dacfifo #(
151161
avl_dacfifo_rd #(
152162
.AVL_DATA_WIDTH(AVL_DATA_WIDTH),
153163
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
164+
.AVL_ADDRESS_WIDTH (AVL_ADDRESS_WIDTH),
154165
.AVL_DDR_BASE_ADDRESS(AVL_BASE_ADDRESS),
155166
.AVL_DDR_ADDRESS_LIMIT(AVL_ADDRESS_LIMIT),
156167
.DAC_MEM_ADDRESS_WIDTH(DAC_MEM_ADDRESS_WIDTH),
@@ -163,7 +174,7 @@ module avl_dacfifo #(
163174
.dac_xfer_req(dac_xfer_fifo_out_s),
164175
.dac_dunf(dac_dunf_fifo_s),
165176
.avl_clk(avl_clk),
166-
.avl_reset(avl_reset),
177+
.avl_reset(avl_reset_s),
167178
.avl_address(avl_rd_address_s),
168179
.avl_burstcount(avl_rd_burstcount_s),
169180
.avl_byteenable(avl_rd_byteenable_s),
@@ -182,7 +193,7 @@ module avl_dacfifo #(
182193
assign avl_xfer_wren_s = ~avl_xfer_in_s;
183194

184195
always @(posedge avl_clk) begin
185-
if (avl_reset == 1'b1) begin
196+
if (avl_reset_s == 1'b1) begin
186197
avl_address <= 0;
187198
avl_burstcount <= 0;
188199
avl_byteenable <= 0;

‎library/intel/avl_dacfifo/avl_dacfifo_hw.tcl

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2017-2023, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -22,6 +22,7 @@ ad_ip_files avl_dacfifo [list\
2222
# parameters
2323

2424
ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
25+
ad_ip_parameter ACTIVE_LOW_RESET INTEGER 0
2526
ad_ip_parameter DAC_DATA_WIDTH INTEGER 64
2627
ad_ip_parameter DAC_MEM_ADDRESS_WIDTH INTEGER 8
2728
ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
@@ -30,7 +31,7 @@ ad_ip_parameter AVL_DATA_WIDTH INTEGER 512
3031
ad_ip_parameter AVL_ADDRESS_WIDTH INTEGER 25
3132
ad_ip_parameter AVL_BURST_LENGTH INTEGER 127
3233
ad_ip_parameter AVL_BASE_ADDRESS INTEGER 0
33-
ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x800000
34+
ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x80000000
3435

3536
# interfaces
3637

@@ -63,15 +64,15 @@ set_interface_property avl_reset associatedclock avl_clock
6364
add_interface_port avl_reset avl_reset reset input 1
6465

6566
add_interface amm_ddr avalon master
66-
add_interface_port amm_ddr avl_address address output 25
67-
add_interface_port amm_ddr avl_burstcount burstcount output 7
68-
add_interface_port amm_ddr avl_byteenable byteenable output 64
69-
add_interface_port amm_ddr avl_read read output 1
70-
add_interface_port amm_ddr avl_readdata readdata input 512
67+
add_interface_port amm_ddr avl_address address output AVL_ADDRESS_WIDTH
68+
add_interface_port amm_ddr avl_burstcount burstcount output 7
69+
add_interface_port amm_ddr avl_byteenable byteenable output AVL_DATA_WIDTH/8
70+
add_interface_port amm_ddr avl_read read output 1
71+
add_interface_port amm_ddr avl_readdata readdata input AVL_DATA_WIDTH
7172
add_interface_port amm_ddr avl_readdata_valid readdatavalid input 1
72-
add_interface_port amm_ddr avl_ready waitrequest_n input 1
73-
add_interface_port amm_ddr avl_write write output 1
74-
add_interface_port amm_ddr avl_writedata writedata output 512
73+
add_interface_port amm_ddr avl_ready waitrequest_n input 1
74+
add_interface_port amm_ddr avl_write write output 1
75+
add_interface_port amm_ddr avl_writedata writedata output AVL_DATA_WIDTH
7576

7677
set_interface_property amm_ddr associatedClock avl_clock
7778
set_interface_property amm_ddr associatedReset avl_reset
@@ -140,4 +141,3 @@ proc p_avl_dacfifo_elab {} {
140141
set_instance_parameter_value ad_mem_asym_bypass B_DATA_WIDTH $m_dac_data_width
141142

142143
}
143-

‎library/intel/avl_dacfifo/avl_dacfifo_rd.v

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -39,6 +39,7 @@ module avl_dacfifo_rd #(
3939

4040
parameter AVL_DATA_WIDTH = 512,
4141
parameter DAC_DATA_WIDTH = 64,
42+
parameter AVL_ADDRESS_WIDTH = 25,
4243
parameter AVL_BURST_LENGTH = 127,
4344
parameter AVL_DDR_BASE_ADDRESS = 0,
4445
parameter AVL_DDR_ADDRESS_LIMIT = 33554432,
@@ -53,15 +54,15 @@ module avl_dacfifo_rd #(
5354

5455
input avl_clk,
5556
input avl_reset,
56-
output reg [24:0] avl_address,
57+
output reg [(AVL_ADDRESS_WIDTH-1):0] avl_address,
5758
output reg [ 6:0] avl_burstcount,
5859
output [63:0] avl_byteenable,
5960
input avl_waitrequest,
6061
input avl_readdatavalid,
6162
output reg avl_read,
6263
input [AVL_DATA_WIDTH-1:0] avl_data,
6364

64-
input [24:0] avl_last_address,
65+
input [(AVL_ADDRESS_WIDTH-1):0] avl_last_address,
6566
input [ 6:0] avl_last_burstcount,
6667
input [ 7:0] dma_last_beats,
6768
input avl_xfer_req_in,

‎library/intel/avl_dacfifo/avl_dacfifo_wr.v

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -39,6 +39,7 @@ module avl_dacfifo_wr #(
3939

4040
parameter AVL_DATA_WIDTH = 512,
4141
parameter DMA_DATA_WIDTH = 64,
42+
parameter AVL_ADDRESS_WIDTH = 25,
4243
parameter AVL_BURST_LENGTH = 128,
4344
parameter AVL_DDR_BASE_ADDRESS = 0,
4445
parameter AVL_DDR_ADDRESS_LIMIT = 33554432,
@@ -56,14 +57,14 @@ module avl_dacfifo_wr #(
5657

5758
input avl_clk,
5859
input avl_reset,
59-
output reg [24:0] avl_address,
60+
output reg [(AVL_ADDRESS_WIDTH-1):0] avl_address,
6061
output reg [ 6:0] avl_burstcount,
6162
output [63:0] avl_byteenable,
6263
input avl_waitrequest,
6364
output reg avl_write,
6465
output reg [AVL_DATA_WIDTH-1:0] avl_data,
6566

66-
output reg [24:0] avl_last_address,
67+
output reg [(AVL_ADDRESS_WIDTH-1):0] avl_last_address,
6768
output reg [ 6:0] avl_last_burstcount,
6869
output reg avl_xfer_req_out,
6970
input avl_xfer_req_in

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