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adrv9371x: Replace dacfifo with data_offload
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
1 parent d87c0d7 commit 55fa0de

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10 files changed

+73
-64
lines changed

10 files changed

+73
-64
lines changed

‎projects/adrv9371x/common/adrv9371x_bd.tcl

Lines changed: 24 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -41,18 +41,17 @@ set RX_OS_SAMPLE_WIDTH 16 ; # N/NP
4141
set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 32 / \
4242
($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
4343

44-
set dac_fifo_name axi_ad9371_dacfifo
44+
set dac_offload_name ad9371_data_offload
4545
set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
4646
set dac_dma_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
4747

4848
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
4949
source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
50+
source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
5051

5152
# ad9371
5253

5354
create_bd_port -dir I ref_clk
54-
55-
create_bd_port -dir I dac_fifo_bypass
5655
create_bd_port -dir I adc_fir_filter_active
5756
create_bd_port -dir I dac_fir_filter_active
5857

@@ -102,7 +101,16 @@ ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_2D_TRANSFER 0
102101
ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
103102
ad_ip_parameter axi_ad9371_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
104103

105-
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
104+
ad_data_offload_create $dac_offload_name \
105+
1 \
106+
$dac_offload_type \
107+
$dac_offload_size \
108+
$dac_dma_data_width \
109+
$dac_data_width \
110+
$plddr_offload_axi_data_width
111+
112+
ad_ip_parameter $dac_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
113+
ad_connect $dac_offload_name/sync_ext GND
106114

107115
# adc peripherals
108116

@@ -254,10 +262,6 @@ for {set i 0} {$i < $MAX_RX_OS_NUM_OF_LANES} {incr i} {
254262
ad_xcvrpll axi_ad9371_rx_os_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_$ch
255263
}
256264

257-
# dma clock & reset
258-
259-
ad_connect $sys_dma_reset axi_ad9371_dacfifo/dma_rst
260-
261265
# connections (dac)
262266

263267
ad_connect axi_ad9371_tx_clkgen/clk_0 tx_ad9371_tpl_core/link_clk
@@ -266,8 +270,14 @@ ad_connect axi_ad9371_tx_jesd/tx_data tx_ad9371_tpl_core/link
266270
ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_tx_upack/clk
267271
ad_connect ad9371_tx_device_clk_rstgen/peripheral_reset util_ad9371_tx_upack/reset
268272

269-
ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
270-
ad_connect ad9371_tx_device_clk_rstgen/peripheral_reset axi_ad9371_dacfifo/dac_rst
273+
ad_connect $sys_dma_clk $dac_offload_name/s_axis_aclk
274+
ad_connect $sys_dma_resetn $dac_offload_name/s_axis_aresetn
275+
ad_connect $sys_dma_clk axi_ad9371_tx_dma/m_axis_aclk
276+
ad_connect $sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
277+
278+
ad_connect axi_ad9371_tx_clkgen/clk_0 $dac_offload_name/m_axis_aclk
279+
ad_connect ad9371_tx_device_clk_rstgen/peripheral_aresetn $dac_offload_name/m_axis_aresetn
280+
ad_connect util_ad9371_tx_upack/s_axis $dac_offload_name/m_axis
271281

272282
ad_connect tx_fir_interpolator/aclk axi_ad9371_tx_clkgen/clk_0
273283

@@ -295,21 +305,9 @@ if {$TX_NUM_OF_CONVERTERS <= 2} {
295305

296306
ad_connect tx_fir_interpolator/active dac_fir_filter_active
297307

298-
# TODO: Add streaming AXI interface for DAC FIFO
299-
ad_connect util_ad9371_tx_upack/s_axis_valid VCC
300-
ad_connect util_ad9371_tx_upack/s_axis_ready axi_ad9371_dacfifo/dac_valid
301-
ad_connect util_ad9371_tx_upack/s_axis_data axi_ad9371_dacfifo/dac_data
302-
303-
ad_connect $sys_dma_clk axi_ad9371_dacfifo/dma_clk
304-
ad_connect $sys_dma_clk axi_ad9371_tx_dma/m_axis_aclk
305-
ad_connect axi_ad9371_dacfifo/dma_valid axi_ad9371_tx_dma/m_axis_valid
306-
ad_connect axi_ad9371_dacfifo/dma_data axi_ad9371_tx_dma/m_axis_data
307-
ad_connect axi_ad9371_dacfifo/dma_ready axi_ad9371_tx_dma/m_axis_ready
308-
ad_connect axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
309-
ad_connect axi_ad9371_dacfifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
310-
ad_connect axi_ad9371_dacfifo/dac_dunf tx_ad9371_tpl_core/dac_dunf
311-
ad_connect axi_ad9371_dacfifo/bypass dac_fifo_bypass
312-
ad_connect $sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
308+
ad_connect $dac_offload_name/s_axis axi_ad9371_tx_dma/m_axis
309+
ad_connect $dac_offload_name/init_req axi_ad9371_tx_dma/m_axis_xfer_req
310+
ad_connect tx_ad9371_tpl_core/dac_dunf util_ad9371_tx_upack/fifo_rd_underflow
313311

314312
# connections (adc)
315313

@@ -371,6 +369,7 @@ ad_cpu_interconnect 0x44A80000 axi_ad9371_tx_xcvr
371369
ad_cpu_interconnect 0x43C00000 axi_ad9371_tx_clkgen
372370
ad_cpu_interconnect 0x44A90000 axi_ad9371_tx_jesd
373371
ad_cpu_interconnect 0x7c420000 axi_ad9371_tx_dma
372+
ad_cpu_interconnect 0x7c430000 $dac_offload_name
374373
ad_cpu_interconnect 0x44A60000 axi_ad9371_rx_xcvr
375374
ad_cpu_interconnect 0x43C10000 axi_ad9371_rx_clkgen
376375
ad_cpu_interconnect 0x44AA0000 axi_ad9371_rx_jesd

‎projects/adrv9371x/kcu105/Makefile

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################
@@ -8,13 +8,14 @@ PROJECT_NAME := adrv9371x_kcu105
88

99
M_DEPS += ../common/adrv9371x_bd.tcl
1010
M_DEPS += ../../scripts/adi_pd.tcl
11-
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
1211
M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc
1312
M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl
1413
M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
1514
M_DEPS += ../../common/kcu105/kcu105_system_lutram_constr.xdc
1615
M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
1716
M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
17+
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
18+
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
1819
M_DEPS += ../../../library/util_cdc/sync_bits.v
1920
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
2021
M_DEPS += ../../../library/common/util_pulse_gen.v
@@ -24,14 +25,16 @@ M_DEPS += ../../../library/common/ad_bus_mux.v
2425
LIB_DEPS += axi_clkgen
2526
LIB_DEPS += axi_dmac
2627
LIB_DEPS += axi_sysid
28+
LIB_DEPS += data_offload
2729
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
2830
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
2931
LIB_DEPS += jesd204/axi_jesd204_rx
3032
LIB_DEPS += jesd204/axi_jesd204_tx
3133
LIB_DEPS += jesd204/jesd204_rx
3234
LIB_DEPS += jesd204/jesd204_tx
3335
LIB_DEPS += sysid_rom
34-
LIB_DEPS += util_dacfifo
36+
LIB_DEPS += util_do_ram
37+
LIB_DEPS += util_hbm
3538
LIB_DEPS += util_pack/util_cpack2
3639
LIB_DEPS += util_pack/util_upack2
3740
LIB_DEPS += xilinx/axi_adxcvr

‎projects/adrv9371x/kcu105/system_bd.tcl

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,16 @@
11
###############################################################################
2-
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
## FIFO depth is 8Mb - 500k samples
7-
set dac_fifo_address_width 16
8-
9-
## NOTE: With this configuration the #36Kb BRAM utilization is at ~68%
6+
## Offload attributes
7+
set dac_offload_type 0 ; ## BRAM
8+
set dac_offload_size [expr 1*1024*1024] ; ## 1 MB
9+
set plddr_offload_axi_data_width 0
1010

1111
source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
1212
source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl
13-
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
13+
source ../common/adrv9371x_bd.tcl
1414
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
1515

1616
#system ID
@@ -27,14 +27,13 @@ S=$ad_project_params(TX_JESD_S)\
2727
RX_OS:M=$ad_project_params(RX_OS_JESD_M)\
2828
L=$ad_project_params(RX_OS_JESD_L)\
2929
S=$ad_project_params(RX_OS_JESD_S)\
30-
DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
30+
DAC_OFFLOAD:TYPE=$dac_offload_type\
31+
SIZE=$dac_offload_size"
3132

3233
sysid_gen_sys_init_file $sys_cstring
3334

3435
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 200
3536

36-
source ../common/adrv9371x_bd.tcl
37-
3837
ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 80
3938
ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_REFCLK_DIV 1
4039
ad_ip_parameter util_ad9371_xcvr CONFIG.CPLL_CFG0 0x67f8

‎projects/adrv9371x/kcu105/system_top.v

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -239,7 +239,6 @@ module system_top (
239239
assign gpio_i[63:60] = gpio_o[63:60];
240240

241241
system_wrapper i_system_wrapper (
242-
.dac_fifo_bypass (gpio_o[60]),
243242
.adc_fir_filter_active (gpio_o[61]),
244243
.dac_fir_filter_active (gpio_o[62]),
245244
.c0_ddr4_act_n (ddr4_act_n),

‎projects/adrv9371x/zc706/Makefile

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################
@@ -10,10 +10,12 @@ M_DEPS += ../common/adrv9371x_bd.tcl
1010
M_DEPS += ../../scripts/adi_pd.tcl
1111
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
1212
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
13-
M_DEPS += ../../common/zc706/zc706_plddr3_dacfifo_bd.tcl
13+
M_DEPS += ../../common/zc706/zc706_plddr3_data_offload_bd.tcl
1414
M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
1515
M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc
1616
M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl
17+
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
18+
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
1719
M_DEPS += ../../../library/util_cdc/sync_bits.v
1820
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
1921
M_DEPS += ../../../library/common/util_pulse_gen.v
@@ -25,17 +27,19 @@ LIB_DEPS += axi_dmac
2527
LIB_DEPS += axi_hdmi_tx
2628
LIB_DEPS += axi_spdif_tx
2729
LIB_DEPS += axi_sysid
30+
LIB_DEPS += data_offload
2831
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
2932
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
3033
LIB_DEPS += jesd204/axi_jesd204_rx
3134
LIB_DEPS += jesd204/axi_jesd204_tx
3235
LIB_DEPS += jesd204/jesd204_rx
3336
LIB_DEPS += jesd204/jesd204_tx
3437
LIB_DEPS += sysid_rom
38+
LIB_DEPS += util_do_ram
39+
LIB_DEPS += util_hbm
3540
LIB_DEPS += util_pack/util_cpack2
3641
LIB_DEPS += util_pack/util_upack2
3742
LIB_DEPS += xilinx/axi_adxcvr
38-
LIB_DEPS += xilinx/axi_dacfifo
3943
LIB_DEPS += xilinx/util_adxcvr
4044

4145
include ../../scripts/project-xilinx.mk

‎projects/adrv9371x/zc706/system_bd.tcl

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,20 @@
11
###############################################################################
2-
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2016-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
set dac_fifo_address_width 10
6+
## Offload attributes
7+
set dac_offload_type 1 ; ## PL_DDR
8+
set dac_offload_size [expr 1024*1024*1024] ; ## 1 GB
9+
set plddr_offload_axi_data_width 512
710

811
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
9-
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
12+
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_data_offload_bd.tcl
13+
source ../common/adrv9371x_bd.tcl
1014
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
1115

16+
ad_plddr_data_offload_create $dac_offload_name
17+
1218
#system ID
1319
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
1420
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
@@ -23,10 +29,9 @@ S=$ad_project_params(TX_JESD_S)\
2329
RX_OS:M=$ad_project_params(RX_OS_JESD_M)\
2430
L=$ad_project_params(RX_OS_JESD_L)\
2531
S=$ad_project_params(RX_OS_JESD_S)\
26-
DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
32+
DAC_OFFLOAD:TYPE=$dac_offload_type\
33+
SIZE=$dac_offload_size"
2734

2835
sysid_gen_sys_init_file $sys_cstring
2936

3037
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200
31-
32-
source ../common/adrv9371x_bd.tcl

‎projects/adrv9371x/zc706/system_top.v

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2016-2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -246,7 +246,6 @@ module system_top (
246246
assign gpio_i[63:60] = gpio_o[63:60];
247247

248248
system_wrapper i_system_wrapper (
249-
.dac_fifo_bypass (gpio_o[60]),
250249
.adc_fir_filter_active (gpio_o[61]),
251250
.dac_fir_filter_active (gpio_o[62]),
252251
.ddr3_addr (ddr3_addr),

‎projects/adrv9371x/zcu102/Makefile

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################
@@ -10,9 +10,10 @@ M_DEPS += ../common/adrv9371x_bd.tcl
1010
M_DEPS += ../../scripts/adi_pd.tcl
1111
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
1212
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
13-
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
1413
M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc
1514
M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl
15+
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
16+
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
1617
M_DEPS += ../../../library/util_cdc/sync_bits.v
1718
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
1819
M_DEPS += ../../../library/common/util_pulse_gen.v
@@ -22,14 +23,16 @@ M_DEPS += ../../../library/common/ad_bus_mux.v
2223
LIB_DEPS += axi_clkgen
2324
LIB_DEPS += axi_dmac
2425
LIB_DEPS += axi_sysid
26+
LIB_DEPS += data_offload
2527
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
2628
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
2729
LIB_DEPS += jesd204/axi_jesd204_rx
2830
LIB_DEPS += jesd204/axi_jesd204_tx
2931
LIB_DEPS += jesd204/jesd204_rx
3032
LIB_DEPS += jesd204/jesd204_tx
3133
LIB_DEPS += sysid_rom
32-
LIB_DEPS += util_dacfifo
34+
LIB_DEPS += util_do_ram
35+
LIB_DEPS += util_hbm
3336
LIB_DEPS += util_pack/util_cpack2
3437
LIB_DEPS += util_pack/util_upack2
3538
LIB_DEPS += xilinx/axi_adxcvr

‎projects/adrv9371x/zcu102/system_bd.tcl

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,15 @@
11
###############################################################################
2-
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
## FIFO depth is 16Mb - 1M samples
7-
set dac_fifo_address_width 17
8-
9-
## NOTE: With this configuration the #36Kb BRAM utilization is at ~51%
6+
## Offload attributes
7+
set dac_offload_type 0 ; ## BRAM
8+
set dac_offload_size [expr 2*1024*1024] ; ## 2 MB
9+
set plddr_offload_axi_data_width 0
1010

1111
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
12-
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
12+
source ../common/adrv9371x_bd.tcl
1313
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
1414

1515
#system ID
@@ -26,16 +26,15 @@ S=$ad_project_params(TX_JESD_S)\
2626
RX_OS:M=$ad_project_params(RX_OS_JESD_M)\
2727
L=$ad_project_params(RX_OS_JESD_L)\
2828
S=$ad_project_params(RX_OS_JESD_S)\
29-
DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
29+
DAC_OFFLOAD:TYPE=$dac_offload_type\
30+
SIZE=$dac_offload_size"
3031

3132
sysid_gen_sys_init_file $sys_cstring
3233

3334
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
3435
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
3536
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 200
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37-
source ../common/adrv9371x_bd.tcl
38-
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ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.TX_DIFFCTRL 6
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ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 80

‎projects/adrv9371x/zcu102/system_top.v

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
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// ***************************************************************************
3-
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -199,7 +199,6 @@ module system_top (
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assign spi_csn_ad9371 = spi_csn[1];
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system_wrapper i_system_wrapper (
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.dac_fifo_bypass (gpio_o[60]),
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.adc_fir_filter_active (gpio_o[61]),
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.dac_fir_filter_active (gpio_o[62]),
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.gpio_i (gpio_i),

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