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ad9208_dual_ebz: Replace adcfifo with data_offload
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
1 parent 81a579c commit 774429a

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-23
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3 files changed

+45
-23
lines changed

‎projects/ad9208_dual_ebz/common/dual_ad9208_bd.tcl

Lines changed: 35 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -13,8 +13,9 @@ set RX_SAMPLES_PER_CHANNEL 8 ; # L * 32 / (M * N)
1313

1414

1515
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
16+
source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
1617

17-
set adc_fifo_name axi_ad9208_fifo
18+
set adc_offload_name ad9208_data_offload
1819
set adc_data_width 512
1920
set adc_dma_data_width 512
2021

@@ -77,7 +78,23 @@ ad_ip_instance util_cpack2 util_ad9208_cpack [list \
7778
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
7879
]
7980

80-
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
81+
ad_data_offload_create $adc_offload_name \
82+
0 \
83+
$adc_offload_type \
84+
$adc_offload_size \
85+
$adc_data_width \
86+
$adc_dma_data_width
87+
88+
ad_ip_parameter $adc_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
89+
ad_connect $adc_offload_name/sync_ext GND
90+
91+
ad_ip_instance util_vector_logic rx_do_rstout_logic
92+
ad_ip_parameter rx_do_rstout_logic config.c_operation {not}
93+
ad_ip_parameter rx_do_rstout_logic config.c_size {1}
94+
95+
ad_ip_instance util_vector_logic cpack_reset_logic
96+
ad_ip_parameter cpack_reset_logic config.c_operation {or}
97+
ad_ip_parameter cpack_reset_logic config.c_size {1}
8198

8299
ad_ip_instance axi_dmac axi_ad9208_dma
83100
ad_ip_parameter axi_ad9208_dma CONFIG.DMA_TYPE_SRC 1
@@ -146,16 +163,19 @@ ad_connect glbl_clk_0 rx_ad9208_0_tpl_core/link_clk
146163
ad_connect glbl_clk_0 rx_ad9208_1_tpl_core/link_clk
147164

148165
ad_connect glbl_clk_0 util_ad9208_cpack/clk
149-
ad_connect glbl_clk_0 axi_ad9208_fifo/adc_clk
166+
ad_connect glbl_clk_0 $adc_offload_name/s_axis_aclk
150167

151168

152169
# dma clock domain
153-
ad_connect $sys_cpu_clk axi_ad9208_fifo/dma_clk
170+
ad_connect $sys_cpu_clk $adc_offload_name/m_axis_aclk
154171
ad_connect $sys_cpu_clk axi_ad9208_dma/s_axis_aclk
155172

156173
# connect resets
157-
ad_connect glbl_clk_0_rstgen/peripheral_reset axi_ad9208_fifo/adc_rst
158-
ad_connect glbl_clk_0_rstgen/peripheral_reset util_ad9208_cpack/reset
174+
ad_connect glbl_clk_0_rstgen/peripheral_aresetn $adc_offload_name/s_axis_aresetn
175+
ad_connect glbl_clk_0_rstgen/peripheral_reset cpack_reset_logic/op1
176+
ad_connect rx_do_rstout_logic/res cpack_reset_logic/op2
177+
ad_connect cpack_reset_logic/res util_ad9208_cpack/reset
178+
ad_connect $sys_cpu_resetn $adc_offload_name/m_axis_aresetn
159179
ad_connect $sys_cpu_resetn axi_ad9208_dma/m_dest_axi_aresetn
160180

161181

@@ -179,13 +199,14 @@ for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
179199
ad_connect rx_ad9208_0_tpl_core/adc_dovf util_ad9208_cpack/fifo_wr_overflow
180200
ad_connect rx_ad9208_1_tpl_core/adc_dovf util_ad9208_cpack/fifo_wr_overflow
181201

182-
ad_connect util_ad9208_cpack/packed_fifo_wr_data axi_ad9208_fifo/adc_wdata
183-
ad_connect util_ad9208_cpack/packed_fifo_wr_en axi_ad9208_fifo/adc_wr
202+
ad_connect util_ad9208_cpack/packed_fifo_wr_data $adc_offload_name/s_axis_tdata
203+
ad_connect util_ad9208_cpack/packed_fifo_wr_en $adc_offload_name/s_axis_tvalid
204+
ad_connect $adc_offload_name/s_axis_tlast GND
205+
ad_connect $adc_offload_name/s_axis_tkeep VCC
206+
ad_connect $adc_offload_name/s_axis_tready rx_do_rstout_logic/op1
184207

185-
ad_connect axi_ad9208_fifo/dma_wr axi_ad9208_dma/s_axis_valid
186-
ad_connect axi_ad9208_fifo/dma_wdata axi_ad9208_dma/s_axis_data
187-
ad_connect axi_ad9208_fifo/dma_wready axi_ad9208_dma/s_axis_ready
188-
ad_connect axi_ad9208_fifo/dma_xfer_req axi_ad9208_dma/s_axis_xfer_req
208+
ad_connect $adc_offload_name/m_axis axi_ad9208_dma/s_axis
209+
ad_connect $adc_offload_name/init_req axi_ad9208_dma/s_axis_xfer_req
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190211
# interconnect (cpu)
191212

@@ -196,6 +217,7 @@ ad_cpu_interconnect 0x44b10000 rx_ad9208_1_tpl_core
196217
ad_cpu_interconnect 0x44a90000 axi_ad9208_0_jesd
197218
ad_cpu_interconnect 0x44b90000 axi_ad9208_1_jesd
198219
ad_cpu_interconnect 0x7c420000 axi_ad9208_dma
220+
ad_cpu_interconnect 0x7c430000 $adc_offload_name
199221

200222
# interconnect (gt/adc)
201223

@@ -208,6 +230,3 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9208_dma/m_dest_axi
208230
ad_cpu_interrupt ps-12 mb-12 axi_ad9208_dma/irq
209231
ad_cpu_interrupt ps-11 mb-13 axi_ad9208_0_jesd/irq
210232
ad_cpu_interrupt ps-10 mb-14 axi_ad9208_1_jesd/irq
211-
212-
213-

‎projects/ad9208_dual_ebz/vcu118/Makefile

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################
@@ -9,19 +9,22 @@ PROJECT_NAME := ad9208_dual_ebz_vcu118
99
M_DEPS += ../common/dual_ad9208_bd.tcl
1010
M_DEPS += ../../scripts/adi_pd.tcl
1111
M_DEPS += ../../daq3/common/daq3_spi.v
12-
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
1312
M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc
1413
M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl
14+
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
15+
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
1516
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
1617
M_DEPS += ../../../library/common/ad_iobuf.v
1718

1819
LIB_DEPS += axi_dmac
1920
LIB_DEPS += axi_sysid
21+
LIB_DEPS += data_offload
2022
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
2123
LIB_DEPS += jesd204/axi_jesd204_rx
2224
LIB_DEPS += jesd204/jesd204_rx
2325
LIB_DEPS += sysid_rom
24-
LIB_DEPS += util_adcfifo
26+
LIB_DEPS += util_do_ram
27+
LIB_DEPS += util_hbm
2528
LIB_DEPS += util_pack/util_cpack2
2629
LIB_DEPS += xilinx/axi_adxcvr
2730
LIB_DEPS += xilinx/util_adxcvr

‎projects/ad9208_dual_ebz/vcu118/system_bd.tcl

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
11
###############################################################################
2-
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
## FIFO depth is 4Mb - 250k samples (65k samples per converter)
7-
set adc_fifo_address_width 13
6+
## Offload attributes
7+
set adc_offload_type 0 ; ## BRAM
8+
set adc_offload_size [expr 512*1024] ; ## 512 kB
89

910
source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
10-
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
1111
source ../common/dual_ad9208_bd.tcl
1212
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
1313

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