@@ -126,18 +126,19 @@ CPU/Memory interconnects addresses
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL (see more at :ref: `architecture cpu-intercon-addr `).
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- ==================== =============== ===========
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- Instance Zynq/Microblaze ZynqMP
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- ==================== =============== ===========
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- rx_adrv9026_tpl_core 0x44A0_0000 0x84A0_0000
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- tx_adrv9026_tpl_core 0x44A0_4000 0x84A0_4000
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- axi_adrv9026_rx_xcvr 0x44A6_0000 0x84A6_0000
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- axi_adrv9026_tx_xcvr 0x44A8_0000 0x84A8_0000
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- axi_adrv9026_tx_jesd 0x44A9_0000 0x84A9_0000
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- axi_adrv9026_rx_jesd 0x44AA_0000 0x84AA_0000
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- axi_adrv9026_rx_dma 0x7C40_0000 0x9C40_0000
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- axi_adrv9026_tx_dma 0x7C42_0000 0x9C42_0000
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- ==================== =============== ===========
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+ ===================== =============== ===========
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+ Instance Zynq/Microblaze ZynqMP
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+ ===================== =============== ===========
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+ rx_adrv9026_tpl_core 0x44A0_0000 0x84A0_0000
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+ tx_adrv9026_tpl_core 0x44A0_4000 0x84A0_4000
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+ axi_adrv9026_rx_xcvr 0x44A6_0000 0x84A6_0000
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+ axi_adrv9026_tx_xcvr 0x44A8_0000 0x84A8_0000
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+ axi_adrv9026_tx_jesd 0x44A9_0000 0x84A9_0000
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+ axi_adrv9026_rx_jesd 0x44AA_0000 0x84AA_0000
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+ axi_adrv9026_rx_dma 0x7C40_0000 0x9C40_0000
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+ axi_adrv9026_tx_dma 0x7C42_0000 0x9C42_0000
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+ adrv9026_data_offload 0x7C43_0000 0x9C43_0000
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+ ===================== =============== ===========
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -497,6 +498,9 @@ HDL related
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* - AXI_DMAC
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- :git-hdl: `library/axi_dmac `
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- :ref: `axi_dmac `
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+ * - DATA_OFFLOAD
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+ - :git-hdl: `library/data_offload `
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+ - :ref: `data_offload `
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* - AXI_SYSID
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- :git-hdl: `library/axi_sysid `
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- :ref: `axi_sysid `
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