library: adxcvr: Sync inputs for Agilex 7

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>

Author: bluncan

library/intel/axi_adxcvr/axi_adxcvr_hw.tcl

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2016-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2016-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -20,6 +20,7 @@ set_module_property VALIDATION_CALLBACK info_param_validate
 # files
 
 ad_ip_files axi_adxcvr [list \
+  $ad_hdl_dir/library/util_cdc/sync_bits.v \
   $ad_hdl_dir/library/common/up_axi.v \
   axi_adxcvr_up.v \
   axi_adxcvr.v \

library/intel/axi_adxcvr/axi_adxcvr_up.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -81,17 +81,20 @@ module axi_adxcvr_up #(
   reg                           up_wreq_d = 'd0;
   reg     [31:0]                up_scratch = 'd0;
   reg                           up_resetn = 'd0;
-  reg     [ 3:0]                up_rst_cnt = 'd8;
   reg                           up_status_int = 'd0;
   reg                           up_rreq_d = 'd0;
   reg     [31:0]                up_rdata_d = 'd0;
 
   // internal signals
 
-  wire                          up_ready_s;
+  wire                          up_all_ready_s;
   wire    [31:0]                up_status_32_s;
   wire    [31:0]                up_rparam_s;
 
+  wire                          up_pll_locked_s;
+  wire                          up_rx_lockedtodata_s;
+  wire                          up_ready_s;
+
   // defaults
 
   assign up_wack = up_wreq_d;
@@ -120,53 +123,81 @@ module axi_adxcvr_up #(
     end
   end
 
-  assign up_ready_s = & up_status_32_s[(NUM_OF_LANES-1):0];
+  generate if (FPGA_TECHNOLOGY == 105) begin
+    sync_bits #(
+      .NUM_OF_BITS (3),
+      .ASYNC_CLK (1)
+    ) i_sync_input_ctrl (
+      .in_bits ({up_ready, up_pll_locked, up_rx_lockedtodata}),
+      .out_resetn (1'b1),
+      .out_clk (up_clk),
+      .out_bits({up_ready_s, up_pll_locked_s, up_rx_lockedtodata_s}));
+  end else begin
+    assign up_ready_s = up_ready;
+    assign up_pll_locked_s = up_pll_locked;
+    assign up_rx_lockedtodata_s = up_rx_lockedtodata;
+  end
+  endgenerate
+
+  assign up_all_ready_s = & up_status_32_s[(NUM_OF_LANES-1):0];
   assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0;
-  assign up_status_32_s[NUM_OF_LANES] = FPGA_TECHNOLOGY == 105 ? TX_OR_RX_N ? up_pll_locked : up_rx_lockedtodata :
-                                                                 up_pll_locked;
-  assign up_status_32_s[(NUM_OF_LANES-1):0] = FPGA_TECHNOLOGY == 105 ? {NUM_OF_LANES{up_ready}} : up_ready;
+  assign up_status_32_s[NUM_OF_LANES] = FPGA_TECHNOLOGY == 105 ? TX_OR_RX_N ? up_pll_locked_s : up_rx_lockedtodata_s :
+                                                                 up_pll_locked_s;
+  assign up_status_32_s[(NUM_OF_LANES-1):0] = FPGA_TECHNOLOGY == 105 ? {NUM_OF_LANES{up_ready_s}} : up_ready_s;
 
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_rst_cnt <= 4'h8;
-      up_status_int <= 1'b0;
-    end else begin
-      if (up_resetn == 1'b0) begin
-        up_rst_cnt <= 4'h8;
-      end else if (up_rst_cnt[3] == 1'b1) begin
-        up_rst_cnt <= up_rst_cnt + 1'b1;
-      end
-      if (up_resetn == 1'b0) begin
-        up_status_int <= 1'b0;
-      end else if (up_ready_s == 1'b1) begin
-        up_status_int <= 1'b1;
+  generate if (FPGA_TECHNOLOGY == 105) begin
+    wire up_reset_ack_s;
+    reg  up_rst_d;
+
+    sync_bits #(
+      .NUM_OF_BITS (1),
+      .ASYNC_CLK (1)
+    ) i_sync_reset_ack (
+      .in_bits (up_reset_ack),
+      .out_resetn (1'b1),
+      .out_clk (up_clk),
+      .out_bits(up_reset_ack_s));
+
+    always @(negedge up_rstn or posedge up_clk) begin
+      if (up_rstn == 0) begin
+        up_rst_d <= 1'b1;
+      end else if (up_resetn == 1'b0) begin
+        up_rst_d <= 1'b1;
+      end else if (up_reset_ack_s) begin
+        up_rst_d <= 1'b0;
       end
     end
-  end
-
-  generate if (FPGA_TECHNOLOGY == 105) begin
-    reg up_reset_ack_d = 'd0;
+    assign up_rst = up_rst_d;
+  end else begin
+    reg [3:0] up_rst_cnt = 'd8;
 
     always @(negedge up_rstn or posedge up_clk) begin
       if (up_rstn == 0) begin
-        up_reset_ack_d <= 1'b0;
+        up_rst_cnt <= 4'h8;
       end else begin
         if (up_resetn == 1'b0) begin
-          up_reset_ack_d <= 1'b0;
-        end else begin
-          if (up_reset_ack_d == 1'b0) begin
-            up_reset_ack_d <= up_reset_ack;
-          end
+          up_rst_cnt <= 4'h8;
+        end else if (up_rst_cnt[3] == 1'b1) begin
+          up_rst_cnt <= up_rst_cnt + 1'b1;
         end
       end
     end
-
-    assign up_rst = ~up_reset_ack_d;
-  end else begin
     assign up_rst = up_rst_cnt[3];
   end
   endgenerate
 
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_status_int <= 1'b0;
+    end else begin
+      if (up_resetn == 1'b0) begin
+        up_status_int <= 1'b0;
+      end else if (up_all_ready_s) begin
+        up_status_int <= 1'b1;
+      end
+    end
+  end
+
   // Specific to Intel
 
   assign up_rparam_s[31:28] = 8'd0;