axi_dmac: Delay input packet until IRQ is acknowledged

[IstvanZsSzekely]

PR Description

Using the DMA in Scatter-Gather mode multiple interrupts can overlap if the input data rate if faster than what the processing system (PS) can acknowledge. In this case, if the PS is waiting for an interrupt request after each data packet, then some of the interrupts are lost because of this overlap.
This feature introduces a blocking mechanism, that prevents new data to be sent to the DMA until the interrupt has been acknowledged for the previous packet.

Testbench branch
When SG_DELAYED_INPUT is set to 1 in the system_bd.tcl under dma_sg_2, the DMA can parse all of the input data packet by packet. Changing this value to 0 will hang the simulation.

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[podgori]

Please move the added logic in a submodule - axi_dmac_transfer.v for instance - so that the top module is left for module instantiations only.

[podgori]

I'd like to suggest some improvements for this implementation:

1. Currently, a synthesis parameter is used to select the delay logic, thus blocking the DMA to only work in one of the two possible cases: acknowledge the interrupts or not - this can be improved by using a register bit to select the functionality, perhaps in the FLAGS register.
2. The added logic polls the irq output, which means that the interrupts cannot be treated separately. In fact the irq doesn't need to be read, the information about the interrupt clear is found in the up_irq_source_clear signal in the regmap module for both start and end of transfer interrupts, so this signal can be used instead.