From 27599bd2c2681ff57c3b81e35897928546519b4b Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Thu, 23 Jan 2025 14:55:41 +0200 Subject: [PATCH 1/4] library: intel: avl_dacfifo: Make avl interface parametrizable Signed-off-by: Bogdan Luncan --- library/intel/avl_dacfifo/avl_dacfifo.v | 27 ++++++++++++++------ library/intel/avl_dacfifo/avl_dacfifo_hw.tcl | 22 ++++++++-------- library/intel/avl_dacfifo/avl_dacfifo_rd.v | 7 ++--- library/intel/avl_dacfifo/avl_dacfifo_wr.v | 7 ++--- 4 files changed, 38 insertions(+), 25 deletions(-) diff --git a/library/intel/avl_dacfifo/avl_dacfifo.v b/library/intel/avl_dacfifo/avl_dacfifo.v index c7c412c9454..223241b827e 100644 --- a/library/intel/avl_dacfifo/avl_dacfifo.v +++ b/library/intel/avl_dacfifo/avl_dacfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -36,7 +36,7 @@ `timescale 1ns/100ps module avl_dacfifo #( - + parameter ACTIVE_LOW_RESET = 0, parameter DAC_DATA_WIDTH = 64, parameter DAC_MEM_ADDRESS_WIDTH = 8, parameter DMA_DATA_WIDTH = 64, @@ -102,9 +102,9 @@ module avl_dacfifo #( wire dma_ready_bypass_s; wire avl_read_s; wire avl_write_s; - wire [ 24:0] avl_wr_address_s; - wire [ 24:0] avl_rd_address_s; - wire [ 24:0] avl_last_address_s; + wire [(AVL_ADDRESS_WIDTH-1):0] avl_wr_address_s; + wire [(AVL_ADDRESS_WIDTH-1):0] avl_rd_address_s; + wire [(AVL_ADDRESS_WIDTH-1):0] avl_last_address_s; wire [ 6:0] avl_last_burstcount_s; wire [ 7:0] dma_last_beats_s; wire [ 6:0] avl_wr_burstcount_s; @@ -120,9 +120,19 @@ module avl_dacfifo #( wire dac_dunf_fifo_s; wire dac_dunf_bypass_s; + wire avl_reset_s; + + generate if (ACTIVE_LOW_RESET == 1) begin + assign avl_reset_s = ~avl_reset; + end else begin + assign avl_reset_s = avl_reset; + end + endgenerate + avl_dacfifo_wr #( .AVL_DATA_WIDTH (AVL_DATA_WIDTH), .DMA_DATA_WIDTH (DMA_DATA_WIDTH), + .AVL_ADDRESS_WIDTH (AVL_ADDRESS_WIDTH), .AVL_DDR_BASE_ADDRESS (AVL_BASE_ADDRESS), .DMA_MEM_ADDRESS_WIDTH(DMA_MEM_ADDRESS_WIDTH), .AVL_BURST_LENGTH (AVL_BURST_LENGTH) @@ -138,7 +148,7 @@ module avl_dacfifo #( .avl_last_address (avl_last_address_s), .avl_last_burstcount (avl_last_burstcount_s), .avl_clk (avl_clk), - .avl_reset (avl_reset), + .avl_reset (avl_reset_s), .avl_address (avl_wr_address_s), .avl_burstcount (avl_wr_burstcount_s), .avl_byteenable (avl_wr_byteenable_s), @@ -151,6 +161,7 @@ module avl_dacfifo #( avl_dacfifo_rd #( .AVL_DATA_WIDTH(AVL_DATA_WIDTH), .DAC_DATA_WIDTH(DAC_DATA_WIDTH), + .AVL_ADDRESS_WIDTH (AVL_ADDRESS_WIDTH), .AVL_DDR_BASE_ADDRESS(AVL_BASE_ADDRESS), .AVL_DDR_ADDRESS_LIMIT(AVL_ADDRESS_LIMIT), .DAC_MEM_ADDRESS_WIDTH(DAC_MEM_ADDRESS_WIDTH), @@ -163,7 +174,7 @@ module avl_dacfifo #( .dac_xfer_req(dac_xfer_fifo_out_s), .dac_dunf(dac_dunf_fifo_s), .avl_clk(avl_clk), - .avl_reset(avl_reset), + .avl_reset(avl_reset_s), .avl_address(avl_rd_address_s), .avl_burstcount(avl_rd_burstcount_s), .avl_byteenable(avl_rd_byteenable_s), @@ -182,7 +193,7 @@ module avl_dacfifo #( assign avl_xfer_wren_s = ~avl_xfer_in_s; always @(posedge avl_clk) begin - if (avl_reset == 1'b1) begin + if (avl_reset_s == 1'b1) begin avl_address <= 0; avl_burstcount <= 0; avl_byteenable <= 0; diff --git a/library/intel/avl_dacfifo/avl_dacfifo_hw.tcl b/library/intel/avl_dacfifo/avl_dacfifo_hw.tcl index 3e80d6318b7..69048697c43 100644 --- a/library/intel/avl_dacfifo/avl_dacfifo_hw.tcl +++ b/library/intel/avl_dacfifo/avl_dacfifo_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2023, 2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -22,6 +22,7 @@ ad_ip_files avl_dacfifo [list\ # parameters ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter ACTIVE_LOW_RESET INTEGER 0 ad_ip_parameter DAC_DATA_WIDTH INTEGER 64 ad_ip_parameter DAC_MEM_ADDRESS_WIDTH INTEGER 8 ad_ip_parameter DMA_DATA_WIDTH INTEGER 64 @@ -30,7 +31,7 @@ ad_ip_parameter AVL_DATA_WIDTH INTEGER 512 ad_ip_parameter AVL_ADDRESS_WIDTH INTEGER 25 ad_ip_parameter AVL_BURST_LENGTH INTEGER 127 ad_ip_parameter AVL_BASE_ADDRESS INTEGER 0 -ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x800000 +ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x80000000 # interfaces @@ -63,15 +64,15 @@ set_interface_property avl_reset associatedclock avl_clock add_interface_port avl_reset avl_reset reset input 1 add_interface amm_ddr avalon master -add_interface_port amm_ddr avl_address address output 25 -add_interface_port amm_ddr avl_burstcount burstcount output 7 -add_interface_port amm_ddr avl_byteenable byteenable output 64 -add_interface_port amm_ddr avl_read read output 1 -add_interface_port amm_ddr avl_readdata readdata input 512 +add_interface_port amm_ddr avl_address address output AVL_ADDRESS_WIDTH +add_interface_port amm_ddr avl_burstcount burstcount output 7 +add_interface_port amm_ddr avl_byteenable byteenable output AVL_DATA_WIDTH/8 +add_interface_port amm_ddr avl_read read output 1 +add_interface_port amm_ddr avl_readdata readdata input AVL_DATA_WIDTH add_interface_port amm_ddr avl_readdata_valid readdatavalid input 1 -add_interface_port amm_ddr avl_ready waitrequest_n input 1 -add_interface_port amm_ddr avl_write write output 1 -add_interface_port amm_ddr avl_writedata writedata output 512 +add_interface_port amm_ddr avl_ready waitrequest_n input 1 +add_interface_port amm_ddr avl_write write output 1 +add_interface_port amm_ddr avl_writedata writedata output AVL_DATA_WIDTH set_interface_property amm_ddr associatedClock avl_clock set_interface_property amm_ddr associatedReset avl_reset @@ -140,4 +141,3 @@ proc p_avl_dacfifo_elab {} { set_instance_parameter_value ad_mem_asym_bypass B_DATA_WIDTH $m_dac_data_width } - diff --git a/library/intel/avl_dacfifo/avl_dacfifo_rd.v b/library/intel/avl_dacfifo/avl_dacfifo_rd.v index ced1ca3cc54..ce534fc7442 100644 --- a/library/intel/avl_dacfifo/avl_dacfifo_rd.v +++ b/library/intel/avl_dacfifo/avl_dacfifo_rd.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -39,6 +39,7 @@ module avl_dacfifo_rd #( parameter AVL_DATA_WIDTH = 512, parameter DAC_DATA_WIDTH = 64, + parameter AVL_ADDRESS_WIDTH = 25, parameter AVL_BURST_LENGTH = 127, parameter AVL_DDR_BASE_ADDRESS = 0, parameter AVL_DDR_ADDRESS_LIMIT = 33554432, @@ -53,7 +54,7 @@ module avl_dacfifo_rd #( input avl_clk, input avl_reset, - output reg [24:0] avl_address, + output reg [(AVL_ADDRESS_WIDTH-1):0] avl_address, output reg [ 6:0] avl_burstcount, output [63:0] avl_byteenable, input avl_waitrequest, @@ -61,7 +62,7 @@ module avl_dacfifo_rd #( output reg avl_read, input [AVL_DATA_WIDTH-1:0] avl_data, - input [24:0] avl_last_address, + input [(AVL_ADDRESS_WIDTH-1):0] avl_last_address, input [ 6:0] avl_last_burstcount, input [ 7:0] dma_last_beats, input avl_xfer_req_in, diff --git a/library/intel/avl_dacfifo/avl_dacfifo_wr.v b/library/intel/avl_dacfifo/avl_dacfifo_wr.v index 74ee1a24ba6..7752015459a 100644 --- a/library/intel/avl_dacfifo/avl_dacfifo_wr.v +++ b/library/intel/avl_dacfifo/avl_dacfifo_wr.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -39,6 +39,7 @@ module avl_dacfifo_wr #( parameter AVL_DATA_WIDTH = 512, parameter DMA_DATA_WIDTH = 64, + parameter AVL_ADDRESS_WIDTH = 25, parameter AVL_BURST_LENGTH = 128, parameter AVL_DDR_BASE_ADDRESS = 0, parameter AVL_DDR_ADDRESS_LIMIT = 33554432, @@ -56,14 +57,14 @@ module avl_dacfifo_wr #( input avl_clk, input avl_reset, - output reg [24:0] avl_address, + output reg [(AVL_ADDRESS_WIDTH-1):0] avl_address, output reg [ 6:0] avl_burstcount, output [63:0] avl_byteenable, input avl_waitrequest, output reg avl_write, output reg [AVL_DATA_WIDTH-1:0] avl_data, - output reg [24:0] avl_last_address, + output reg [(AVL_ADDRESS_WIDTH-1):0] avl_last_address, output reg [ 6:0] avl_last_burstcount, output reg avl_xfer_req_out, input avl_xfer_req_in From 94bd806d09631f5ab5631fa55f383d591320113d Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Thu, 23 Jan 2025 14:50:44 +0200 Subject: [PATCH 2/4] projects: common: fm87: Add external ddr instantiation with avl_dacfifo Signed-off-by: Bogdan Luncan --- .../common/fm87/fm87_plddr_dacfifo_qsys.tcl | 2270 +++++++++++++++++ .../common/fm87/fm87_plddr_system_assign.tcl | 145 ++ projects/common/fm87/system_ddr_constr.sdc | 6 + 3 files changed, 2421 insertions(+) create mode 100644 projects/common/fm87/fm87_plddr_dacfifo_qsys.tcl create mode 100644 projects/common/fm87/fm87_plddr_system_assign.tcl create mode 100644 projects/common/fm87/system_ddr_constr.sdc diff --git a/projects/common/fm87/fm87_plddr_dacfifo_qsys.tcl b/projects/common/fm87/fm87_plddr_dacfifo_qsys.tcl new file mode 100644 index 00000000000..1341d11b0b9 --- /dev/null +++ b/projects/common/fm87/fm87_plddr_dacfifo_qsys.tcl @@ -0,0 +1,2270 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc ad_dacfifo_create {dac_fifo_name dac_data_width dac_dma_data_width dac_fifo_address_width instantiate_ddr4} { + + if {$instantiate_ddr4} { + add_instance sys_ddr4_cntrl altera_emif_fm + set_instance_parameter_value sys_ddr4_cntrl AUTO_BOARD {default} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_AC_TO_CK_SKEW_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_DQS_TO_CK_SKEW_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_MAX_CK_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_MAX_DQS_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_RCLK_SLEW_RATE {5.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_RDATA_SLEW_RATE {2.5} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS {0.05} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_SKEW_BETWEEN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_SKEW_WITHIN_AC_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_SKEW_WITHIN_DQS_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_TDH_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_TDS_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_TIH_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_TIS_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_RCLK_SLEW_RATE {5.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_RDATA_SLEW_RATE {2.5} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USER_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USE_DEFAULT_ISI_VALUES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_USE_DEFAULT_SLEW_RATES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR3_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_AC_ISI_NS {0.15} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_AC_TO_CK_SKEW_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_DQS_TO_CK_SKEW_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_MAX_CK_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_MAX_DQS_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_RCLK_ISI_NS {0.15} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_RCLK_SLEW_RATE {8.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_RDATA_ISI_NS {0.12} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_RDATA_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS {0.05} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_SKEW_BETWEEN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_SKEW_WITHIN_AC_NS {0.18} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_SKEW_WITHIN_DQS_NS {0.12} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_TIH_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_TIS_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_RCLK_SLEW_RATE {8.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_RDATA_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USER_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USE_DEFAULT_ISI_VALUES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_USE_DEFAULT_SLEW_RATES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_WCLK_ISI_NS {0.06} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_WDATA_ISI_NS {0.13} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDR4_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_AC_TO_CK_SKEW_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_DQS_TO_CK_SKEW_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_MAX_CK_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_MAX_DQS_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_RCLK_SLEW_RATE {8.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_RDATA_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS {0.05} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_SKEW_BETWEEN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_SKEW_WITHIN_AC_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_SKEW_WITHIN_DQS_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_TIH_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_TIS_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_RCLK_SLEW_RATE {8.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_RDATA_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USER_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USE_DEFAULT_ISI_VALUES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_USE_DEFAULT_SLEW_RATES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_DDRT_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_AC_TO_CK_SKEW_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_DQS_TO_CK_SKEW_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_MAX_CK_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_MAX_DQS_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_RCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_RDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS {0.05} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_SKEW_WITHIN_AC_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_SKEW_WITHIN_DQS_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_TDH_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_TDS_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_TIH_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_TIS_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_RCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_RDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USER_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_LPDDR3_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_AC_TO_K_SKEW_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_BRD_SKEW_WITHIN_D_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_K_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_MAX_K_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_RCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_RDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_SKEW_WITHIN_AC_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_SKEW_WITHIN_D_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_SKEW_WITHIN_Q_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USER_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USER_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USER_K_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USER_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USER_RCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USER_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USER_RDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USER_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USER_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USER_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USE_DEFAULT_ISI_VALUES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_USE_DEFAULT_SLEW_RATES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR2_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_AC_TO_CK_SKEW_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_DK_TO_CK_SKEW_NS {-0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_MAX_CK_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_MAX_DK_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_RCLK_SLEW_RATE {5.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_RDATA_SLEW_RATE {2.5} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS {0.05} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_SKEW_BETWEEN_DK_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_SKEW_WITHIN_AC_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_SKEW_WITHIN_QK_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_RCLK_SLEW_RATE {5.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_RDATA_SLEW_RATE {2.5} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USER_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USE_DEFAULT_ISI_VALUES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_USE_DEFAULT_SLEW_RATES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_QDR4_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_AC_TO_CK_SKEW_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_DK_TO_CK_SKEW_NS {-0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_MAX_CK_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_MAX_DK_DELAY_NS {0.6} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_RCLK_SLEW_RATE {7.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_RDATA_SLEW_RATE {3.5} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS {0.05} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_SKEW_BETWEEN_DK_NS {0.02} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_SKEW_WITHIN_AC_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_SKEW_WITHIN_QK_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_TDH_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_TDS_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_TIH_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_TIS_DERATING_PS {0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_AC_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_AC_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_CK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_RCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_RCLK_SLEW_RATE {7.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_RDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_RDATA_SLEW_RATE {3.5} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USER_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USE_DEFAULT_ISI_VALUES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_USE_DEFAULT_SLEW_RATES {1} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_WCLK_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_WCLK_SLEW_RATE {4.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_WDATA_ISI_NS {0.0} + set_instance_parameter_value sys_ddr4_cntrl BOARD_RLD3_WDATA_SLEW_RATE {2.0} + set_instance_parameter_value sys_ddr4_cntrl CAL_DEBUG_CLOCK_FREQUENCY {50000000.0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_AUTO_PRECHARGE_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_AUTO_POWER_DOWN_CYCS {32} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_AUTO_POWER_DOWN_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_AUTO_PRECHARGE_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_ECC_AUTO_CORRECTION_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_ECC_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_ECC_STATUS_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_REORDER_EN {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_SELF_REFRESH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_STARVE_LIMIT {10} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_USER_PRIORITY_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_USER_REFRESH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_AUTO_POWER_DOWN_CYCS {32} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_AUTO_POWER_DOWN_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_AUTO_PRECHARGE_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_ECC_AUTO_CORRECTION_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_ECC_EN {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_ECC_STATUS_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_MAJOR_MODE_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_POST_REFRESH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_POST_REFRESH_LOWER_LIMIT {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_POST_REFRESH_UPPER_LIMIT {2} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_PRE_REFRESH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_REORDER_EN {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_SELF_REFRESH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_STARVE_LIMIT {10} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_USER_PRIORITY_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_USER_REFRESH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_ADDR_INTERLEAVING {COARSE} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_AUTO_POWER_DOWN_CYCS {32} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_AUTO_POWER_DOWN_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_AUTO_PRECHARGE_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_AXIS_DATA_WIDTH {512} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_DIMM_DENSITY {128} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_DIMM_VIRAL_FLOW_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_DRIVER_MARGINING_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_ECC_AUTO_CORRECTION_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_ECC_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_ECC_STATUS_EN {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_ERR_INJECT_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_ERR_REPLAY_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_EXT_ERR_INJECT_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_HOST_VIRAL_FLOW_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_NUM_OF_AXIS_ID {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_PARITY_CMD_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_PMM_ADR_FLOW_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_PMM_WPQ_FLUSH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_POISON_DETECTION_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_PORT_AFI_C_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_REORDER_EN {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_SELF_REFRESH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_STARVE_LIMIT {10} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_UPI_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_UPI_ID_WIDTH {8} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_USER_PRIORITY_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_USER_REFRESH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_WR_ACK_POLICY {POSTED} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_DDRT_ZQ_INTERVAL_MS {3} + set_instance_parameter_value sys_ddr4_cntrl CTRL_ECC_EN {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_ECC_READDATAERROR_EN {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_ECC_STATUS_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS {32} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_AUTO_POWER_DOWN_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_AUTO_PRECHARGE_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_REORDER_EN {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_SELF_REFRESH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_STARVE_LIMIT {10} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_USER_PRIORITY_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_USER_REFRESH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_MMR_EN {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR2_AVL_MAX_BURST_COUNT {4} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR2_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR2_AVL_SYMBOL_WIDTH {9} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS {0} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR4_AVL_MAX_BURST_COUNT {4} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR4_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR4_AVL_SYMBOL_WIDTH {9} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC {11} + set_instance_parameter_value sys_ddr4_cntrl CTRL_REORDER_EN {1} + set_instance_parameter_value sys_ddr4_cntrl CTRL_RLD2_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value sys_ddr4_cntrl CTRL_RLD3_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value sys_ddr4_cntrl CTRL_USER_PRIORITY_EN {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_AC_PARITY_ERR {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_ADD_READY_PIPELINE {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_BOARD_DELAY_CONFIG_STR {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DB_RESET_AUTO_RELEASE {avl_release} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_ABSTRACT_PHY {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_AC_PARITY_ERR {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_CAL_ADDR0 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_CAL_ADDR1 {8} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_CAL_ENABLE_MICRON_AP {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_CAL_ENABLE_NON_DES {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_CAL_FULL_CAL_ON_RESET {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_CA_DESKEW_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_CA_LEVEL_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_ENABLE_DEFAULT_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_EX_DESIGN_ISSP_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_INTERFACE_ID {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_SEPARATE_READ_WRITE_ITFS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_USER_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_USE_NEW_EFFMON_S10 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_USE_SIM_MEMORY_VALIDATION_TG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR3_USE_TG_HBM {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_ABSTRACT_PHY {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_AC_PARITY_ERR {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_CAL_ADDR0 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_CAL_ADDR1 {8} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_CAL_ENABLE_NON_DES {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_CAL_FULL_CAL_ON_RESET {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_ENABLE_DEFAULT_MODE {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_EX_DESIGN_ISSP_EN {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_INTERFACE_ID {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_SEPARATE_READ_WRITE_ITFS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_SKIP_AC_PARITY_CHECK {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_SKIP_CA_DESKEW {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_SKIP_CA_LEVEL {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_SKIP_VREF_CAL {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_USER_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_USE_NEW_EFFMON_S10 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_USE_SIM_MEMORY_VALIDATION_TG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDR4_USE_TG_HBM {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_ABSTRACT_PHY {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_AC_PARITY_ERR {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_CAL_ADDR0 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_CAL_ADDR1 {8} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_CAL_ENABLE_NON_DES {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_CAL_FULL_CAL_ON_RESET {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_EFF_TEST {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_ENABLE_DEFAULT_MODE {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_ENABLE_DRIVER_MARGINING {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_ENABLE_ENHANCED_TESTING {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_EX_DESIGN_ISSP_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_INTERFACE_ID {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_SEPARATE_READ_WRITE_ITFS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_SKIP_CA_DESKEW {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_SKIP_CA_LEVEL {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_SKIP_VREF_CAL {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_USER_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_USE_NEW_EFFMON_S10 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_USE_SIM_MEMORY_VALIDATION_TG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DDRT_USE_TG_HBM {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_DISABLE_AFI_P2C_REGISTERS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_ECLIPSE_DEBUG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl DIAG_ENABLE_DEFAULT_MODE {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_ENABLE_HPS_EMIF_DEBUG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_ENABLE_JTAG_UART {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_ENABLE_JTAG_UART_HEX {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_ENABLE_SOFT_M20K {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_ENABLE_USER_MODE {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXPORT_SEQ_AVALON_MASTER {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXPORT_VJI {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXPOSE_DFT_SIGNALS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXPOSE_EARLY_READY {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXPOSE_RD_TYPE {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXTRA_CONFIGS {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXT_DOCS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EX_DESIGN_ADD_TEST_EMIFS {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EX_DESIGN_ISSP_EN {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EX_DESIGN_NUM_OF_SLAVES {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EX_DESIGN_SEPARATE_RESETS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EX_DESIGN_SEPARATE_RZQS {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_FAST_SIM {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_FAST_SIM_OVERRIDE {FAST_SIM_OVERRIDE_DEFAULT} + set_instance_parameter_value sys_ddr4_cntrl DIAG_HMC_HRC {auto} + set_instance_parameter_value sys_ddr4_cntrl DIAG_INTERFACE_ID {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_ABSTRACT_PHY {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_AC_PARITY_ERR {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_ENABLE_DEFAULT_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_EX_DESIGN_ISSP_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_INTERFACE_ID {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_SKIP_CA_DESKEW {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_SKIP_CA_LEVEL {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_USE_NEW_EFFMON_S10 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_USE_SIM_MEMORY_VALIDATION_TG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_LPDDR3_USE_TG_HBM {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_ABSTRACT_PHY {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_AC_PARITY_ERR {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_ENABLE_DEFAULT_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_EX_DESIGN_ISSP_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_INTERFACE_ID {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_SEPARATE_READ_WRITE_ITFS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_USER_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_USE_NEW_EFFMON_S10 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_USE_SIM_MEMORY_VALIDATION_TG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR2_USE_TG_HBM {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_ABSTRACT_PHY {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_AC_PARITY_ERR {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_ENABLE_DEFAULT_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_EX_DESIGN_ISSP_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_INTERFACE_ID {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_SEPARATE_READ_WRITE_ITFS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_SKIP_VREF_CAL {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_USER_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_USE_NEW_EFFMON_S10 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_USE_SIM_MEMORY_VALIDATION_TG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_QDR4_USE_TG_HBM {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_ABSTRACT_PHY {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_AC_PARITY_ERR {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_ENABLE_DEFAULT_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_EX_DESIGN_ISSP_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_INTERFACE_ID {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_SEPARATE_READ_WRITE_ITFS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_USER_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_USE_NEW_EFFMON_S10 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_USE_SIM_MEMORY_VALIDATION_TG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD2_USE_TG_HBM {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_ABSTRACT_PHY {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_AC_PARITY_ERR {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_CA_DESKEW_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_CA_LEVEL_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_ENABLE_DEFAULT_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_EX_DESIGN_ISSP_EN {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_INTERFACE_ID {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_SEPARATE_READ_WRITE_ITFS {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_USER_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_USE_NEW_EFFMON_S10 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_USE_SIM_MEMORY_VALIDATION_TG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RLD3_USE_TG_HBM {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_RS232_UART_BAUDRATE {57600} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SEQ_RESET_AUTO_RELEASE {avl} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_CHECKER_SKIP_TG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_MEMORY_PRELOAD {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_MEMORY_PRELOAD_PRI_ABPHY_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_MEMORY_PRELOAD_PRI_ECC_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_MEMORY_PRELOAD_PRI_MEM_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_MEMORY_PRELOAD_SEC_ABPHY_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_MEMORY_PRELOAD_SEC_ECC_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_MEMORY_PRELOAD_SEC_MEM_FILE {} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_REGTEST_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SIM_VERBOSE_LEVEL {5} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SOFT_NIOS_CLOCK_FREQUENCY {100} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SOFT_NIOS_MODE {SOFT_NIOS_MODE_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl DIAG_SYNTH_FOR_SIM {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_TG2_TEST_DURATION {SHORT} + set_instance_parameter_value sys_ddr4_cntrl DIAG_TG_AVL_2_NUM_CFG_INTERFACES {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_TIMING_REGTEST_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_USE_ABSTRACT_PHY {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_USE_BOARD_DELAY_MODEL {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_USE_NEW_EFFMON_S10 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_USE_RS232_UART {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_USE_SIM_MEMORY_VALIDATION_TG {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_USE_TG_AVL_2 {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_USE_TG_HBM {0} + set_instance_parameter_value sys_ddr4_cntrl DIAG_VERBOSE_IOAUX {0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_0_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_0_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_0_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_10_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_10_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_10_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_11_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_11_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_11_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_12_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_12_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_12_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_13_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_13_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_13_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_14_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_14_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_14_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_15_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_15_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_15_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_1_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_1_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_1_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_2_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_2_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_2_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_3_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_3_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_3_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_4_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_4_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_4_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_5_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_5_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_5_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_6_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_6_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_6_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_7_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_7_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_7_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_8_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_8_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_8_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EMIF_9_CONN_TO_CALIP {CALIP_0} + set_instance_parameter_value sys_ddr4_cntrl EMIF_9_REF_CLK_SHARING {EXPORTED} + set_instance_parameter_value sys_ddr4_cntrl EMIF_9_STORED_PARAM {} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_DDR3_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_DDR3_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_DDR4_PREV_PRESET {TARGET_DEV_KIT_SI_AGI_027_ES2_DDR4_J5} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_DDR4_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_DDRT_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_DDRT_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_GEN_BSI {0} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_GEN_CDC {0} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_GEN_SIM {1} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_GEN_SYNTH {1} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_LPDDR3_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_LPDDR3_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_QDR2_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_QDR2_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_QDR4_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_QDR4_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_RLD2_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_RLD2_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_RLD3_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_RLD3_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value sys_ddr4_cntrl EX_DESIGN_GUI_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_instance_parameter_value sys_ddr4_cntrl FAMILY_ENUM {FAMILY_AGILEX} + set_instance_parameter_value sys_ddr4_cntrl INTERNAL_TESTING_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl IS_ED_SLAVE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_BURST_LENGTH {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DATA_MASK_EN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_AC_PAR_EN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_ADDRESS_MIRROR_BITVEC {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_ADDR_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_ALERT_N_DQS_GROUP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_ALERT_N_PLACEMENT_ENUM {DDR3_ALERT_N_PLACEMENT_AC_LANES} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_ASR_ENUM {DDR3_ASR_MANUAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_ATCL_ENUM {DDR3_ATCL_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_BANK_ADDR_WIDTH {3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_BL_ENUM {DDR3_BL_BL8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_BT_ENUM {DDR3_BT_SEQUENTIAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CFG_GEN_DBE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CFG_GEN_SBE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CKE_PER_DIMM {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CKE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CK_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_COL_ADDR_WIDTH {10} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CS_PER_DIMM {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CTRL_CFG_READ_ODT_CHIP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CTRL_CFG_READ_ODT_RANK {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CTRL_CFG_WRITE_ODT_CHIP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_CTRL_CFG_WRITE_ODT_RANK {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_DISCRETE_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_DLL_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_DM_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_DM_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_DQS_WIDTH {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_DQ_PER_DQS {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_DQ_WIDTH {72} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_DRV_STR_ENUM {DDR3_DRV_STR_RZQ_7} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_FORMAT_ENUM {MEM_FORMAT_UDIMM} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_HIDE_ADV_MR_SETTINGS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_LRDIMM_EXTENDED_CONFIG {000000000000000000} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_MIRROR_ADDRESSING_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_MR0 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_MR1 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_MR2 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_MR3 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_NUM_OF_DIMMS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_NUM_OF_LOGICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_NUM_OF_PHYSICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_ODT_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_PD_ENUM {DDR3_PD_OFF} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_RANKS_PER_DIMM {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_RDIMM_CONFIG {0000000000000000} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_RM_WIDTH {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_ROW_ADDR_WIDTH {15} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_RTT_NOM_ENUM {DDR3_RTT_NOM_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_RTT_WR_ENUM {DDR3_RTT_WR_RZQ_4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_DERIVED_ODT0 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_DERIVED_ODT1 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_DERIVED_ODT2 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_DERIVED_ODT3 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_DERIVED_ODTN {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODT0_1X1 {off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODT0_2X2 {off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODT0_4X2 {off off on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODT0_4X4 {off off on off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODT1_2X2 {off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODT1_4X2 {on on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODT1_4X4 {off off off on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODT2_4X4 {on off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODT3_4X4 {off on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODTN_1X1 {Rank 0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_SEQ_ODT_TABLE_HI {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_SEQ_ODT_TABLE_LO {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_SPEEDBIN_ENUM {DDR3_SPEEDBIN_2133} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_SRT_ENUM {DDR3_SRT_NORMAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TCL {14} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDH_DC_MV {100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDH_PS {55} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDQSCKDL {1200} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDQSCKDM {900} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDQSCKDS {450} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDQSCK_DERV_PS {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDQSCK_PS {180} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDQSQ_PS {75} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDQSS_CYC {0.27} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDSH_CYC {0.18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDSS_CYC {0.18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDS_AC_MV {135} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TDS_PS {53} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TFAW_CYC {27} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TFAW_NS {25.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TIH_DC_MV {100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TIH_PS {95} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TINIT_CK {499} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TINIT_US {500} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TIS_AC_MV {135} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TIS_PS {60} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TMRD_CK_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TQH_CYC {0.38} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TQSH_CYC {0.4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TRAS_CYC {36} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TRAS_NS {33.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TRCD_CYC {14} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TRCD_NS {13.09} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TREFI_CYC {8320} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TREFI_US {7.8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TRFC_CYC {171} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TRFC_NS {160.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TRP_CYC {14} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TRP_NS {13.09} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TRRD_CYC {6} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TRTP_CYC {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_ADDR_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_BANK_ADDR_WIDTH {3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_CKE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_CK_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_DM_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_DQS_WIDTH {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_DQ_WIDTH {72} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_NUM_OF_DIMMS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_NUM_OF_LOGICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_NUM_OF_PHYSICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_ODT_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TTL_RM_WIDTH {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TWLH_PS {125.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TWLS_PS {125.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TWR_CYC {16} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TWR_NS {15.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_TWTR_CYC {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_USE_DEFAULT_ODT {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_WTCL {10} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_DERIVED_ODT0 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_DERIVED_ODT1 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_DERIVED_ODT2 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_DERIVED_ODT3 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_DERIVED_ODTN {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODT0_1X1 {on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODT0_2X2 {on off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODT0_4X2 {off off on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODT0_4X4 {on off on off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODT1_2X2 {off on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODT1_4X2 {on on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODT1_4X4 {off on off on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODT2_4X4 {on off on off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODT3_4X4 {off on off on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODTN_1X1 {Rank 0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR3_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_AC_PARITY_LATENCY {DDR4_AC_PARITY_LATENCY_DISABLE} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_AC_PERSISTENT_ERROR {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ADDRESS_MIRROR_BITVEC {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ADDR_WIDTH {17} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ALERT_N_AC_LANE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ALERT_N_AC_PIN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ALERT_N_DQS_GROUP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ALERT_N_PLACEMENT_ENUM {DDR4_ALERT_N_PLACEMENT_FM_LANE3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ALERT_PAR_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ASR_ENUM {DDR4_ASR_MANUAL_NORMAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ATCL_ENUM {DDR4_ATCL_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_BANK_ADDR_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_BANK_GROUP_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_BL_ENUM {DDR4_BL_BL8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_BT_ENUM {DDR4_BT_SEQUENTIAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CAL_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CFG_GEN_DBE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CFG_GEN_SBE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CHIP_ID_WIDTH {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CKE_PER_DIMM {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CKE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CK_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_COL_ADDR_WIDTH {10} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CS_PER_DIMM {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CTRL_CFG_READ_ODT_CHIP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CTRL_CFG_READ_ODT_RANK {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CTRL_CFG_WRITE_ODT_CHIP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_CTRL_CFG_WRITE_ODT_RANK {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DB_DQ_DRV_ENUM {DDR4_DB_DRV_STR_RZQ_7} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DB_RTT_NOM_ENUM {DDR4_DB_RTT_NOM_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DB_RTT_PARK_ENUM {DDR4_DB_RTT_PARK_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DB_RTT_WR_ENUM {DDR4_DB_RTT_WR_RZQ_3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DEFAULT_VREFOUT {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DISCRETE_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DLL_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DM_EN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DQS_WIDTH {18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DQ_PER_DQS {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DQ_WIDTH {72} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_DRV_STR_ENUM {DDR4_DRV_STR_RZQ_7} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_FINE_GRANULARITY_REFRESH {DDR4_FINE_REFRESH_FIXED_1X} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_FORMAT_ENUM {MEM_FORMAT_RDIMM} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_GEARDOWN {DDR4_GEARDOWN_HR} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_HIDE_ADV_MR_SETTINGS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_IDEAL_VREF_IN_PCT {68.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_IDEAL_VREF_OUT_PCT {70.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM {DDR4_DB_DRV_STR_RZQ_7} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM_DISP {RZQ/7 (34 Ohm)} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM {DDR4_DB_RTT_NOM_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM_DISP {RTT_NOM disabled} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM {DDR4_DB_RTT_PARK_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM_DISP {RTT_PARK disabled} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM {DDR4_DB_RTT_WR_RZQ_3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM_DISP {RZQ/3 (80 Ohm)} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM {DDR4_DRV_STR_RZQ_7} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM_DISP {RZQ/7 (34 Ohm)} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM {DDR4_RTT_NOM_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM_DISP {ODT Disabled} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM {DDR4_RTT_PARK_RZQ_4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM_DISP {RZQ/4 (60 Ohm)} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM {DDR4_RTT_WR_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM_DISP {Dynamic ODT off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTEL_DEFAULT_TERM {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_INTERNAL_VREFDQ_MONITOR {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_LRDIMM_EXTENDED_CONFIG {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_LRDIMM_ODT_LESS_BS {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM {240} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_LRDIMM_VREFDQ_VALUE {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_MAX_POWERDOWN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_MIRROR_ADDRESSING_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_MPR_READ_FORMAT {DDR4_MPR_READ_FORMAT_SERIAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_MR0 {2672} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_MR1 {65537} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_MR2 {131104} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_MR3 {197632} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_MR4 {264192} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_MR5 {327776} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_MR6 {397327} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_NUM_OF_DIMMS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_NUM_OF_LOGICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_NUM_OF_PHYSICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ODT_IN_POWERDOWN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ODT_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_PER_DRAM_ADDR {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RANKS_PER_DIMM {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RCD_CA_IBT_ENUM {DDR4_RCD_CA_IBT_100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RCD_CKE_IBT_ENUM {DDR4_RCD_CKE_IBT_100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RCD_COMMAND_LATENCY {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RCD_CS_IBT_ENUM {DDR4_RCD_CS_IBT_100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RCD_ODT_IBT_ENUM {DDR4_RCD_ODT_IBT_100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RCD_PARITY_CONTROL_WORD {13} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RDIMM_CONFIG {00000020000000004700001D40040B0F001000} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_READ_DBI {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_READ_PREAMBLE {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_READ_PREAMBLE_TRAINING {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RM_WIDTH {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_ROW_ADDR_WIDTH {17} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RTT_NOM_ENUM {DDR4_RTT_NOM_RZQ_4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RTT_PARK {DDR4_RTT_PARK_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_RTT_WR_ENUM {DDR4_RTT_WR_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_DERIVED_BODT0 {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_DERIVED_BODT1 {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_DERIVED_BODTN {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_DERIVED_ODT0 {(Drive)\ RZQ/7\ (34\ Ohm) - - -} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_DERIVED_ODT1 {- - - -} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_DERIVED_ODT2 {- - - -} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_DERIVED_ODT3 {- - - -} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_DERIVED_ODTN {Rank\ 0 - - -} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODT0_1X1 {off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODT0_2X2 {off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODT0_4X2 {off off on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODT0_4X4 {off off on off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODT1_2X2 {off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODT1_4X2 {on on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODT1_4X4 {off off off on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODT2_4X4 {on off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODT3_4X4 {off on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODTN_1X1 {Rank 0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SELF_RFSH_ABORT {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SEQ_ODT_TABLE_HI {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SEQ_ODT_TABLE_LO {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_135_RCD_REV {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_137_RCD_CA_DRV {16} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_138_RCD_CK_DRV {64} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_139_DB_REV {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 {29} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 {29} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 {29} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 {29} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_144_DB_VREFDQ {37} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_145_DB_MDQ_DRV {21} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_148_DRAM_DRV {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM {20} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_152_DRAM_RTT_PARK {39} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPD_155_DB_VREFDQ_RANGE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_SPEEDBIN_ENUM {DDR4_SPEEDBIN_2933} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TCCD_L_CYC {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TCCD_S_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TCL {19} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDIVW_DJ_CYC {0.1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDIVW_TOTAL_UI {0.23} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDQSCKDL {1200} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDQSCKDM {900} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDQSCKDS {450} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDQSCK_DERV_PS {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDQSCK_PS {170} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDQSQ_PS {66} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDQSQ_UI {0.18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDQSS_CYC {0.27} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDSH_CYC {0.18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDSS_CYC {0.18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TDVWP_UI {0.72} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE {DDR4_TEMP_CONTROLLED_RFSH_NORMAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TEMP_SENSOR_READOUT {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TFAW_CYC {15} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TFAW_DLR_CYC {16} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TFAW_NS {10.875} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TIH_DC_MV {65} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TIH_PS {73} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TINIT_CK {666667} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TINIT_US {500} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TIS_AC_MV {90} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TIS_PS {48} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TMRD_CK_CYC {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TQH_CYC {0.38} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TQH_UI {0.74} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TQSH_CYC {0.4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRAS_CYC {43} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRAS_NS {32.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRCD_CYC {20} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRCD_NS {14.32} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TREFI_CYC {10400} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TREFI_US {7.8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRFC_CYC {467} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRFC_DLR_CYC {160} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRFC_DLR_NS {120.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRFC_NS {350.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRP_CYC {20} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRP_NS {14.32} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRRD_DLR_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRRD_L_CYC {6} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRRD_S_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TRTP_CYC {10} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_ADDR_WIDTH {17} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_BANK_ADDR_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_BANK_GROUP_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_CHIP_ID_WIDTH {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_CKE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_CK_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_DQS_WIDTH {18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_DQ_WIDTH {72} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_NUM_OF_DIMMS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_NUM_OF_LOGICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_NUM_OF_PHYSICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_ODT_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TTL_RM_WIDTH {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TWLH_CYC {0.13} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TWLH_PS {0.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TWLS_CYC {0.13} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TWLS_PS {0.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TWR_CYC {20} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TWR_NS {15.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TWTR_L_CYC {11} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_TWTR_S_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_USER_VREFDQ_TRAINING_RANGE {DDR4_VREFDQ_TRAINING_RANGE_1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_USER_VREFDQ_TRAINING_VALUE {56.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_USE_DEFAULT_ODT {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_VDIVW_TOTAL {115} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_VREFDQ_TRAINING_RANGE {DDR4_VREFDQ_TRAINING_RANGE_0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP {Range 1 - 60% to 92.5%} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_VREFDQ_TRAINING_VALUE {70.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_WRITE_CMD_LATENCY {6} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_WRITE_CRC {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_WRITE_DBI {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_WRITE_PREAMBLE {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_WTCL {14} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_DERIVED_BODT0 {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_DERIVED_BODT1 {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_DERIVED_BODTN {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_DERIVED_ODT0 {(Park)\ RZQ/4\ (60\ Ohm) - - -} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_DERIVED_ODT1 {- - - -} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_DERIVED_ODT2 {- - - -} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_DERIVED_ODT3 {- - - -} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_DERIVED_ODTN {Rank\ 0 - - -} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODT0_1X1 {on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODT0_2X2 {on off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODT0_4X2 {off off on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODT0_4X4 {on off on off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODT1_2X2 {off on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODT1_4X2 {on on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODT1_4X4 {off on off on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODT2_4X4 {on off on off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODT3_4X4 {off on off on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODTN_1X1 {Rank 0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDR4_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_AC_PARITY_LATENCY {DDRT_AC_PARITY_LATENCY_DISABLE} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_AC_PERSISTENT_ERROR {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ADDRESS_MIRROR_BITVEC {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ADDR_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ALERT_N_AC_LANE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ALERT_N_AC_PIN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ALERT_N_DQS_GROUP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ALERT_N_PLACEMENT_ENUM {DDRT_ALERT_N_PLACEMENT_AUTO} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ALERT_PAR_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ASR_ENUM {DDRT_ASR_MANUAL_NORMAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ATCL_ENUM {DDRT_ATCL_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_BANK_ADDR_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_BANK_GROUP_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_BL_ENUM {DDRT_BL_BL8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_BT_ENUM {DDRT_BT_SEQUENTIAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CAL_MODE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CFG_GEN_DBE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CFG_GEN_SBE {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CHIP_ID_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CKE_PER_DIMM {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CKE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CK_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_COL_ADDR_WIDTH {10} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CS_PER_DIMM {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CTRL_CFG_READ_ODT_CHIP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CTRL_CFG_READ_ODT_RANK {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CTRL_CFG_WRITE_ODT_CHIP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_CTRL_CFG_WRITE_ODT_RANK {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DB_DQ_DRV_ENUM {DDRT_DB_DRV_STR_RZQ_7} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DB_RTT_NOM_ENUM {DDRT_DB_RTT_NOM_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DB_RTT_PARK_ENUM {DDRT_DB_RTT_PARK_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DB_RTT_WR_ENUM {DDRT_DB_RTT_WR_RZQ_4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DEFAULT_ADDED_LATENCY {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DEFAULT_PREAMBLE {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DEFAULT_VREFOUT {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DISCRETE_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DLL_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DM_EN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DQS_WIDTH {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DQ_PER_DQS {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DQ_WIDTH {72} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_DRV_STR_ENUM {DDRT_DRV_STR_RZQ_7} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ERID_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ERR_N_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_FINE_GRANULARITY_REFRESH {DDRT_FINE_REFRESH_FIXED_1X} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_FORMAT_ENUM {MEM_FORMAT_LRDIMM} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_GEARDOWN {DDRT_GEARDOWN_HR} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_GNT_N_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_HIDE_ADV_MR_SETTINGS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_HIDE_LATENCY_SETTINGS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_I2C_DIMM_0_SA {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_I2C_DIMM_1_SA {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_I2C_DIMM_2_SA {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_I2C_DIMM_3_SA {3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_INTERNAL_VREFDQ_MONITOR {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_LRDIMM_EXTENDED_CONFIG {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_LRDIMM_ODT_LESS_BS {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM {240} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_LRDIMM_VREFDQ_VALUE {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_MAX_POWERDOWN {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_MIRROR_ADDRESSING_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_MPR_READ_FORMAT {DDRT_MPR_READ_FORMAT_SERIAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_MR0 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_MR1 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_MR2 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_MR3 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_MR4 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_MR5 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_MR6 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_NUM_OF_DIMMS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_NUM_OF_LOGICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_NUM_OF_PHYSICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ODT_IN_POWERDOWN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ODT_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_PARTIAL_WRITES {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_PERSISTENT_MODE {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_PER_DRAM_ADDR {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_PWR_MODE {DDRT_PWR_MODE_12W} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RANKS_PER_DIMM {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RCD_CA_IBT_ENUM {DDRT_RCD_CA_IBT_100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RCD_CKE_IBT_ENUM {DDRT_RCD_CKE_IBT_100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RCD_COMMAND_LATENCY {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RCD_CS_IBT_ENUM {DDRT_RCD_CS_IBT_100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RCD_ODT_IBT_ENUM {DDRT_RCD_ODT_IBT_100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RCD_PARITY_CONTROL_WORD {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RDIMM_CONFIG {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_READ_DBI {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_READ_PREAMBLE {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_READ_PREAMBLE_TRAINING {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_REQ_N_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RM_WIDTH {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_ROW_ADDR_WIDTH {18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RTT_NOM_ENUM {DDRT_RTT_NOM_RZQ_4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RTT_PARK {DDRT_RTT_PARK_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_RTT_WR_ENUM {DDRT_RTT_WR_ODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_DERIVED_BODT0 {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_DERIVED_BODT1 {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_DERIVED_BODTN {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_DERIVED_ODT0 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_DERIVED_ODT1 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_DERIVED_ODT2 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_DERIVED_ODT3 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_DERIVED_ODTN {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODT0_1X1 {off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODT0_2X2 {off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODT0_4X2 {off off on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODT0_4X4 {off off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODT1_2X2 {off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODT1_4X2 {on on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODT1_4X4 {off off on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODT2_4X4 {off off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODT3_4X4 {on on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODTN_1X1 {Rank 0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SELF_RFSH_ABORT {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SEQ_ODT_TABLE_HI {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SEQ_ODT_TABLE_LO {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_135_RCD_REV {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_137_RCD_CA_DRV {85} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_138_RCD_CK_DRV {5} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_139_DB_REV {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_140_DRAM_VREFDQ_R0 {29} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_141_DRAM_VREFDQ_R1 {29} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_142_DRAM_VREFDQ_R2 {29} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_143_DRAM_VREFDQ_R3 {29} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_144_DB_VREFDQ {25} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_145_DB_MDQ_DRV {21} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_148_DRAM_DRV {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM {20} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPD_152_DRAM_RTT_PARK {39} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_SPEEDBIN_ENUM {DDRT_SPEEDBIN_2400} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TCCD_L_CYC {6} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TCCD_S_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TCL {15} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TCL_ADDED {-1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDIVW_DJ_CYC {0.1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDIVW_TOTAL_UI {0.2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDQSCKDL {1200} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDQSCKDM {900} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDQSCKDS {450} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDQSCK_DERV_PS {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDQSCK_PS {165} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDQSQ_PS {66} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDQSQ_UI {0.16} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDQSS_CYC {0.27} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDSH_CYC {0.18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDSS_CYC {0.18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TDVWP_UI {0.72} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE {DDRT_TEMP_CONTROLLED_RFSH_NORMAL} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TEMP_SENSOR_READOUT {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TFAW_CYC {27} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TFAW_DLR_CYC {16} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TFAW_NS {21.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TIH_DC_MV {75} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TIH_PS {95} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TINIT_CK {499} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TINIT_US {500} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TIS_AC_MV {100} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TIS_PS {60} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TMRD_CK_CYC {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TQH_CYC {0.38} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TQH_UI {0.76} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TQSH_CYC {0.38} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRAS_CYC {36} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRAS_NS {32.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRCD_CYC {14} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRCD_NS {15.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TREFI_CYC {8320} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TREFI_US {7.8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRFC_CYC {171} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRFC_DLR_CYC {109} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRFC_DLR_NS {90.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRFC_NS {260.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRP_CYC {14} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRP_NS {15.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRRD_DLR_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRRD_L_CYC {6} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRRD_S_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TRTP_CYC {9} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_ADDR_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_BANK_ADDR_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_BANK_GROUP_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_CHIP_ID_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_CKE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_CK_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_DQS_WIDTH {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_DQ_WIDTH {72} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_ERID_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_ERR_N_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_GNT_N_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_NUM_OF_DIMMS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_NUM_OF_LOGICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_NUM_OF_PHYSICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_ODT_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_REQ_N_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TTL_RM_WIDTH {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TWLH_CYC {0.13} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TWLH_PS {0.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TWLS_CYC {0.13} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TWLS_PS {0.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TWR_CYC {18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TWR_NS {15.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TWTR_L_CYC {9} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_TWTR_S_CYC {3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_USER_READ_PREAMBLE {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_USER_TCL_ADDED {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_USER_VREFDQ_TRAINING_RANGE {DDRT_VREFDQ_TRAINING_RANGE_1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_USER_VREFDQ_TRAINING_VALUE {56.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_USER_WRITE_PREAMBLE {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_USER_WTCL_ADDED {6} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_USE_DEFAULT_ODT {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_VDIVW_TOTAL {136} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_VREFDQ_TRAINING_RANGE {DDRT_VREFDQ_TRAINING_RANGE_1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_VREFDQ_TRAINING_RANGE_DISP {Range 2 - 45% to 77.5%} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_VREFDQ_TRAINING_VALUE {56.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_WRITE_CMD_LATENCY {5} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_WRITE_CRC {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_WRITE_DBI {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_WRITE_PREAMBLE {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_WTCL {18} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_WTCL_ADDED {-1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_DERIVED_BODT0 {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_DERIVED_BODT1 {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_DERIVED_BODTN {} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_DERIVED_ODT0 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_DERIVED_ODT1 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_DERIVED_ODT2 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_DERIVED_ODT3 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_DERIVED_ODTN {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODT0_1X1 {on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODT0_2X2 {on off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODT0_4X2 {off off on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODT0_4X4 {on on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODT1_2X2 {off on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODT1_4X2 {on on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODT1_4X4 {off off on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODT2_4X4 {off off on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODT3_4X4 {on on off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODTN_1X1 {Rank 0} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_DDRT_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_FORMAT_ENUM {MEM_FORMAT_RDIMM} + set_instance_parameter_value sys_ddr4_cntrl MEM_HAS_BSI_SUPPORT {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_HAS_SIM_SUPPORT {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_ADDR_WIDTH {10} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_BANK_ADDR_WIDTH {3} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_BL {LPDDR3_BL_BL8} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_CKE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_CK_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_COL_ADDR_WIDTH {10} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_CTRL_CFG_READ_ODT_CHIP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_CTRL_CFG_READ_ODT_RANK {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_CTRL_CFG_WRITE_ODT_CHIP {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_CTRL_CFG_WRITE_ODT_RANK {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_DATA_LATENCY {LPDDR3_DL_RL12_WL6} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_DISCRETE_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_DM_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_DM_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_DQODT {LPDDR3_DQODT_DISABLE} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_DQS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_DQ_PER_DQS {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_DQ_WIDTH {32} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_DRV_STR {LPDDR3_DRV_STR_40D_40U} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_FORMAT_ENUM {MEM_FORMAT_DISCRETE} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_MR1 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_MR11 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_MR2 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_MR3 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_NUM_OF_LOGICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_NUM_OF_PHYSICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_NWR {LPDDR3_NWR_NWR12} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_ODT_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_PDODT {LPDDR3_PDODT_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_ROW_ADDR_WIDTH {15} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_DERIVED_ODT0 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_DERIVED_ODT1 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_DERIVED_ODT2 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_DERIVED_ODT3 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_DERIVED_ODTN {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_ODT0_1X1 {off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_ODT0_2X2 {off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_ODT0_4X4 {off off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_ODT1_2X2 {off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_ODT1_4X4 {off off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_ODT2_4X4 {off off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_ODT3_4X4 {off off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_ODTN_1X1 {Rank 0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_SEQ_ODT_TABLE_HI {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_SEQ_ODT_TABLE_LO {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_SPEEDBIN_ENUM {LPDDR3_SPEEDBIN_1600} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDH_DC_MV {100} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDH_PS {100} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDQSCKDL {614} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDQSCKDM {511} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDQSCKDS {220} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDQSCK_DERV_PS {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDQSCK_PS {5500} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDQSQ_PS {135} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDQSS_CYC {1.25} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDSH_CYC {0.2} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDSS_CYC {0.2} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDS_AC_MV {150} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TDS_PS {75} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TFAW_CYC {40} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TFAW_NS {50.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TIH_DC_MV {100} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TIH_PS {100} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TINIT_CK {499} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TINIT_US {500} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TIS_AC_MV {150} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TIS_PS {75} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TMRR_CK_CYC {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TMRW_CK_CYC {10} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TQH_CYC {0.38} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TQSH_CYC {0.38} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRAS_CYC {34} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRAS_NS {42.5} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRCD_CYC {17} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRCD_NS {18.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TREFI_CYC {3120} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TREFI_US {3.9} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRFC_CYC {168} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRFC_NS {210.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRL_CYC {10} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRP_CYC {17} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRP_NS {18.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRRD_CYC {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TRTP_CYC {6} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TWLH_PS {175.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TWLS_PS {175.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TWL_CYC {6} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TWR_CYC {12} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TWR_NS {15.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_TWTR_CYC {6} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_USE_DEFAULT_ODT {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_WLSELECT {Set A} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_DERIVED_ODT0 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_DERIVED_ODT1 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_DERIVED_ODT2 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_DERIVED_ODT3 {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_DERIVED_ODTN {{} {} {}} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_ODT0_1X1 {on} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_ODT0_2X2 {on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_ODT0_4X4 {on on on on} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_ODT1_2X2 {off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_ODT1_4X4 {off off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_ODT2_4X4 {off off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_ODT3_4X4 {off off off off} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_ODTN_1X1 {Rank 0} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_instance_parameter_value sys_ddr4_cntrl MEM_LPDDR3_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value sys_ddr4_cntrl MEM_NUM_OF_DATA_ENDPOINTS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_NUM_OF_LOGICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_NUM_OF_PHYSICAL_RANKS {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_ADDR_WIDTH {19} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_BL {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_BWS_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_BWS_N_PER_DEVICE {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_BWS_N_WIDTH {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_CQ_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_DATA_PER_DEVICE {36} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_DATA_WIDTH {36} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_DEVICE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_FORMAT_ENUM {MEM_FORMAT_DISCRETE} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_INTERNAL_JITTER_NS {0.08} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_K_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_SPEEDBIN_ENUM {QDR2_SPEEDBIN_633} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_TCCQO_NS {0.45} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_TCQDOH_NS {-0.09} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_TCQD_NS {0.09} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_TCQH_NS {0.71} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_THA_NS {0.18} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_THD_NS {0.18} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_TRL_CYC {2.5} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_TSA_NS {0.23} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_TSD_NS {0.23} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_TWL_CYC {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR2_WIDTH_EXPANDED {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_AC_ODT_MODE_ENUM {QDR4_ODT_25_PCT} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_ADDR_INV_ENA {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_ADDR_WIDTH {21} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_AVL_CHNLS {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_BL {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_CK_ODT_MODE_ENUM {QDR4_ODT_25_PCT} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_CR0 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_CR1 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_CR2 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DATA_INV_ENA {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DATA_ODT_MODE_ENUM {QDR4_ODT_25_PCT} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DEVICE_DEPTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DEVICE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DINV_PER_PORT_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DINV_WIDTH {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DK_PER_PORT_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DK_WIDTH {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DQ_PER_PORT_PER_DEVICE {36} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DQ_PER_PORT_WIDTH {36} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DQ_PER_RD_GROUP {18} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DQ_PER_WR_GROUP {18} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_DQ_WIDTH {72} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_FORMAT_ENUM {MEM_FORMAT_DISCRETE} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_MEM_TYPE_ENUM {MEM_XP} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM {QDR4_OUTPUT_DRIVE_25_PCT} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM {QDR4_OUTPUT_DRIVE_25_PCT} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_QK_PER_PORT_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_QK_WIDTH {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_SKIP_ODT_SWEEPING {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_SPEEDBIN_ENUM {QDR4_SPEEDBIN_2133} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_TASH_PS {170} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_TCKDK_MAX_PS {150} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_TCKDK_MIN_PS {-150} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_TCKQK_MAX_PS {225} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_TCSH_PS {170} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_TISH_PS {150} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_TQH_CYC {0.4} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_TQKQ_MAX_PS {75} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_TRL_CYC {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_TWL_CYC {5} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_USE_ADDR_PARITY {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_QDR4_WIDTH_EXPANDED {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_READ_LATENCY {22.0} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_ADDR_WIDTH {21} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_BANK_ADDR_WIDTH {3} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_BL {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_CONFIG_ENUM {RLD2_CONFIG_TRC_8_TRL_8_TWL_9} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_DEVICE_DEPTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_DEVICE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_DK_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_DM_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_DM_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_DQ_PER_DEVICE {9} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_DQ_PER_RD_GROUP {9} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_DQ_PER_WR_GROUP {9} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_DQ_WIDTH {9} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_DRIVE_IMPEDENCE_ENUM {RLD2_DRIVE_IMPEDENCE_INTERNAL_50} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_FORMAT_ENUM {MEM_FORMAT_DISCRETE} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_MR {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_ODT_MODE_ENUM {RLD2_ODT_ON} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_QK_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_REFRESH_INTERVAL_US {0.24} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_SPEEDBIN_ENUM {RLD2_SPEEDBIN_18} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TAH_NS {0.3} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TAS_NS {0.3} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TCKDK_MAX_NS {0.3} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TCKDK_MIN_NS {-0.3} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TCKH_CYC {0.45} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TCKQK_MAX_NS {0.2} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TDH_NS {0.17} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TDS_NS {0.17} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TQKH_HCYC {0.9} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TQKQ_MAX_NS {0.12} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TQKQ_MIN_NS {-0.12} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TRC {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TRL {8} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_TWL {9} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD2_WIDTH_EXPANDED {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_ADDR_WIDTH {20} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_AREF_PROTOCOL_ENUM {RLD3_AREF_BAC} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_BANK_ADDR_WIDTH {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_BL {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_CS_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DATA_LATENCY_MODE_ENUM {RLD3_DL_RL16_WL17} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DEPTH_EXPANDED {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DEVICE_DEPTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DEVICE_WIDTH {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DK_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DM_EN {1} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DM_WIDTH {2} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DQ_PER_DEVICE {36} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DQ_PER_RD_GROUP {9} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DQ_PER_WR_GROUP {18} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_DQ_WIDTH {36} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_FORMAT_ENUM {MEM_FORMAT_DISCRETE} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_MR0 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_MR1 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_MR2 {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_ODT_MODE_ENUM {RLD3_ODT_40} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM {RLD3_OUTPUT_DRIVE_40} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_QK_WIDTH {4} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_SPEEDBIN_ENUM {RLD3_SPEEDBIN_093E} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TCKDK_MAX_CYC {0.27} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TCKDK_MIN_CYC {-0.27} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TCKQK_MAX_PS {135} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TDH_DC_MV {100} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TDH_PS {5} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TDS_AC_MV {150} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TDS_PS {-30} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TIH_DC_MV {100} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TIH_PS {65} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TIS_AC_MV {150} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TIS_PS {85} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TQH_CYC {0.38} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_TQKQ_MAX_PS {75} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_T_RC_MODE_ENUM {RLD3_TRC_9} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_WIDTH_EXPANDED {0} + set_instance_parameter_value sys_ddr4_cntrl MEM_RLD3_WRITE_PROTOCOL_ENUM {RLD3_WRITE_1BANK} + set_instance_parameter_value sys_ddr4_cntrl MEM_TTL_DATA_WIDTH {72} + set_instance_parameter_value sys_ddr4_cntrl MEM_TTL_NUM_OF_READ_GROUPS {18} + set_instance_parameter_value sys_ddr4_cntrl MEM_TTL_NUM_OF_WRITE_GROUPS {18} + set_instance_parameter_value sys_ddr4_cntrl MEM_WRITE_LATENCY {17} + set_instance_parameter_value sys_ddr4_cntrl NUM_IPS_SAVED {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_AC_CALIBRATED_OCT {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_AC_DEEMPHASIS_ENUM {DEEMPHASIS_MODE_OFF} + set_instance_parameter_value sys_ddr4_cntrl PHY_AC_IO_STD_ENUM {IO_STD_SSTL_12} + set_instance_parameter_value sys_ddr4_cntrl PHY_AC_MODE_ENUM {OUT_OCT_40_CAL} + set_instance_parameter_value sys_ddr4_cntrl PHY_CALIBRATED_OCT {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_CK_CALIBRATED_OCT {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_CK_DEEMPHASIS_ENUM {DEEMPHASIS_MODE_OFF} + set_instance_parameter_value sys_ddr4_cntrl PHY_CK_IO_STD_ENUM {IO_STD_SSTL_12} + set_instance_parameter_value sys_ddr4_cntrl PHY_CK_MODE_ENUM {OUT_OCT_40_CAL} + set_instance_parameter_value sys_ddr4_cntrl PHY_CLAMSHELL_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_CONFIG_ENUM {CONFIG_PHY_AND_HARD_CTRL} + set_instance_parameter_value sys_ddr4_cntrl PHY_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl PHY_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DATA_CALIBRATED_OCT {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DATA_IO_STD_ENUM {IO_STD_POD_12} + set_instance_parameter_value sys_ddr4_cntrl PHY_DATA_OUT_DEEMPHASIS_ENUM {DEEMPHASIS_MODE_HIGH} + set_instance_parameter_value sys_ddr4_cntrl PHY_DATA_OUT_MODE_ENUM {OUT_OCT_40_CAL} + set_instance_parameter_value sys_ddr4_cntrl PHY_DATA_OUT_SLEW_RATE_ENUM {} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_CAL_ADDR0 {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_CAL_ADDR1 {8} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_CAL_ENABLE_NON_DES {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_DEFAULT_IO {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_DEFAULT_REF_CLK_FREQ {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_HPS_ENABLE_EARLY_RELEASE {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_IO_VOLTAGE {1.5} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_MEM_CLK_FREQ_MHZ {1066.667} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_MIMIC_HPS_EMIF {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_RATE_ENUM {RATE_QUARTER} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_REF_CLK_JITTER_PS {10.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_DLL_CORE_UPDN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR3_USER_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_AC_DEEMPHASIS_ENUM {DEEMPHASIS_MODE_OFF} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_AC_IO_STD_ENUM {IO_STD_SSTL_12} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_AC_MODE_ENUM {OUT_OCT_40_CAL} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_AC_SLEW_RATE_ENUM {SLEW_RATE_FM_FAST} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_ALLOW_72_DQ_WIDTH {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_CK_DEEMPHASIS_ENUM {DEEMPHASIS_MODE_OFF} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_CK_IO_STD_ENUM {IO_STD_SSTL_12} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_CK_MODE_ENUM {OUT_OCT_40_CAL} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_CK_SLEW_RATE_ENUM {SLEW_RATE_FM_FAST} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_CLAMSHELL_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_DATA_IN_MODE_ENUM {IN_OCT_60_CAL} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_DATA_IO_STD_ENUM {IO_STD_POD_12} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_DATA_OUT_DEEMPHASIS_ENUM {DEEMPHASIS_MODE_HIGH} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_DATA_OUT_MODE_ENUM {OUT_OCT_40_CAL} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_DATA_OUT_SLEW_RATE_ENUM {SLEW_RATE_FM_FAST} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_DEFAULT_IO {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_DEFAULT_REF_CLK_FREQ {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_HPS_ENABLE_EARLY_RELEASE {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_IO_VOLTAGE {1.2} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_MEM_CLK_FREQ_MHZ {1333.333} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_MIMIC_HPS_EMIF {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM {IO_STD_TRUE_DIFF_SIGNALING} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_RATE_ENUM {RATE_QUARTER} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_REF_CLK_FREQ_MHZ {166.667} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_REF_CLK_JITTER_PS {10.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_RZQ_IO_STD_ENUM {IO_STD_CMOS_12} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_STARTING_VREFIN {68.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_CLAMSHELL_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_DLL_CORE_UPDN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_REF_CLK_FREQ_MHZ {166.667} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDR4_USER_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_2CH_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_AC_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_DEFAULT_IO {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_DEFAULT_REF_CLK_FREQ {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_EXPORT_CLK_STP_IF {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_HPS_ENABLE_EARLY_RELEASE {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_I2C_USE_SMC {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_IC_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_IO_VOLTAGE {1.2} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_MEM_CLK_FREQ_MHZ {1200.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_MIMIC_HPS_EMIF {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_RATE_ENUM {RATE_QUARTER} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_REF_CLK_JITTER_PS {10.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_AC_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_DLL_CORE_UPDN_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USER_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DDRT_USE_OLD_SMBUS_MULTICOL {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_DLL_CORE_UPDN_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_FPGA_SPEEDGRADE_GUI {E1V (ES3) - change device under 'View'->'Device Family'} + set_instance_parameter_value sys_ddr4_cntrl PHY_HPS_ENABLE_EARLY_RELEASE {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_DEFAULT_IO {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_DEFAULT_REF_CLK_FREQ {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_IO_VOLTAGE {1.2} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_MEM_CLK_FREQ_MHZ {800.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_MIMIC_HPS_EMIF {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_RATE_ENUM {RATE_QUARTER} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_REF_CLK_JITTER_PS {10.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_DLL_CORE_UPDN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_LPDDR3_USER_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_MEM_CLK_FREQ_MHZ {1333.333} + set_instance_parameter_value sys_ddr4_cntrl PHY_MIMIC_HPS_EMIF {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_DEFAULT_IO {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_DEFAULT_REF_CLK_FREQ {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_HPS_ENABLE_EARLY_RELEASE {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_IO_VOLTAGE {1.5} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_MEM_CLK_FREQ_MHZ {633.333} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_MIMIC_HPS_EMIF {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_RATE_ENUM {RATE_HALF} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_REF_CLK_JITTER_PS {10.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_DLL_CORE_UPDN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR2_USER_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_DEFAULT_IO {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_DEFAULT_REF_CLK_FREQ {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_HPS_ENABLE_EARLY_RELEASE {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_IO_VOLTAGE {1.2} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_MEM_CLK_FREQ_MHZ {1066.667} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_MIMIC_HPS_EMIF {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_RATE_ENUM {RATE_QUARTER} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_REF_CLK_JITTER_PS {10.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_DLL_CORE_UPDN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_QDR4_USER_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RATE_ENUM {RATE_QUARTER} + set_instance_parameter_value sys_ddr4_cntrl PHY_REF_CLK_FREQ_MHZ {166.667} + set_instance_parameter_value sys_ddr4_cntrl PHY_REF_CLK_JITTER_PS {10.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_DEFAULT_IO {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_DEFAULT_REF_CLK_FREQ {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_HPS_ENABLE_EARLY_RELEASE {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_IO_VOLTAGE {1.8} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_MEM_CLK_FREQ_MHZ {533.333} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_MIMIC_HPS_EMIF {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_RATE_ENUM {RATE_HALF} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_REF_CLK_JITTER_PS {10.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_DLL_CORE_UPDN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD2_USER_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_DEFAULT_IO {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_DEFAULT_REF_CLK_FREQ {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_HPS_ENABLE_EARLY_RELEASE {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_IO_VOLTAGE {1.2} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_MEM_CLK_FREQ_MHZ {1066.667} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_MIMIC_HPS_EMIF {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_RATE_ENUM {RATE_QUARTER} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_REF_CLK_JITTER_PS {10.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_AC_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_AC_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_AC_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_AC_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_CK_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_CK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_CK_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_CK_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_DATA_IN_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_DATA_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_DATA_OUT_MODE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_DLL_CORE_UPDN_EN {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_PING_PONG_EN {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_REF_CLK_FREQ_MHZ {-1.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_RZQ_IO_STD_ENUM {unset} + set_instance_parameter_value sys_ddr4_cntrl PHY_RLD3_USER_STARTING_VREFIN {70.0} + set_instance_parameter_value sys_ddr4_cntrl PHY_RZQ {240} + set_instance_parameter_value sys_ddr4_cntrl PHY_TARGET_IS_ES {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_TARGET_IS_ES2 {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_TARGET_IS_ES3 {1} + set_instance_parameter_value sys_ddr4_cntrl PHY_TARGET_IS_PRODUCTION {0} + set_instance_parameter_value sys_ddr4_cntrl PHY_TARGET_SPEEDGRADE {E1V} + set_instance_parameter_value sys_ddr4_cntrl PHY_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value sys_ddr4_cntrl PLL_ADD_EXTRA_CLKS {0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_0 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_1 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_2 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_3 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_4 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_5 {1333.333} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_6 {1333.333} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_7 {1333.333} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_8 {1333.333} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_0 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_1 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_2 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_3 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_4 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_5 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_6 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_7 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_8 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 {50.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 {0.0} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 {ps} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 {ps} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 {ps} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 {ps} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 {ps} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 {ps} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 {ps} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 {ps} + set_instance_parameter_value sys_ddr4_cntrl PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 {ps} + set_instance_parameter_value sys_ddr4_cntrl PLL_NUM_OF_EXTRA_CLKS {0} + set_instance_parameter_value sys_ddr4_cntrl PLL_USER_NUM_OF_EXTRA_CLKS {0} + set_instance_parameter_value sys_ddr4_cntrl PLL_VCO_CLK_FREQ_MHZ {1333.333} + set_instance_parameter_value sys_ddr4_cntrl PREV_PROTOCOL_ENUM {PROTOCOL_DDR4} + set_instance_parameter_value sys_ddr4_cntrl SHORT_QSYS_INTERFACE_NAMES {1} + set_instance_parameter_value sys_ddr4_cntrl SYS_INFO_DEVICE {AGIB027R31B1E1V} + set_instance_parameter_value sys_ddr4_cntrl SYS_INFO_DEVICE_DIE_REVISIONS {HSSI_GDR_REVB MAIN_FM8_REVA} + set_instance_parameter_value sys_ddr4_cntrl SYS_INFO_DEVICE_FAMILY {Agilex 7} + set_instance_parameter_value sys_ddr4_cntrl SYS_INFO_DEVICE_POWER_MODEL {STANDARD_POWER} + set_instance_parameter_value sys_ddr4_cntrl SYS_INFO_DEVICE_SPEEDGRADE {1} + set_instance_parameter_value sys_ddr4_cntrl SYS_INFO_DEVICE_TEMPERATURE_GRADE {EXTENDED} + set_instance_parameter_value sys_ddr4_cntrl SYS_INFO_UNIQUE_ID {emif_0_emif_0} + set_instance_parameter_value sys_ddr4_cntrl TRAIT_IOBANK_REVISION {IO96A_REVB2} + set_instance_parameter_value sys_ddr4_cntrl TRAIT_SUPPORTS_VID {1} + set_instance_parameter_value sys_ddr4_cntrl DIAG_EXPORT_PLL_LOCKED {1} + + add_instance emif_calbus_ddr4 altera_emif_cal + set_instance_parameter_value emif_calbus_ddr4 DIAG_ENABLE_JTAG_UART {0} + set_instance_parameter_value emif_calbus_ddr4 DIAG_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value emif_calbus_ddr4 DIAG_EXPORT_VJI {0} + set_instance_parameter_value emif_calbus_ddr4 DIAG_EXTRA_CONFIGS {} + set_instance_parameter_value emif_calbus_ddr4 DIAG_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_calbus_ddr4 DIAG_SIM_VERBOSE {0} + set_instance_parameter_value emif_calbus_ddr4 DIAG_SYNTH_FOR_SIM {0} + set_instance_parameter_value emif_calbus_ddr4 NUM_CALBUS_INTERFACE {1} + set_instance_parameter_value emif_calbus_ddr4 SHORT_QSYS_INTERFACE_NAMES {1} + + add_connection emif_calbus_ddr4.emif_calbus_clk sys_ddr4_cntrl.emif_calbus_clk + add_connection emif_calbus_ddr4.emif_calbus_0 sys_ddr4_cntrl.emif_calbus + + add_interface sys_ddr_ref_clk clock sink + set_interface_property sys_ddr_ref_clk EXPORT_OF sys_ddr4_cntrl.pll_ref_clk + add_interface sys_ddr_oct conduit end + set_interface_property sys_ddr_oct EXPORT_OF sys_ddr4_cntrl.oct + add_interface sys_ddr_mem conduit end + set_interface_property sys_ddr_mem EXPORT_OF sys_ddr4_cntrl.mem + add_interface sys_ddr_status conduit end + set_interface_property sys_ddr_status EXPORT_OF sys_ddr4_cntrl.status + + add_interface sys_ddr4_cntrl_reset_n conduit end + set_interface_property sys_ddr4_cntrl_reset_n EXPORT_OF sys_ddr4_cntrl.emif_usr_reset_n + + add_interface sys_ddr4_local_reset conduit end + set_interface_property sys_ddr4_local_reset EXPORT_OF sys_ddr4_cntrl.local_reset_req + + add_interface sys_ddr4_pll_locked conduit end + set_interface_property sys_ddr4_pll_locked EXPORT_OF sys_ddr4_cntrl.pll_locked + + add_interface sys_ddr4_local_reset_status conduit end + set_interface_property sys_ddr4_local_reset_status EXPORT_OF sys_ddr4_cntrl.local_reset_status + } + + add_instance $dac_fifo_name avl_dacfifo + set_instance_parameter_value $dac_fifo_name {ACTIVE_LOW_RESET} {1} + set_instance_parameter_value $dac_fifo_name {DAC_DATA_WIDTH} $dac_data_width + set_instance_parameter_value $dac_fifo_name {DMA_DATA_WIDTH} $dac_dma_data_width + set_instance_parameter_value $dac_fifo_name {AVL_DATA_WIDTH} {512} + set_instance_parameter_value $dac_fifo_name {AVL_ADDRESS_WIDTH} {28} + set_instance_parameter_value $dac_fifo_name {AVL_BASE_ADDRESS} {0} + set_instance_parameter_value $dac_fifo_name {AVL_ADDRESS_LIMIT} {0x10000000} + set_instance_parameter_value $dac_fifo_name {DAC_MEM_ADDRESS_WIDTH} {12} + set_instance_parameter_value $dac_fifo_name {DMA_MEM_ADDRESS_WIDTH} {12} + set_instance_parameter_value $dac_fifo_name {AVL_BURST_LENGTH} {64} + + add_connection sys_ddr4_cntrl.emif_usr_reset_n $dac_fifo_name.avl_reset + add_connection sys_ddr4_cntrl.emif_usr_clk $dac_fifo_name.avl_clock + add_connection $dac_fifo_name.amm_ddr sys_ddr4_cntrl.ctrl_amm_0 + set_connection_parameter_value $dac_fifo_name.amm_ddr/sys_ddr4_cntrl.ctrl_amm_0 baseAddress {0x0} +} diff --git a/projects/common/fm87/fm87_plddr_system_assign.tcl b/projects/common/fm87/fm87_plddr_system_assign.tcl new file mode 100644 index 00000000000..344a987b70f --- /dev/null +++ b/projects/common/fm87/fm87_plddr_system_assign.tcl @@ -0,0 +1,145 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_location_assignment PIN_DL40 -to sys_ddr_mem_mem_dq[3] +set_location_assignment PIN_DM39 -to sys_ddr_mem_mem_dq[0] +set_location_assignment PIN_DR40 -to sys_ddr_mem_mem_dq[2] +set_location_assignment PIN_DP39 -to sys_ddr_mem_mem_dq[1] +set_location_assignment PIN_DL36 -to sys_ddr_mem_mem_dq[4] +set_location_assignment PIN_DM35 -to sys_ddr_mem_mem_dq[5] +set_location_assignment PIN_DR36 -to sys_ddr_mem_mem_dq[6] +set_location_assignment PIN_DP35 -to sys_ddr_mem_mem_dq[7] +set_location_assignment PIN_DG36 -to sys_ddr_mem_mem_dq[8] +set_location_assignment PIN_DF35 -to sys_ddr_mem_mem_dq[9] +set_location_assignment PIN_DJ36 -to sys_ddr_mem_mem_dq[11] +set_location_assignment PIN_DK35 -to sys_ddr_mem_mem_dq[10] +set_location_assignment PIN_DG32 -to sys_ddr_mem_mem_dq[15] +set_location_assignment PIN_DF31 -to sys_ddr_mem_mem_dq[14] +set_location_assignment PIN_DJ32 -to sys_ddr_mem_mem_dq[12] +set_location_assignment PIN_DK31 -to sys_ddr_mem_mem_dq[13] +set_location_assignment PIN_DL34 -to sys_ddr_mem_mem_dq[17] +set_location_assignment PIN_DM33 -to sys_ddr_mem_mem_dq[16] +set_location_assignment PIN_DR34 -to sys_ddr_mem_mem_dq[18] +set_location_assignment PIN_DP33 -to sys_ddr_mem_mem_dq[19] +set_location_assignment PIN_DL30 -to sys_ddr_mem_mem_dq[20] +set_location_assignment PIN_DM29 -to sys_ddr_mem_mem_dq[23] +set_location_assignment PIN_DR30 -to sys_ddr_mem_mem_dq[22] +set_location_assignment PIN_DP29 -to sys_ddr_mem_mem_dq[21] +set_location_assignment PIN_DG30 -to sys_ddr_mem_mem_dq[25] +set_location_assignment PIN_DF29 -to sys_ddr_mem_mem_dq[27] +set_location_assignment PIN_DK29 -to sys_ddr_mem_mem_dq[24] +set_location_assignment PIN_DJ30 -to sys_ddr_mem_mem_dq[26] +set_location_assignment PIN_DG26 -to sys_ddr_mem_mem_dq[30] +set_location_assignment PIN_DF25 -to sys_ddr_mem_mem_dq[29] +set_location_assignment PIN_DJ26 -to sys_ddr_mem_mem_dq[31] +set_location_assignment PIN_DK25 -to sys_ddr_mem_mem_dq[28] +set_location_assignment PIN_DL22 -to sys_ddr_mem_mem_dq[33] +set_location_assignment PIN_DM21 -to sys_ddr_mem_mem_dq[35] +set_location_assignment PIN_DP21 -to sys_ddr_mem_mem_dq[34] +set_location_assignment PIN_DR22 -to sys_ddr_mem_mem_dq[32] +set_location_assignment PIN_DL18 -to sys_ddr_mem_mem_dq[36] +set_location_assignment PIN_DM17 -to sys_ddr_mem_mem_dq[39] +set_location_assignment PIN_DR18 -to sys_ddr_mem_mem_dq[38] +set_location_assignment PIN_DP17 -to sys_ddr_mem_mem_dq[37] +set_location_assignment PIN_DM27 -to sys_ddr_mem_mem_dq[41] +set_location_assignment PIN_DL28 -to sys_ddr_mem_mem_dq[42] +set_location_assignment PIN_DR28 -to sys_ddr_mem_mem_dq[43] +set_location_assignment PIN_DP27 -to sys_ddr_mem_mem_dq[40] +set_location_assignment PIN_DM23 -to sys_ddr_mem_mem_dq[45] +set_location_assignment PIN_DL24 -to sys_ddr_mem_mem_dq[47] +set_location_assignment PIN_DR24 -to sys_ddr_mem_mem_dq[44] +set_location_assignment PIN_DP23 -to sys_ddr_mem_mem_dq[46] +set_location_assignment PIN_DA24 -to sys_ddr_mem_mem_dq[49] +set_location_assignment PIN_DB23 -to sys_ddr_mem_mem_dq[51] +set_location_assignment PIN_DE24 -to sys_ddr_mem_mem_dq[48] +set_location_assignment PIN_DD23 -to sys_ddr_mem_mem_dq[50] +set_location_assignment PIN_DA20 -to sys_ddr_mem_mem_dq[52] +set_location_assignment PIN_DB19 -to sys_ddr_mem_mem_dq[55] +set_location_assignment PIN_DE20 -to sys_ddr_mem_mem_dq[54] +set_location_assignment PIN_DD19 -to sys_ddr_mem_mem_dq[53] +set_location_assignment PIN_DF23 -to sys_ddr_mem_mem_dq[59] +set_location_assignment PIN_DK23 -to sys_ddr_mem_mem_dq[57] +set_location_assignment PIN_DJ24 -to sys_ddr_mem_mem_dq[56] +set_location_assignment PIN_DG24 -to sys_ddr_mem_mem_dq[58] +set_location_assignment PIN_DG20 -to sys_ddr_mem_mem_dq[60] +set_location_assignment PIN_DF19 -to sys_ddr_mem_mem_dq[61] +set_location_assignment PIN_DJ20 -to sys_ddr_mem_mem_dq[62] +set_location_assignment PIN_DK19 -to sys_ddr_mem_mem_dq[63] +set_location_assignment PIN_DA30 -to sys_ddr_mem_mem_dq[65] +set_location_assignment PIN_DB29 -to sys_ddr_mem_mem_dq[64] +set_location_assignment PIN_DE30 -to sys_ddr_mem_mem_dq[66] +set_location_assignment PIN_DD29 -to sys_ddr_mem_mem_dq[67] +set_location_assignment PIN_DA26 -to sys_ddr_mem_mem_dq[68] +set_location_assignment PIN_DB25 -to sys_ddr_mem_mem_dq[69] +set_location_assignment PIN_DD25 -to sys_ddr_mem_mem_dq[70] +set_location_assignment PIN_DE26 -to sys_ddr_mem_mem_dq[71] +set_location_assignment PIN_DR38 -to sys_ddr_mem_mem_dqs_n[0] +set_location_assignment PIN_DP37 -to sys_ddr_mem_mem_dqs_p[0] +set_location_assignment PIN_DL38 -to sys_ddr_mem_mem_dqs_n[1] +set_location_assignment PIN_DM37 -to sys_ddr_mem_mem_dqs_p[1] +set_location_assignment PIN_DJ34 -to sys_ddr_mem_mem_dqs_n[2] +set_location_assignment PIN_DK33 -to sys_ddr_mem_mem_dqs_p[2] +set_location_assignment PIN_DG34 -to sys_ddr_mem_mem_dqs_n[3] +set_location_assignment PIN_DF33 -to sys_ddr_mem_mem_dqs_p[3] +set_location_assignment PIN_DR32 -to sys_ddr_mem_mem_dqs_n[4] +set_location_assignment PIN_DP31 -to sys_ddr_mem_mem_dqs_p[4] +set_location_assignment PIN_DL32 -to sys_ddr_mem_mem_dqs_n[5] +set_location_assignment PIN_DM31 -to sys_ddr_mem_mem_dqs_p[5] +set_location_assignment PIN_DJ28 -to sys_ddr_mem_mem_dqs_n[6] +set_location_assignment PIN_DK27 -to sys_ddr_mem_mem_dqs_p[6] +set_location_assignment PIN_DG28 -to sys_ddr_mem_mem_dqs_n[7] +set_location_assignment PIN_DF27 -to sys_ddr_mem_mem_dqs_p[7] +set_location_assignment PIN_DP19 -to sys_ddr_mem_mem_dqs_n[8] +set_location_assignment PIN_DR20 -to sys_ddr_mem_mem_dqs_p[8] +set_location_assignment PIN_DL20 -to sys_ddr_mem_mem_dqs_n[9] +set_location_assignment PIN_DM19 -to sys_ddr_mem_mem_dqs_p[9] +set_location_assignment PIN_DR26 -to sys_ddr_mem_mem_dqs_n[10] +set_location_assignment PIN_DP25 -to sys_ddr_mem_mem_dqs_p[10] +set_location_assignment PIN_DL26 -to sys_ddr_mem_mem_dqs_n[11] +set_location_assignment PIN_DM25 -to sys_ddr_mem_mem_dqs_p[11] +set_location_assignment PIN_DE22 -to sys_ddr_mem_mem_dqs_n[12] +set_location_assignment PIN_DD21 -to sys_ddr_mem_mem_dqs_p[12] +set_location_assignment PIN_DA22 -to sys_ddr_mem_mem_dqs_n[13] +set_location_assignment PIN_DB21 -to sys_ddr_mem_mem_dqs_p[13] +set_location_assignment PIN_DJ22 -to sys_ddr_mem_mem_dqs_n[14] +set_location_assignment PIN_DK21 -to sys_ddr_mem_mem_dqs_p[14] +set_location_assignment PIN_DF21 -to sys_ddr_mem_mem_dqs_n[15] +set_location_assignment PIN_DG22 -to sys_ddr_mem_mem_dqs_p[15] +set_location_assignment PIN_DE28 -to sys_ddr_mem_mem_dqs_n[16] +set_location_assignment PIN_DD27 -to sys_ddr_mem_mem_dqs_p[16] +set_location_assignment PIN_DA28 -to sys_ddr_mem_mem_dqs_n[17] +set_location_assignment PIN_DB27 -to sys_ddr_mem_mem_dqs_p[17] +set_location_assignment PIN_DD35 -to sys_ddr_ref_clk_clk +set_location_assignment PIN_DA34 -to sys_ddr_mem_mem_a[16] +set_location_assignment PIN_DB33 -to sys_ddr_mem_mem_a[15] +set_location_assignment PIN_DA36 -to sys_ddr_mem_mem_a[12] +set_location_assignment PIN_DE34 -to sys_ddr_mem_mem_a[14] +set_location_assignment PIN_DD33 -to sys_ddr_mem_mem_a[13] +set_location_assignment PIN_CU36 -to sys_ddr_mem_mem_a[11] +set_location_assignment PIN_CT35 -to sys_ddr_mem_mem_a[10] +set_location_assignment PIN_CW36 -to sys_ddr_mem_mem_a[9] +set_location_assignment PIN_CY35 -to sys_ddr_mem_mem_a[8] +set_location_assignment PIN_CU38 -to sys_ddr_mem_mem_a[7] +set_location_assignment PIN_CT37 -to sys_ddr_mem_mem_a[6] +set_location_assignment PIN_CT39 -to sys_ddr_mem_mem_a[3] +set_location_assignment PIN_CU40 -to sys_ddr_mem_mem_a[2] +set_location_assignment PIN_CW40 -to sys_ddr_mem_mem_a[1] +set_location_assignment PIN_CY39 -to sys_ddr_mem_mem_a[0] +set_location_assignment PIN_CW38 -to sys_ddr_mem_mem_a[5] +set_location_assignment PIN_CY37 -to sys_ddr_mem_mem_a[4] +set_location_assignment PIN_CP37 -to sys_ddr_mem_mem_odt +set_location_assignment PIN_CM37 -to sys_ddr_mem_mem_cke +set_location_assignment PIN_CL40 -to sys_ddr_mem_mem_act_n +set_location_assignment PIN_CM39 -to sys_ddr_mem_mem_cs_n +set_location_assignment PIN_CP39 -to sys_ddr_mem_mem_reset_n +set_location_assignment PIN_CR36 -to sys_ddr_mem_mem_clk_n +set_location_assignment PIN_CP35 -to sys_ddr_mem_mem_clk_p +set_location_assignment PIN_CL36 -to sys_ddr_mem_mem_par +set_location_assignment PIN_CY29 -to sys_ddr_mem_mem_alert_n +set_location_assignment PIN_DB35 -to sys_ddr_oct_oct_rzq +set_location_assignment PIN_CR40 -to sys_ddr_mem_mem_bg[1] +set_location_assignment PIN_DA32 -to sys_ddr_mem_mem_bg[0] +set_location_assignment PIN_DB31 -to sys_ddr_mem_mem_ba[1] +set_location_assignment PIN_DE32 -to sys_ddr_mem_mem_ba[0] diff --git a/projects/common/fm87/system_ddr_constr.sdc b/projects/common/fm87/system_ddr_constr.sdc new file mode 100644 index 00000000000..efe774e4d4e --- /dev/null +++ b/projects/common/fm87/system_ddr_constr.sdc @@ -0,0 +1,6 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +create_clock -period "6.000 ns" -name sys_ddr_ref_clk [get_ports {sys_ddr_ref_clk_clk}] From 61342724e9ad700ad17b6b5ab42d451063c7e763 Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Tue, 29 Oct 2024 15:10:44 +0200 Subject: [PATCH 3/4] library: util_pack: pack_shell: Parallelized the prefix sum calculation The old algorithm used NUMBER_OF_SAMPLES adders in series to calculate the prefix sum and this caused a timing violation at high lane rates when NUMBER_OF_SAMPLES was large (e.g 64). The new algorithm uses at most log2(NUMBER_OF_SAMPLES) adders in series for the right most element but more adders overall. Signed-off-by: Bogdan Luncan --- library/util_pack/util_cpack2/util_cpack2.v | 8 +-- .../util_pack/util_cpack2/util_cpack2_hw.tcl | 8 ++- .../util_pack/util_cpack2/util_cpack2_impl.v | 8 +-- .../util_pack/util_cpack2/util_cpack2_ip.tcl | 3 +- .../util_pack/util_pack_common/pack_shell.v | 52 +++++++++++++++++-- library/util_pack/util_upack2/util_upack2.v | 8 +-- .../util_pack/util_upack2/util_upack2_hw.tcl | 7 ++- .../util_pack/util_upack2/util_upack2_impl.v | 8 +-- .../util_pack/util_upack2/util_upack2_ip.tcl | 3 +- 9 files changed, 83 insertions(+), 22 deletions(-) diff --git a/library/util_pack/util_cpack2/util_cpack2.v b/library/util_pack/util_cpack2/util_cpack2.v index 2f573281d23..8baf9b08a55 100644 --- a/library/util_pack/util_cpack2/util_cpack2.v +++ b/library/util_pack/util_cpack2/util_cpack2.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -38,7 +38,8 @@ module util_cpack2 #( parameter NUM_OF_CHANNELS = 4, parameter SAMPLES_PER_CHANNEL = 1, - parameter SAMPLE_DATA_WIDTH = 16 + parameter SAMPLE_DATA_WIDTH = 16, + parameter PARALLEL_OR_SERIAL_N = 0 ) ( input clk, input reset, @@ -282,7 +283,8 @@ module util_cpack2 #( util_cpack2_impl #( .NUM_OF_CHANNELS (REAL_NUM_OF_CHANNELS), .SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH), - .SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL) + .SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL), + .PARALLEL_OR_SERIAL_N (PARALLEL_OR_SERIAL_N) ) i_cpack ( .clk (clk), .reset (reset), diff --git a/library/util_pack/util_cpack2/util_cpack2_hw.tcl b/library/util_pack/util_cpack2/util_cpack2_hw.tcl index fb5b2651921..ea2e58b2177 100644 --- a/library/util_pack/util_cpack2/util_cpack2_hw.tcl +++ b/library/util_pack/util_cpack2/util_cpack2_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -31,6 +31,11 @@ ad_ip_parameter SAMPLE_DATA_WIDTH INTEGER 16 true [list \ DISPLAY_NAME "Sample Data Width" ] +ad_ip_parameter PARALLEL_OR_SERIAL_N INTEGER 0 true [list \ + DISPLAY_NAME "Parallel prefix sum calculation" \ + ALLOWED_RANGES {"0:Serial" "1:Parallel"} \ +] + # defaults proc util_cpack_elab {} { @@ -68,4 +73,3 @@ proc util_cpack_elab {} { set_interface_property adc_ch_$n associatedReset "" } } - diff --git a/library/util_pack/util_cpack2/util_cpack2_impl.v b/library/util_pack/util_cpack2/util_cpack2_impl.v index 722b274effc..4eaf7a93448 100644 --- a/library/util_pack/util_cpack2/util_cpack2_impl.v +++ b/library/util_pack/util_cpack2/util_cpack2_impl.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -38,7 +38,8 @@ module util_cpack2_impl #( parameter NUM_OF_CHANNELS = 4, parameter SAMPLES_PER_CHANNEL = 1, - parameter SAMPLE_DATA_WIDTH = 16 + parameter SAMPLE_DATA_WIDTH = 16, + parameter PARALLEL_OR_SERIAL_N = 0 ) ( input clk, input reset, @@ -100,7 +101,8 @@ module util_cpack2_impl #( .NUM_OF_CHANNELS (NUM_OF_CHANNELS), .SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL), .SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH), - .PACK (1) + .PACK (1), + .PARALLEL_OR_SERIAL_N (PARALLEL_OR_SERIAL_N) ) i_pack_shell ( .clk (clk), .reset (reset), diff --git a/library/util_pack/util_cpack2/util_cpack2_ip.tcl b/library/util_pack/util_cpack2/util_cpack2_ip.tcl index 9be8e4c9de5..58b5f59c6cc 100644 --- a/library/util_pack/util_cpack2/util_cpack2_ip.tcl +++ b/library/util_pack/util_cpack2/util_cpack2_ip.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -39,6 +39,7 @@ foreach {k v} { \ "NUM_OF_CHANNELS" "Number of Channels" \ "SAMPLES_PER_CHANNEL" "Samples per Channel" \ "SAMPLE_DATA_WIDTH" "Sample Width" \ + "PARALLEL_OR_SERIAL_N" "Parallel prefix sum calculation" \ } { \ set p [ipgui::get_guiparamspec -name $k -component $cc] # ipgui::move_param -component $cc -order $i $p -parent $ diff --git a/library/util_pack/util_pack_common/pack_shell.v b/library/util_pack/util_pack_common/pack_shell.v index b838daa945a..148acde5ea4 100644 --- a/library/util_pack/util_pack_common/pack_shell.v +++ b/library/util_pack/util_pack_common/pack_shell.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023, 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -39,7 +39,8 @@ module pack_shell #( parameter NUM_OF_CHANNELS = 4, parameter SAMPLES_PER_CHANNEL = 1, parameter SAMPLE_DATA_WIDTH = 16, - parameter PACK = 0 + parameter PACK = 0, + parameter PARALLEL_OR_SERIAL_N = 0 ) ( input clk, input reset, @@ -65,6 +66,7 @@ module pack_shell #( localparam TOTAL_DATA_WIDTH = CHANNEL_DATA_WIDTH * NUM_OF_CHANNELS; localparam NUM_OF_SAMPLES = NUM_OF_CHANNELS * SAMPLES_PER_CHANNEL; + localparam LOG2_NUM_OF_SAMPLES = $clog2(NUM_OF_SAMPLES); /* * Reset and control signals for the state machine. Data and control have @@ -189,6 +191,11 @@ module pack_shell #( */ wire [SAMPLE_ADDRESS_WIDTH-1:0] prefix_count_s[0:NUM_OF_SAMPLES]; + /* + * Used for the vectorized approach when PARALLEL_OR_SERIAL_N == 1 + */ + wire [SAMPLE_ADDRESS_WIDTH-1:0] prefix_count_tmp[0:LOG2_NUM_OF_SAMPLES+1][0:NUM_OF_SAMPLES-1]; + /* * Samples are interleaved, so the sample mask is just the channel mask * concatenated with itself SAMPLES_PER_CHANNEL times. @@ -201,13 +208,50 @@ module pack_shell #( */ assign ce_ctrl = startup_ctrl | ce; + if (PARALLEL_OR_SERIAL_N == 1) begin + /* + * Calculate the prefix sum using a vectorized approach. + * This way we should have at most log2(NUM_OF_SAMPLES) + * adders in series for the rightmost element and even less + * for the elements before it since we just propagate it to + * the last row from where it was calculated. + */ + + /* Copy the samples_enable to the first row to make addressing it easier */ + genvar j; + for (j = 0; j < NUM_OF_SAMPLES; j = j + 1) begin + assign prefix_count_tmp[0][j] = ~samples_enable[j]; + end + + /* + * E.g: for samples_enable = '1 1 1 1 1 1 1 1': + * prefix_count_tmp[0] = '1 1 1 1 1 1 1 1' (copy of samples_enable) + * prefix_count_tmp[1] = '1 2 2 2 2 2 2 2' + * prefix_count_tmp[2] = '1 2 3 4 4 4 4 4' + * prefix_count_tmp[3] = '1 2 3 4 5 6 7 8' + */ + genvar k; + for (j = 1; j < LOG2_NUM_OF_SAMPLES + 1; j = j + 1) begin + for (k = 0; k < NUM_OF_SAMPLES; k = k + 1) begin + if (k < 2 ** (j-1)) begin + assign prefix_count_tmp[j][k] = prefix_count_tmp[j-1][k]; + end else begin + assign prefix_count_tmp[j][k] = prefix_count_tmp[j-1][k] + prefix_count_tmp[j-1][k - 2 ** (j-1)]; + end + end + end + end + /* First channel has no other channels before it */ assign prefix_count_s[0] = 'h0; genvar i; for (i = 0; i < NUM_OF_SAMPLES; i = i + 1) begin: gen_prefix_count - assign prefix_count_s[i+1] = prefix_count_s[i] + (samples_enable[i] ? 1'b0 : 1'b1); - + if (PARALLEL_OR_SERIAL_N == 1) begin + assign prefix_count_s[i+1] = prefix_count_tmp[LOG2_NUM_OF_SAMPLES][i]; + end else begin + assign prefix_count_s[i+1] = prefix_count_s[i] + (samples_enable[i] ? 1'b0 : 1'b1); + end if (i < 2 || NUM_OF_CHANNELS <= 2) begin /* This will only be one bit, no need to register it */ always @(prefix_count_s[i]) begin diff --git a/library/util_pack/util_upack2/util_upack2.v b/library/util_pack/util_upack2/util_upack2.v index cc9267ae72e..2b80e39a1d8 100644 --- a/library/util_pack/util_upack2/util_upack2.v +++ b/library/util_pack/util_upack2/util_upack2.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -38,7 +38,8 @@ module util_upack2 #( parameter NUM_OF_CHANNELS = 4, parameter SAMPLES_PER_CHANNEL = 1, - parameter SAMPLE_DATA_WIDTH = 16 + parameter SAMPLE_DATA_WIDTH = 16, + parameter PARALLEL_OR_SERIAL_N = 0 ) ( input clk, input reset, @@ -203,7 +204,8 @@ module util_upack2 #( util_upack2_impl #( .NUM_OF_CHANNELS(REAL_NUM_OF_CHANNELS), .SAMPLE_DATA_WIDTH(SAMPLE_DATA_WIDTH), - .SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL) + .SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL), + .PARALLEL_OR_SERIAL_N (PARALLEL_OR_SERIAL_N) ) i_upack ( .clk (clk), .reset (reset), diff --git a/library/util_pack/util_upack2/util_upack2_hw.tcl b/library/util_pack/util_upack2/util_upack2_hw.tcl index 2193c7a7bb0..5aecac42045 100644 --- a/library/util_pack/util_upack2/util_upack2_hw.tcl +++ b/library/util_pack/util_upack2/util_upack2_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -35,6 +35,10 @@ ad_ip_parameter INTERFACE_TYPE INTEGER 0 false [list \ ALLOWED_RANGES {"0:AXIS" "1:FIFO"} \ ] +ad_ip_parameter PARALLEL_OR_SERIAL_N INTEGER 0 true [list \ + DISPLAY_NAME "Parallel prefix sum calculation" \ + ALLOWED_RANGES {"0:Serial" "1:Parallel"} \ +] # defaults @@ -91,4 +95,3 @@ proc util_upack_elab {} { set_interface_property dac_ch_${n} associatedReset "" } } - diff --git a/library/util_pack/util_upack2/util_upack2_impl.v b/library/util_pack/util_upack2/util_upack2_impl.v index 9e9bc4386a2..bd3ec0a197e 100644 --- a/library/util_pack/util_upack2/util_upack2_impl.v +++ b/library/util_pack/util_upack2/util_upack2_impl.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -38,7 +38,8 @@ module util_upack2_impl #( parameter NUM_OF_CHANNELS = 4, parameter SAMPLES_PER_CHANNEL = 1, - parameter SAMPLE_DATA_WIDTH = 16 + parameter SAMPLE_DATA_WIDTH = 16, + parameter PARALLEL_OR_SERIAL_N = 0 ) ( input clk, input reset, @@ -92,7 +93,8 @@ module util_upack2_impl #( .NUM_OF_CHANNELS (NUM_OF_CHANNELS), .SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL), .SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH), - .PACK (0) + .PACK (0), + .PARALLEL_OR_SERIAL_N (PARALLEL_OR_SERIAL_N) ) i_pack_shell ( .clk (clk), .reset (reset), diff --git a/library/util_pack/util_upack2/util_upack2_ip.tcl b/library/util_pack/util_upack2/util_upack2_ip.tcl index 9a1c2b7d287..5152eb87332 100644 --- a/library/util_pack/util_upack2/util_upack2_ip.tcl +++ b/library/util_pack/util_upack2/util_upack2_ip.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -40,6 +40,7 @@ foreach {k v} { \ "NUM_OF_CHANNELS" "Number of Channels" \ "SAMPLES_PER_CHANNEL" "Samples per Channel" \ "SAMPLE_DATA_WIDTH" "Sample Width" \ + "PARALLEL_OR_SERIAL_N" "Parallel prefix sum calculation" \ } { \ set p [ipgui::get_guiparamspec -name $k -component $cc] # ipgui::move_param -component $cc -order $i $p -parent $ From f871a0f799798e71c85d564572b32796cb668a2d Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Thu, 7 Nov 2024 12:15:34 +0200 Subject: [PATCH 4/4] library: adxcvr: Sync inputs for Agilex 7 Signed-off-by: Bogdan Luncan --- library/intel/axi_adxcvr/axi_adxcvr_hw.tcl | 3 +- library/intel/axi_adxcvr/axi_adxcvr_up.v | 99 ++++++++++++++-------- 2 files changed, 67 insertions(+), 35 deletions(-) diff --git a/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl b/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl index d80d14be441..63ab8d32746 100644 --- a/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl +++ b/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2016-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2016-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -20,6 +20,7 @@ set_module_property VALIDATION_CALLBACK info_param_validate # files ad_ip_files axi_adxcvr [list \ + $ad_hdl_dir/library/util_cdc/sync_bits.v \ $ad_hdl_dir/library/common/up_axi.v \ axi_adxcvr_up.v \ axi_adxcvr.v \ diff --git a/library/intel/axi_adxcvr/axi_adxcvr_up.v b/library/intel/axi_adxcvr/axi_adxcvr_up.v index 203c693d8c9..57f68a9b97d 100644 --- a/library/intel/axi_adxcvr/axi_adxcvr_up.v +++ b/library/intel/axi_adxcvr/axi_adxcvr_up.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -81,17 +81,20 @@ module axi_adxcvr_up #( reg up_wreq_d = 'd0; reg [31:0] up_scratch = 'd0; reg up_resetn = 'd0; - reg [ 3:0] up_rst_cnt = 'd8; reg up_status_int = 'd0; reg up_rreq_d = 'd0; reg [31:0] up_rdata_d = 'd0; // internal signals - wire up_ready_s; + wire up_all_ready_s; wire [31:0] up_status_32_s; wire [31:0] up_rparam_s; + wire up_pll_locked_s; + wire up_rx_lockedtodata_s; + wire up_ready_s; + // defaults assign up_wack = up_wreq_d; @@ -120,53 +123,81 @@ module axi_adxcvr_up #( end end - assign up_ready_s = & up_status_32_s[(NUM_OF_LANES-1):0]; + generate if (FPGA_TECHNOLOGY == 105) begin + sync_bits #( + .NUM_OF_BITS (3), + .ASYNC_CLK (1) + ) i_sync_input_ctrl ( + .in_bits ({up_ready, up_pll_locked, up_rx_lockedtodata}), + .out_resetn (1'b1), + .out_clk (up_clk), + .out_bits({up_ready_s, up_pll_locked_s, up_rx_lockedtodata_s})); + end else begin + assign up_ready_s = up_ready; + assign up_pll_locked_s = up_pll_locked; + assign up_rx_lockedtodata_s = up_rx_lockedtodata; + end + endgenerate + + assign up_all_ready_s = & up_status_32_s[(NUM_OF_LANES-1):0]; assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0; - assign up_status_32_s[NUM_OF_LANES] = FPGA_TECHNOLOGY == 105 ? TX_OR_RX_N ? up_pll_locked : up_rx_lockedtodata : - up_pll_locked; - assign up_status_32_s[(NUM_OF_LANES-1):0] = FPGA_TECHNOLOGY == 105 ? {NUM_OF_LANES{up_ready}} : up_ready; + assign up_status_32_s[NUM_OF_LANES] = FPGA_TECHNOLOGY == 105 ? TX_OR_RX_N ? up_pll_locked_s : up_rx_lockedtodata_s : + up_pll_locked_s; + assign up_status_32_s[(NUM_OF_LANES-1):0] = FPGA_TECHNOLOGY == 105 ? {NUM_OF_LANES{up_ready_s}} : up_ready_s; - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rst_cnt <= 4'h8; - up_status_int <= 1'b0; - end else begin - if (up_resetn == 1'b0) begin - up_rst_cnt <= 4'h8; - end else if (up_rst_cnt[3] == 1'b1) begin - up_rst_cnt <= up_rst_cnt + 1'b1; - end - if (up_resetn == 1'b0) begin - up_status_int <= 1'b0; - end else if (up_ready_s == 1'b1) begin - up_status_int <= 1'b1; + generate if (FPGA_TECHNOLOGY == 105) begin + wire up_reset_ack_s; + reg up_rst_d; + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (1) + ) i_sync_reset_ack ( + .in_bits (up_reset_ack), + .out_resetn (1'b1), + .out_clk (up_clk), + .out_bits(up_reset_ack_s)); + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rst_d <= 1'b1; + end else if (up_resetn == 1'b0) begin + up_rst_d <= 1'b1; + end else if (up_reset_ack_s) begin + up_rst_d <= 1'b0; end end - end - - generate if (FPGA_TECHNOLOGY == 105) begin - reg up_reset_ack_d = 'd0; + assign up_rst = up_rst_d; + end else begin + reg [3:0] up_rst_cnt = 'd8; always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_reset_ack_d <= 1'b0; + up_rst_cnt <= 4'h8; end else begin if (up_resetn == 1'b0) begin - up_reset_ack_d <= 1'b0; - end else begin - if (up_reset_ack_d == 1'b0) begin - up_reset_ack_d <= up_reset_ack; - end + up_rst_cnt <= 4'h8; + end else if (up_rst_cnt[3] == 1'b1) begin + up_rst_cnt <= up_rst_cnt + 1'b1; end end end - - assign up_rst = ~up_reset_ack_d; - end else begin assign up_rst = up_rst_cnt[3]; end endgenerate + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_int <= 1'b0; + end else begin + if (up_resetn == 1'b0) begin + up_status_int <= 1'b0; + end else if (up_all_ready_s) begin + up_status_int <= 1'b1; + end + end + end + // Specific to Intel assign up_rparam_s[31:28] = 8'd0;