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Parameterizable AVL dacfifo and parallel pack core #1565

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27599bd
library: intel: avl_dacfifo: Make avl interface parametrizable
bluncan Jan 23, 2025
94bd806
projects: common: fm87: Add external ddr instantiation with avl_dacfifo
bluncan Jan 23, 2025
6134272
library: util_pack: pack_shell: Parallelized the prefix sum calculation
bluncan Oct 29, 2024
f871a0f
library: adxcvr: Sync inputs for Agilex 7
bluncan Nov 7, 2024
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27 changes: 19 additions & 8 deletions library/intel/avl_dacfifo/avl_dacfifo.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -36,7 +36,7 @@
`timescale 1ns/100ps

module avl_dacfifo #(

parameter ACTIVE_LOW_RESET = 0,
parameter DAC_DATA_WIDTH = 64,
parameter DAC_MEM_ADDRESS_WIDTH = 8,
parameter DMA_DATA_WIDTH = 64,
Expand Down Expand Up @@ -102,9 +102,9 @@ module avl_dacfifo #(
wire dma_ready_bypass_s;
wire avl_read_s;
wire avl_write_s;
wire [ 24:0] avl_wr_address_s;
wire [ 24:0] avl_rd_address_s;
wire [ 24:0] avl_last_address_s;
wire [(AVL_ADDRESS_WIDTH-1):0] avl_wr_address_s;
wire [(AVL_ADDRESS_WIDTH-1):0] avl_rd_address_s;
wire [(AVL_ADDRESS_WIDTH-1):0] avl_last_address_s;
wire [ 6:0] avl_last_burstcount_s;
wire [ 7:0] dma_last_beats_s;
wire [ 6:0] avl_wr_burstcount_s;
Expand All @@ -120,9 +120,19 @@ module avl_dacfifo #(
wire dac_dunf_fifo_s;
wire dac_dunf_bypass_s;

wire avl_reset_s;

generate if (ACTIVE_LOW_RESET == 1) begin
assign avl_reset_s = ~avl_reset;
end else begin
assign avl_reset_s = avl_reset;
end
endgenerate

avl_dacfifo_wr #(
.AVL_DATA_WIDTH (AVL_DATA_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.AVL_ADDRESS_WIDTH (AVL_ADDRESS_WIDTH),
.AVL_DDR_BASE_ADDRESS (AVL_BASE_ADDRESS),
.DMA_MEM_ADDRESS_WIDTH(DMA_MEM_ADDRESS_WIDTH),
.AVL_BURST_LENGTH (AVL_BURST_LENGTH)
Expand All @@ -138,7 +148,7 @@ module avl_dacfifo #(
.avl_last_address (avl_last_address_s),
.avl_last_burstcount (avl_last_burstcount_s),
.avl_clk (avl_clk),
.avl_reset (avl_reset),
.avl_reset (avl_reset_s),
.avl_address (avl_wr_address_s),
.avl_burstcount (avl_wr_burstcount_s),
.avl_byteenable (avl_wr_byteenable_s),
Expand All @@ -151,6 +161,7 @@ module avl_dacfifo #(
avl_dacfifo_rd #(
.AVL_DATA_WIDTH(AVL_DATA_WIDTH),
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
.AVL_ADDRESS_WIDTH (AVL_ADDRESS_WIDTH),
.AVL_DDR_BASE_ADDRESS(AVL_BASE_ADDRESS),
.AVL_DDR_ADDRESS_LIMIT(AVL_ADDRESS_LIMIT),
.DAC_MEM_ADDRESS_WIDTH(DAC_MEM_ADDRESS_WIDTH),
Expand All @@ -163,7 +174,7 @@ module avl_dacfifo #(
.dac_xfer_req(dac_xfer_fifo_out_s),
.dac_dunf(dac_dunf_fifo_s),
.avl_clk(avl_clk),
.avl_reset(avl_reset),
.avl_reset(avl_reset_s),
.avl_address(avl_rd_address_s),
.avl_burstcount(avl_rd_burstcount_s),
.avl_byteenable(avl_rd_byteenable_s),
Expand All @@ -182,7 +193,7 @@ module avl_dacfifo #(
assign avl_xfer_wren_s = ~avl_xfer_in_s;

always @(posedge avl_clk) begin
if (avl_reset == 1'b1) begin
if (avl_reset_s == 1'b1) begin
avl_address <= 0;
avl_burstcount <= 0;
avl_byteenable <= 0;
Expand Down
22 changes: 11 additions & 11 deletions library/intel/avl_dacfifo/avl_dacfifo_hw.tcl
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2017-2023, 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand All @@ -22,6 +22,7 @@ ad_ip_files avl_dacfifo [list\
# parameters

ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
ad_ip_parameter ACTIVE_LOW_RESET INTEGER 0
ad_ip_parameter DAC_DATA_WIDTH INTEGER 64
ad_ip_parameter DAC_MEM_ADDRESS_WIDTH INTEGER 8
ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
Expand All @@ -30,7 +31,7 @@ ad_ip_parameter AVL_DATA_WIDTH INTEGER 512
ad_ip_parameter AVL_ADDRESS_WIDTH INTEGER 25
ad_ip_parameter AVL_BURST_LENGTH INTEGER 127
ad_ip_parameter AVL_BASE_ADDRESS INTEGER 0
ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x800000
ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x80000000

# interfaces

Expand Down Expand Up @@ -63,15 +64,15 @@ set_interface_property avl_reset associatedclock avl_clock
add_interface_port avl_reset avl_reset reset input 1

add_interface amm_ddr avalon master
add_interface_port amm_ddr avl_address address output 25
add_interface_port amm_ddr avl_burstcount burstcount output 7
add_interface_port amm_ddr avl_byteenable byteenable output 64
add_interface_port amm_ddr avl_read read output 1
add_interface_port amm_ddr avl_readdata readdata input 512
add_interface_port amm_ddr avl_address address output AVL_ADDRESS_WIDTH
add_interface_port amm_ddr avl_burstcount burstcount output 7
add_interface_port amm_ddr avl_byteenable byteenable output AVL_DATA_WIDTH/8
add_interface_port amm_ddr avl_read read output 1
add_interface_port amm_ddr avl_readdata readdata input AVL_DATA_WIDTH
add_interface_port amm_ddr avl_readdata_valid readdatavalid input 1
add_interface_port amm_ddr avl_ready waitrequest_n input 1
add_interface_port amm_ddr avl_write write output 1
add_interface_port amm_ddr avl_writedata writedata output 512
add_interface_port amm_ddr avl_ready waitrequest_n input 1
add_interface_port amm_ddr avl_write write output 1
add_interface_port amm_ddr avl_writedata writedata output AVL_DATA_WIDTH

set_interface_property amm_ddr associatedClock avl_clock
set_interface_property amm_ddr associatedReset avl_reset
Expand Down Expand Up @@ -140,4 +141,3 @@ proc p_avl_dacfifo_elab {} {
set_instance_parameter_value ad_mem_asym_bypass B_DATA_WIDTH $m_dac_data_width

}

7 changes: 4 additions & 3 deletions library/intel/avl_dacfifo/avl_dacfifo_rd.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -39,6 +39,7 @@ module avl_dacfifo_rd #(

parameter AVL_DATA_WIDTH = 512,
parameter DAC_DATA_WIDTH = 64,
parameter AVL_ADDRESS_WIDTH = 25,
parameter AVL_BURST_LENGTH = 127,
parameter AVL_DDR_BASE_ADDRESS = 0,
parameter AVL_DDR_ADDRESS_LIMIT = 33554432,
Expand All @@ -53,15 +54,15 @@ module avl_dacfifo_rd #(

input avl_clk,
input avl_reset,
output reg [24:0] avl_address,
output reg [(AVL_ADDRESS_WIDTH-1):0] avl_address,
output reg [ 6:0] avl_burstcount,
output [63:0] avl_byteenable,
input avl_waitrequest,
input avl_readdatavalid,
output reg avl_read,
input [AVL_DATA_WIDTH-1:0] avl_data,

input [24:0] avl_last_address,
input [(AVL_ADDRESS_WIDTH-1):0] avl_last_address,
input [ 6:0] avl_last_burstcount,
input [ 7:0] dma_last_beats,
input avl_xfer_req_in,
Expand Down
7 changes: 4 additions & 3 deletions library/intel/avl_dacfifo/avl_dacfifo_wr.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -39,6 +39,7 @@ module avl_dacfifo_wr #(

parameter AVL_DATA_WIDTH = 512,
parameter DMA_DATA_WIDTH = 64,
parameter AVL_ADDRESS_WIDTH = 25,
parameter AVL_BURST_LENGTH = 128,
parameter AVL_DDR_BASE_ADDRESS = 0,
parameter AVL_DDR_ADDRESS_LIMIT = 33554432,
Expand All @@ -56,14 +57,14 @@ module avl_dacfifo_wr #(

input avl_clk,
input avl_reset,
output reg [24:0] avl_address,
output reg [(AVL_ADDRESS_WIDTH-1):0] avl_address,
output reg [ 6:0] avl_burstcount,
output [63:0] avl_byteenable,
input avl_waitrequest,
output reg avl_write,
output reg [AVL_DATA_WIDTH-1:0] avl_data,

output reg [24:0] avl_last_address,
output reg [(AVL_ADDRESS_WIDTH-1):0] avl_last_address,
output reg [ 6:0] avl_last_burstcount,
output reg avl_xfer_req_out,
input avl_xfer_req_in
Expand Down
3 changes: 2 additions & 1 deletion library/intel/axi_adxcvr/axi_adxcvr_hw.tcl
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2016-2024 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2016-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand All @@ -20,6 +20,7 @@ set_module_property VALIDATION_CALLBACK info_param_validate
# files

ad_ip_files axi_adxcvr [list \
$ad_hdl_dir/library/util_cdc/sync_bits.v \
$ad_hdl_dir/library/common/up_axi.v \
axi_adxcvr_up.v \
axi_adxcvr.v \
Expand Down
99 changes: 65 additions & 34 deletions library/intel/axi_adxcvr/axi_adxcvr_up.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -81,17 +81,20 @@ module axi_adxcvr_up #(
reg up_wreq_d = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg [ 3:0] up_rst_cnt = 'd8;
reg up_status_int = 'd0;
reg up_rreq_d = 'd0;
reg [31:0] up_rdata_d = 'd0;

// internal signals

wire up_ready_s;
wire up_all_ready_s;
wire [31:0] up_status_32_s;
wire [31:0] up_rparam_s;

wire up_pll_locked_s;
wire up_rx_lockedtodata_s;
wire up_ready_s;

// defaults

assign up_wack = up_wreq_d;
Expand Down Expand Up @@ -120,53 +123,81 @@ module axi_adxcvr_up #(
end
end

assign up_ready_s = & up_status_32_s[(NUM_OF_LANES-1):0];
generate if (FPGA_TECHNOLOGY == 105) begin
sync_bits #(
.NUM_OF_BITS (3),
.ASYNC_CLK (1)
) i_sync_input_ctrl (
.in_bits ({up_ready, up_pll_locked, up_rx_lockedtodata}),
.out_resetn (1'b1),
.out_clk (up_clk),
.out_bits({up_ready_s, up_pll_locked_s, up_rx_lockedtodata_s}));
end else begin
assign up_ready_s = up_ready;
assign up_pll_locked_s = up_pll_locked;
assign up_rx_lockedtodata_s = up_rx_lockedtodata;
end
endgenerate

assign up_all_ready_s = & up_status_32_s[(NUM_OF_LANES-1):0];
assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0;
assign up_status_32_s[NUM_OF_LANES] = FPGA_TECHNOLOGY == 105 ? TX_OR_RX_N ? up_pll_locked : up_rx_lockedtodata :
up_pll_locked;
assign up_status_32_s[(NUM_OF_LANES-1):0] = FPGA_TECHNOLOGY == 105 ? {NUM_OF_LANES{up_ready}} : up_ready;
assign up_status_32_s[NUM_OF_LANES] = FPGA_TECHNOLOGY == 105 ? TX_OR_RX_N ? up_pll_locked_s : up_rx_lockedtodata_s :
up_pll_locked_s;
assign up_status_32_s[(NUM_OF_LANES-1):0] = FPGA_TECHNOLOGY == 105 ? {NUM_OF_LANES{up_ready_s}} : up_ready_s;

always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rst_cnt <= 4'h8;
up_status_int <= 1'b0;
end else begin
if (up_resetn == 1'b0) begin
up_rst_cnt <= 4'h8;
end else if (up_rst_cnt[3] == 1'b1) begin
up_rst_cnt <= up_rst_cnt + 1'b1;
end
if (up_resetn == 1'b0) begin
up_status_int <= 1'b0;
end else if (up_ready_s == 1'b1) begin
up_status_int <= 1'b1;
generate if (FPGA_TECHNOLOGY == 105) begin
wire up_reset_ack_s;
reg up_rst_d;

sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (1)
) i_sync_reset_ack (
.in_bits (up_reset_ack),
.out_resetn (1'b1),
.out_clk (up_clk),
.out_bits(up_reset_ack_s));

always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rst_d <= 1'b1;
end else if (up_resetn == 1'b0) begin
up_rst_d <= 1'b1;
end else if (up_reset_ack_s) begin
up_rst_d <= 1'b0;
end
end
end

generate if (FPGA_TECHNOLOGY == 105) begin
reg up_reset_ack_d = 'd0;
assign up_rst = up_rst_d;
end else begin
reg [3:0] up_rst_cnt = 'd8;

always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_reset_ack_d <= 1'b0;
up_rst_cnt <= 4'h8;
end else begin
if (up_resetn == 1'b0) begin
up_reset_ack_d <= 1'b0;
end else begin
if (up_reset_ack_d == 1'b0) begin
up_reset_ack_d <= up_reset_ack;
end
up_rst_cnt <= 4'h8;
end else if (up_rst_cnt[3] == 1'b1) begin
up_rst_cnt <= up_rst_cnt + 1'b1;
end
end
end

assign up_rst = ~up_reset_ack_d;
end else begin
assign up_rst = up_rst_cnt[3];
end
endgenerate

always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_int <= 1'b0;
end else begin
if (up_resetn == 1'b0) begin
up_status_int <= 1'b0;
end else if (up_all_ready_s) begin
up_status_int <= 1'b1;
end
end
end

// Specific to Intel

assign up_rparam_s[31:28] = 8'd0;
Expand Down
8 changes: 5 additions & 3 deletions library/util_pack/util_cpack2/util_cpack2.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -38,7 +38,8 @@
module util_cpack2 #(
parameter NUM_OF_CHANNELS = 4,
parameter SAMPLES_PER_CHANNEL = 1,
parameter SAMPLE_DATA_WIDTH = 16
parameter SAMPLE_DATA_WIDTH = 16,
parameter PARALLEL_OR_SERIAL_N = 0
) (
input clk,
input reset,
Expand Down Expand Up @@ -282,7 +283,8 @@ module util_cpack2 #(
util_cpack2_impl #(
.NUM_OF_CHANNELS (REAL_NUM_OF_CHANNELS),
.SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH),
.SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL)
.SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL),
.PARALLEL_OR_SERIAL_N (PARALLEL_OR_SERIAL_N)
) i_cpack (
.clk (clk),
.reset (reset),
Expand Down
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