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AD9081/vcu118: Fix timing #1718

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Merged
merged 1 commit into from
Jun 13, 2025
Merged

AD9081/vcu118: Fix timing #1718

merged 1 commit into from
Jun 13, 2025

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AndrDragomir
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PR Description

Changed the implementation strategy.
The project builds successfully on my machine.
Waiting for automatic builds.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@AndrDragomir
ad9081/vcu118: Fix timing
bdf855a 
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
@AndrDragomir AndrDragomir merged commit 1303a28 into main Jun 13, 2025
3 of 5 checks passed
@AndrDragomir AndrDragomir deleted the ad9081_vcu118_fix_timing branch June 13, 2025 11:38
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@IuliaCMoldovan IuliaCMoldovan IuliaCMoldovan approved these changes

@FilipG24 FilipG24 Awaiting requested review from FilipG24 FilipG24 is a code owner

@LBFFilho LBFFilho Awaiting requested review from LBFFilho LBFFilho is a code owner

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@AndrDragomir @IuliaCMoldovan