Add support for EVAL-AD4880 #1752
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The IO_DELAY_GROUP parameter was exposed and adc_enable/adc_rst was exported. Signed-off-by: PopPaul2021 <paul.pop@analog.com>
PopPaul2021
requested review from
IuliaCMoldovan,
gastmaier,
StancaPop,
LBFFilho,
acostina,
AndreiGrozav and
sarpadi
as code owners
Signed-off-by: PopPaul2021 <paul.pop@analog.com>
Signed-off-by: PopPaul2021 <paul.pop@analog.com>
| wire adca_filter_data_ready_n; | ||
| wire adcb_filter_data_ready_n; | ||
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| wire fpga_100_clk; |
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fpga_{100,ref}_clk and ad9508_adf4350_csn are not used. can be removed
| @@ -0,0 +1,284 @@ | |||
| .. _ad488x_fmc_evb: | |||
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| AD408X-FMC-EVB HDL project | |||
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Correct title: AD488X-FMC-EVB
| Overview | ||
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| The :adi:`EVAL-AD4880-FMC <EVAL-AD4880-FMC>` is designed to demonstrate the |
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These mentions:
- :adi:
EVAL-AD4880-FMC <EVAL-AD4880-FMC> - :adi:
AD4880 <AD4880>
Won't work, as they don't redirect the user to the mentioned products' webpage. (AD4880 & EVAL-AD4880 pages don't exist, will they be published in the future?)
| The :adi:`EVAL-AD4880-FMC <EVAL-AD4880-FMC>` evaluation board was designed for | ||
| use with the Digilent ZedBoard via the field programmable gate array(FPGA) | ||
| mezzanine card (FMC) connector. |
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This paragraph can be removed, same thing mentioned in "Supported Carriers" section (also can be removed from AD408x page).
| - Carrier | ||
| - FMC slot | ||
| * - :adi:`EVAL-AD4880-FMC <EVAL-AD4880-FMC>` | ||
| - :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>` |
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- `ZedBoard https://digilent.com/shop/zedboard-zynq-7000-arm-fpga-soc-development-board`__
(same as it's declared in AD408x documentation)
| ================ === ========== =========== | ||
| Instance name HDL Linux Zynq Actual Zynq | ||
| ================ === ========== =========== | ||
| axi_ad4880_dma 13 57 89 |
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From bd, shouldn't this one be added too?
ad_cpu_interrupt ps-10 mb-9 ad4080_b_spi/ip2intc_irpt
| @@ -31,6 +31,8 @@ Contents | |||
| AD4630-FMC <ad4630_fmc/index> | |||
| AD469X-EVB <ad469x_evb/index> | |||
| AD485X-FMCZ <ad485x_fmcz/index> | |||
| AD488X-FMC-EVB <ad488x_fmc_evb/index> | |||
| AD57XX-ARDZ <ad57xx_ardz/index> | |||
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This one is duplicated, appears 2 times in the same list. (AD57XX)
| | Part name | Description | | ||
| |-----------------------------------------------|--------------------------------------------------------------------| | ||
| | [AD4880](https://www.analog.com/ad4880) | Dual Channel 20-Bit, 40 MSPS, SAR ADC | |
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| | Part name | Description | | |
| |-----------------------------------------------|--------------------------------------------------------------------| | |
| | [AD4880](https://www.analog.com/ad4880) | Dual Channel 20-Bit, 40 MSPS, SAR ADC | | |
| | Part name | Description | | |
| |-----------------------------------------|---------------------------------------| | |
| | [AD4880](https://www.analog.com/ad4880) | Dual Channel 20-Bit, 40 MSPS, SAR ADC | |
The same table should be corrected the same in AD4080x/Zed.
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| | Part name | Description | | ||
| |-----------------------------------------------|--------------------------------------------------------------------| | ||
| | [AD4880](https://www.analog.com/ad4880) | Dual Channel 20-Bit, 40 MSPS, SAR ADC | |
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This links to the products (chip and eval. board) won't work as the pages don't exist yet.
| make | ||
| ``` | ||
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| Corresponding device tree: [zynq-zed-adv7511-ad4880.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4880.dts) |
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This link doesn't work.
| create_bd_port -dir I fpga_a_ref_clk | ||
| create_bd_port -dir I fpga_b_ref_clk | ||
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| create_bd_port -dir O ad4080_b_spi_csn_o |
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I know that this project was ported from AD408x and both are very similar, but shouldn't we name the instances properly just in case?
PR Description
Adding the EVAL-AD4880 reference design and documentation.
PR Type
PR Checklist