Merge branch 'update/01-HFSS3DLayout' into update/01-Modeling-Setup

Author: Devin-Crawford

examples/01-HFSS3DLayout/01_power_integrity.py

@@ -1,61 +1,76 @@
 # # HFSS 3D Layout: Power Integrity Analysis
+
 # This example shows how to use the electronics database (EDB) for power integrity analysis. The 
 # EDB will be loaded into HFSS 3D Layout for analysis and post-processing.
+#
 # - Set up EDB
+#
 #     - Assign S-parameter model to components
 #     - Create pin groups
 #     - Create ports
 #     - Create SIwave SYZ anaylsis
 #     - Create cutout
+#
 # - Import EDB into HFSS 3D Layout
+#
 #     - Analyze
 #     - Plot $Z_{11}$
 
-# ## Preparation
-# Import the required packages
+# ## Perform required imports
+#
+# Perform required imports.
 
-# +
 import os
 import json
 import tempfile
 import time
 from pyaedt import Edb
 from pyaedt import Hfss3dLayout
 from pyaedt.downloads import download_file
-# -
 
-# Set constant values
+# ## Define constants
+#
+# Define constant values used in this example 
 
 AEDT_VERSION = "2024.1"
 NG_MODE = True
 
+# ## Create temporary directory and download files
+#
+# Create a temporary directory where we store downloaded data or
+# dumped data.
+
+temp_folder = tempfile.TemporaryDirectory(suffix=".ansys")
 
 # Download the example PCB data.
 
-temp_folder = tempfile.TemporaryDirectory(suffix=".ansys")
 aedb = download_file(
     source="edb/ANSYS-HSD_V1.aedb", destination=temp_folder.name
 )
 download_file(
     source="touchstone", name="GRM32_DC0V_25degC_series.s2p", destination=temp_folder.name
 )
 
-# ## Create a configuration file
-# In this example, we are going to use a configuration file to set up the layout for analysis.
-# ### Initialize a dictionary
+# ## Create a configuration file to set up the layout for analysis
+#
 # Create an empty dictionary to host all configurations.
 
 cfg = dict()
 
-# In this example, we are going to assign S-parameter models to capacitors. 
-# The first step is to use the "general" key to specify where the S-parameter files can be found.
+# > **Note:** In the following, we are going to assign S-parameter
+# > models to capacitors. 
+
+# ### Define the S-parameter files
+#
+# Specify the location of the S-parameter files.
 
 cfg["general"] = {
     "s_parameter_library": os.path.join(temp_folder.name, "touchstone")
 }
 
-# ## Assign model to capactitors. 
-# In this example, the model "GRM32_DC0V_25degC_series.s2p" is assigned to capacitors C3 and C4, which share the same component part number.
+# ### Assign model to capactitors
+#
+# Assign the model "GRM32_DC0V_25degC_series.s2p" to capacitors C3 and C4, which share the same component part number.
 # When "apply_to_all" is ``True``, all components having the part number "CAPC3216X180X20ML20" will be assigned the S-parameter model. 
 
 cfg["s_parameters"] = [
@@ -72,9 +87,11 @@
     }
 ]
 
-# ## Create pin groups.
-# In this example, the listed pins on component U2 are combined into two pin groups. 
-# Pins can be grouped explicitly by the pin name or pin groups can be assigned by net name using the "net" key as shown here:
+# ### Define pin groups
+#
+# Combine the listed pins on component U1 into pin groups:
+# - the first group is defined explicitly by the pins name;
+# - the second group is assigned by net name using the "net" key.
 
 cfg["pin_groups"] = [
     {
@@ -89,8 +106,9 @@
     }
 ]
 
-# ## Create ports
-# Create a circuit port between the two pin groups just created.
+# ### Create ports
+#
+# Create a circuit port between the two pin groups previously created.
 
 cfg["ports"] = [
     {
@@ -106,8 +124,12 @@
     }
 ]
 
-# ## Create SIwave SYZ analysis setup
-# Both SIwave and HFSS can be used to run an analysis in the 3D Layout user interface.
+# ### Create SIwave SYZ analysis setup
+#
+# Create SIwave SYZ analysis setup.
+#
+# > **Note:** Both SIwave and HFSS can be used to run an analysis in the
+# > 3D Layout user interface.
 
 cfg["setups"] = [
     {
@@ -131,8 +153,9 @@
     }
 ]
 
-# ## Cutout
-# The following assignments will define the region of the PCB to be cut out for analysis.
+# ### Cutout
+#
+# Define the the region of the PCB to cutout for analysis.
 
 cfg["operations"] = {
     "cutout": {
@@ -162,17 +185,17 @@
     }
 }
 
-# ## Save the configuration
+# ### Save the configuration
 #
-# The configuration file can be saved in JSON format and applied to layout data using the EDB.
+# Save the configuration file in JSON format.
 
 pi_json = os.path.join(temp_folder.name, "pi.json")
 with open(pi_json, "w") as f:
     json.dump(cfg, f, indent=4, ensure_ascii=False)
 
 # ## Load configuration into EDB
-
-# Load configuration from JSON
+#
+# Load configuration from the JSON file.
 
 edbapp = Edb(aedb, edbversion=AEDT_VERSION)
 edbapp.configuration.load(config_file=pi_json)
@@ -186,7 +209,7 @@
 
 # ## Analyze in HFSS 3D Layout
 
-# ### Load edb into HFSS 3D Layout.
+# ### Load EDB into HFSS 3D Layout
 
 h3d = Hfss3dLayout(
     aedb,
@@ -204,17 +227,17 @@
 solutions = h3d.post.get_solution_data(expressions='Z(port1,port1)')
 solutions.plot()
 
-# ## Shut Down Electronics Desktop
-
-h3d.close_desktop()
+# ## Save project and close AEDT
+#
+# Save the project, release AEDT and remove both the project and temporary directory.
 
-# All project files are saved in the folder ``temp_file.dir``. If you've run this example as a Jupyter notbook you 
-# can retrieve those project files. The following cell removes all temporary files, including the project folder.
+# > **Note:** All project files are saved in the folder ``temp_file.dir``.
+# > If you've run this example as a Jupyter notebook you  can retrieve those project files.
+# > The following cell removes all temporary files, including the project folder.
 
-# ## Cleanup
-#
-# All project files are saved in the folder ``temp_file.dir``. If you've run this example as a Jupyter notbook you 
-# can retrieve those project files. The following cell removes all temporary files, including the project folder.
+# +
+h3d.save_project()
+h3d.release_desktop()
 
 time.sleep(3)
 temp_folder.cleanup()

examples/01-HFSS3DLayout/02_dc_ir_analysis.py

@@ -1,14 +1,18 @@
 # # HFSS 3D Layout: DC IR Analysis
 # This example shows how to configure EDB for DC IR analysis, and load EDB into the 3D Layout UI for analysis and
 # post-processing.
+#
 # - Set up EDB
+#
 #     - Edit via padstack
 #     - Assign SPICE model to components
 #     - Create pin groups
 #     - Create voltage and current sources
 #     - Create SIwave DC anaylsis
 #     - Create cutout
+#
 # - Import EDB into HFSS 3D Layout
+#
 #     - Analyze
 #     - Get DC IR analysis results
 

examples/01-HFSS3DLayout/04_pre_layout_sma_connector_on_pcb.py

@@ -1,7 +1,9 @@
 # # HFSS 3D Layout: Pre-layout Signal Integrity
 # This example shows how to create a parameterized layout design, and load the layout into HFSS 3D Layout for analysis and
 # post-processing.
+#
 # - Create EDB
+#
 #     - Add material
 #     - Create stackup
 #     - Create a parameterized via padstack definition
@@ -10,7 +12,9 @@
 #     - Create signal vias and traces
 #     - Create ground stitching vias
 #     - Create HFSS analysis setup and frequency sweep
+#
 # - Import EDB into HFSS 3D Layout
+#
 #     - Place SMA connector
 #     - Analysis
 #     - Plot return loss