[patch-axel-63] RISC-V A730 #160
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This is most likely an artifact from the change of the IPC buffer handling before v11.0.0, where a thread-local register (tp on RISC-V) was reserved by the kernel for storing the pointer to the thread's IPC buffer. Architectures such as aarch64 would set the register inside Arch_switchToThread() and then not touch the register in restore_user_context(). When the RISC-V port was up-streamed, it didn't restore the register with the other registers, but also didn't restore it in Arch_switchToThread() and so ended up restoring it right at the end of the restore process. Co-authored-by: Kent McLeod <kent@kry10.com> Signed-off-by: Axel Heider <axel.heider@codasip.com>
Signed-off-by: Axel Heider <axelheider@gmx.de>
Signed-off-by: Axel Heider <axelheider@gmx.de>
Signed-off-by: Axel Heider <axelheider@gmx.de>
Signed-off-by: Axel Heider <axelheider@gmx.de>
Signed-off-by: Axel Heider <axel.heider@codasip.com>
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