[patch-axel-28] cleanup risc-v

.cmake-format.yaml

@@ -24,8 +24,10 @@ additional_commands:
       DEFAULT: '*'
       DEPENDS: '*'
   cppfile:
+    pargs:
+      nargs: '3'
     kwargs:
-      EXACT_NAME: '*'
+      EXACT_NAME: '?'
       EXTRA_DEPS: '*'
       EXTRA_FLAGS: '*'
   gen_invocation_header:
@@ -42,16 +44,16 @@ additional_commands:
       PREFIX: '*'
   declare_default_headers:
     kwargs:
-        TIMER_FREQUENCY: '*'
-        MAX_IRQ: '*'
-        NUM_PPI: '*'
-        INTERRUPT_CONTROLLER: '*'
-        TIMER: '*'
-        KERNEL_WCET: '*'
-        CLK_MAGIC: '*'
-        CLK_SHIFT: '*'
-        TIMER_PRECISION: '*'
-        TIMER_OVERHEAD_TICKS: '*'
-        SMMU: '*'
-        MAX_SID: '*'
-        MAX_CB: '*'
+        TIMER_FREQUENCY: '1'
+        MAX_IRQ: '1'
+        NUM_PPI: '1'
+        INTERRUPT_CONTROLLER: '1'
+        TIMER: '1'
+        KERNEL_WCET: '1'
+        CLK_MAGIC: '1'
+        CLK_SHIFT: '1'
+        TIMER_PRECISION: '1'
+        TIMER_OVERHEAD_TICKS: '1'
+        SMMU: '1'
+        MAX_SID: '1'
+        MAX_CB: '1'

include/arch/arm/arch/32/mode/object/structures.h

@@ -42,7 +42,6 @@ typedef pde_t vspace_root_t;
 
 #define PGDE_SIZE_BITS seL4_PGDEntryBits
 #define PDE_SIZE_BITS  seL4_PageDirEntryBits
-#define PTE_SIZE_BITS  seL4_PageTableEntryBits
 #define PGD_INDEX_BITS seL4_PGDIndexBits
 #define PD_INDEX_BITS seL4_PageDirIndexBits
 #define PT_INDEX_BITS seL4_PageTableIndexBits

include/arch/arm/arch/64/mode/object/structures.h

@@ -30,7 +30,6 @@ enum vm_rights {
 };
 typedef word_t vm_rights_t;
 
-#define PTE_SIZE_BITS       seL4_PageTableEntryBits
 #define PT_INDEX_BITS       seL4_PageTableIndexBits
 
 #define PT_INDEX_OFFSET     (seL4_PageBits)

include/arch/riscv/arch/32/mode/machine.h

@@ -8,60 +8,85 @@
 
 #include <util.h>
 #include <arch/model/smp.h>
+#include <arch/machine/registerset.h>
 #include <stdint.h>
 #include <plat/machine/devices_gen.h>
 
+/* Read a consistent 64-bit counter value from two 32-bit registers. The value
+ * from the low register is used only if there was no roll over, otherwise it is
+ * simply taken as 0. This is an acceptable optimization if the value must have
+ * been 0 at some point anyway and certain jitter is acceptable. For high
+ * frequency counters the preference usually not on getting an exact value, but
+ * a value close to the point in time where the read function was called. For a
+ * low frequency counter, the low value is likely 0 anyway when a roll over
+ * happens.
+ */
+#define declare_helper_riscv_read_csr64cntr(_name_, _id_hi_, _id_lo_) \
+    static inline uint64_t riscv_read_csr64cntr_##_name_(void) \
+    { \
+        register word_t nH_prev, nH, nL; \
+        RISCV_CSR_READ(_id_hi_, nH_prev); \
+        RISCV_CSR_READ(_id_lo_, nL); \
+        RISCV_CSR_READ(_id_hi_, nH); \
+        if (nH_prev != nH) { RISCV_CSR_READ(_id_lo_, nL); } \
+        return (((uint64_t)nH) << 32) | nL; \
+    }
+
+/* create riscv_read_csr64cntr_time() */
+declare_helper_riscv_read_csr64cntr(time, RISCV_CSR_TIMEH, RISCV_CSR_TIME)
+
+/* create riscv_read_csr64cntr_cycle() */
+declare_helper_riscv_read_csr64cntr(cycle, RISCV_CSR_CYCLEH, RISCV_CSR_CYCLE)
+
+/* create get_riscv_csr64cntr_instret() */
+declare_helper_riscv_read_csr64cntr(instret, RISCV_CSR_INSTRETH, RISCV_CSR_INSTRET)
+
+
 #ifdef CONFIG_RISCV_USE_CLINT_MTIME
 /*
  * Currently all RISC-V 32-bit platforms supported have the mtime register
  * mapped at the same offset of the base address of the CLINT.
  */
 #define CLINT_MTIME_OFFSET_LO 0xbff8
 #define CLINT_MTIME_OFFSET_HI 0xbffc
-#endif
 
-static inline uint64_t riscv_read_time(void)
+static inline uint32_t riscv_read_clint_u32(word_t offset)
 {
-    word_t nH1, nL, nH2;
+    return *(volatile uint32_t *)(CLINT_PPTR + offset);
+}
 
-#ifdef CONFIG_RISCV_USE_CLINT_MTIME
-    nH1 = *(volatile uint32_t *)(CLINT_PPTR + CLINT_MTIME_OFFSET_HI);
-    nL = *(volatile uint32_t *)(CLINT_PPTR + CLINT_MTIME_OFFSET_LO);
-    nH2 = *(volatile uint32_t *)(CLINT_PPTR + CLINT_MTIME_OFFSET_HI);
-    if (nH1 != nH2) {
-        /* Ensure that the time is correct if there is a rollover in the
-         * high bits between reading the low and high bits. */
-        nL = *(volatile uint32_t *)(CLINT_PPTR + CLINT_MTIME_OFFSET_LO);
+static inline uint64_t riscv_read_clint_mtime(void)
+{
+    /*
+     * Ensure that the time is correct if there is a rollover in the
+     * high bits between reading the low and high bits.
+     */
+    uint32_t nH_prev = riscv_read_clint_u32(CLINT_MTIME_OFFSET_HI);
+    uint32_t nL = riscv_read_clint_u32(CLINT_MTIME_OFFSET_LO);
+    uint32_t nH = riscv_read_clint_u32(CLINT_MTIME_OFFSET_HI);
+    if (nH_prev != nH) {
+        nL = riscv_read_clint_u32(CLINT_MTIME_OFFSET_LO);
     }
+    return (((uint64_t)nH) << 32) | nL;
+}
+
+#endif /* CONFIG_RISCV_USE_CLINT_MTIME */
+
+static inline uint64_t riscv_read_time(void)
+{
+#ifdef CONFIG_RISCV_USE_CLINT_MTIME
+    return riscv_read_clint_mtime();
 #else
-    asm volatile(
-        "rdtimeh %0\n"
-        "rdtime  %1\n"
-        "rdtimeh %2\n"
-        : "=r"(nH1), "=r"(nL), "=r"(nH2));
-    if (nH1 != nH2) {
-        /* Ensure that the time is correct if there is a rollover in the
-         * high bits between reading the low and high bits. */
-        asm volatile("rdtime  %0\n" : "=r"(nL));
-    }
+    return riscv_read_csr64cntr_time();
 #endif
-
-    return (((uint64_t)nH2) << 32) | nL;
 }
 
-
 static inline uint64_t riscv_read_cycle(void)
 {
-    word_t nH1, nL, nH2;
-    asm volatile(
-        "rdcycleh %0\n"
-        "rdcycle  %1\n"
-        "rdcycleh %2\n"
-        : "=r"(nH1), "=r"(nL), "=r"(nH2));
-    if (nH1 != nH2) {
-        /* Ensure that the cycles are correct if there is a rollover in the
-         * high bits between reading the low and high bits. */
-        asm volatile("rdcycle  %0\n" : "=r"(nL));
-    }
-    return (((uint64_t)nH2) << 32) | nL;
+    return riscv_read_csr64cntr_cycle();
+}
+
+static inline uint64_t riscv_read_instret(void)
+{
+    return riscv_read_csr64cntr_instret();
 }

include/arch/riscv/arch/64/mode/machine.h

@@ -8,6 +8,7 @@
 
 #include <util.h>
 #include <arch/model/smp.h>
+#include <arch/machine/registerset.h>
 #include <stdint.h>
 #include <plat/machine/devices_gen.h>
 
@@ -17,22 +18,34 @@
  * mapped at the same offset of the base address of the CLINT.
  */
 #define CLINT_MTIME_OFFSET 0xbff8
-#endif
+
+static inline uint64_t riscv_read_clint_u64(word_t offset)
+{
+    return *(volatile uint64_t *)(CLINT_PPTR + offset);
+}
+
+static inline uint64_t riscv_read_clint_mtime(void)
+{
+    return riscv_read_clint_u64(CLINT_MTIME_OFFSET);
+}
+
+#endif /* CONFIG_RISCV_USE_CLINT_MTIME */
 
 static inline uint64_t riscv_read_time(void)
 {
-    word_t n;
 #ifdef CONFIG_RISCV_USE_CLINT_MTIME
-    n = *(volatile word_t *)(CLINT_PPTR + CLINT_MTIME_OFFSET);
+    return riscv_read_clint_mtime();
 #else
-    asm volatile("rdtime %0" : "=r"(n));
+    return riscv_read_csr_time();
 #endif
-    return n;
 }
 
 static inline uint64_t riscv_read_cycle(void)
 {
-    word_t n;
-    asm volatile("rdcycle %0" : "=r"(n));
-    return n;
+    return riscv_read_csr_cycle();
+}
+
+static inline uint64_t riscv_read_instret(void)
+{
+    return riscv_read_csr_instret();
 }

include/arch/riscv/arch/machine/hardware.h

@@ -45,8 +45,8 @@
  * configured RISC-V system with CONFIG_PT_LEVEL (which can be 2 on Sv32,
  * 3 on Sv39, or 4 on Sv48)
  */
-#define RISCV_GET_PT_INDEX(addr, n)  (((addr) >> (((PT_INDEX_BITS) * (((CONFIG_PT_LEVELS) - 1) - (n))) + seL4_PageBits)) & MASK(PT_INDEX_BITS))
-#define RISCV_GET_LVL_PGSIZE_BITS(n) (((PT_INDEX_BITS) * (((CONFIG_PT_LEVELS) - 1) - (n))) + seL4_PageBits)
+#define RISCV_GET_PT_INDEX(addr, n)  (((addr) >> (((seL4_PageTableIndexBits) * (((CONFIG_PT_LEVELS) - 1) - (n))) + seL4_PageBits)) & MASK(seL4_PageTableIndexBits))
+#define RISCV_GET_LVL_PGSIZE_BITS(n) (((seL4_PageTableIndexBits) * (((CONFIG_PT_LEVELS) - 1) - (n))) + seL4_PageBits)
 #define RISCV_GET_LVL_PGSIZE(n)      BIT(RISCV_GET_LVL_PGSIZE_BITS((n)))
 /*
  * These values are defined in RISC-V priv-1.10 manual, they represent the

include/arch/riscv/arch/machine/registerset.h

@@ -184,5 +184,46 @@ static inline word_t CONST sanitiseRegister(register_t reg, word_t v, bool_t arc
     [seL4_TimeoutReply_TP] = TP, \
 }
 
-#endif /* __ASSEMBLER__ */
+#define RISCV_CSR_CYCLE     0xc00
+#define RISCV_CSR_TIME      0xc01
+#define RISCV_CSR_INSTRET   0xc02
+#ifdef CONFIG_ARCH_RISCV32
+#define RISCV_CSR_CYCLEH    0xc80
+#define RISCV_CSR_TIMEH     0xc81
+#define RISCV_CSR_INSTRETH  0xc82
+#endif /* CONFIG_ARCH_RISCV32 */
+
+
+#define RISCV_CSR_READ(_id_, _var_) \
+    asm volatile("csrr %0, " #_id_ : "=r" (_var_) : : "memory")
+
+#define declare_helper_riscv_read_csr(_name_, _id_) \
+    static inline word_t riscv_read_csr_##_name_(void) \
+    { \
+        register word_t val; \
+        RISCV_CSR_READ(_id_, val); \
+        return val; \
+    }
+
+/* create riscv_read_csr_cycle() */
+declare_helper_riscv_read_csr(cycle, RISCV_CSR_CYCLE)
+#ifdef CONFIG_ARCH_RISCV32
+/* create riscv_read_csr_cycleh() */
+declare_helper_riscv_read_csr(cycleh, RISCV_CSR_CYCLEH)
+#endif
+
+/* create riscv_read_csr_time() */
+declare_helper_riscv_read_csr(time, RISCV_CSR_TIME)
+#ifdef CONFIG_ARCH_RISCV32
+/* create riscv_read_csr_timeh() */
+declare_helper_riscv_read_csr(timeh, RISCV_CSR_TIMEH)
+#endif
 
+/* create riscv_read_csr_instret() */
+declare_helper_riscv_read_csr(instret, RISCV_CSR_INSTRET)
+#ifdef CONFIG_ARCH_RISCV32
+/* create riscv_read_csr_instreth() */
+declare_helper_riscv_read_csr(instreth, RISCV_CSR_INSTRETH)
+#endif
+
+#endif /* __ASSEMBLER__ */

include/arch/riscv/arch/model/statedata.h

@@ -25,14 +25,14 @@ NODE_STATE_END(archNodeState);
 extern asid_pool_t *riscvKSASIDTable[BIT(asidHighBits)];
 
 /* Kernel Page Tables */
-extern pte_t kernel_root_pageTable[BIT(PT_INDEX_BITS)] VISIBLE;
+extern pte_t kernel_root_pageTable[BIT(seL4_PageTableIndexBits)] VISIBLE;
 
 /* We need to introduce a level2 pagetable in order to map OpenSBI to a separate
  * page entry to avoid PMP exception. */
 #if __riscv_xlen != 32
-extern pte_t kernel_image_level2_pt[BIT(PT_INDEX_BITS)];
-extern pte_t kernel_image_level2_dev_pt[BIT(PT_INDEX_BITS)];
+extern pte_t kernel_image_level2_pt[BIT(seL4_PageTableIndexBits)];
+extern pte_t kernel_image_level2_dev_pt[BIT(seL4_PageTableIndexBits)];
 #elif defined(CONFIG_KERNEL_LOG_BUFFER)
-extern pte_t kernel_image_level2_log_buffer_pt[BIT(PT_INDEX_BITS)];
+extern pte_t kernel_image_level2_log_buffer_pt[BIT(seL4_PageTableIndexBits)];
 #endif
 

include/arch/riscv/arch/object/structures.h

@@ -54,16 +54,9 @@ typedef pte_t pde_t;
 #define PTE_PTR(r) ((pte_t *)(r))
 #define PTE_REF(p) ((word_t)(p))
 
-#define PT_SIZE_BITS 12
 #define PT_PTR(r) ((pte_t *)(r))
 #define PT_REF(p) ((word_t)(p))
 
-#define PTE_SIZE_BITS   seL4_PageTableEntryBits
-#define PT_INDEX_BITS   seL4_PageTableIndexBits
-
-#define WORD_BITS   (8 * sizeof(word_t))
-#define WORD_PTR(r) ((word_t *)(r))
-
 static inline bool_t CONST cap_get_archCapIsPhysical(cap_t cap)
 {
     cap_tag_t ctag;
@@ -98,10 +91,11 @@ static inline word_t CONST cap_get_archCapSizeBits(cap_t cap)
 
     switch (ctag) {
     case cap_frame_cap:
+        /* ToDo: could we simply use seL4_PageBits here? */
         return pageBitsForSize(cap_frame_cap_get_capFSize(cap));
 
     case cap_page_table_cap:
-        return PT_SIZE_BITS;
+        return seL4_PageTableBits;
 
     case cap_asid_control_cap:
         return 0;

include/arch/riscv/arch/sbi.h

@@ -1,7 +1,8 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
 
 /* Copyright (c) 2010-2017, The Regents of the University of California
- * (Regents).  All Rights Reserved.
+ *                          (Regents).  All Rights Reserved.
+ * Copyright 2021, HENSOLDT Cyber
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,6 +34,20 @@
 #pragma once
 
 #include <config.h>
+#if defined(CONFIG_RISCV_SBI_NONE)
+/* nothing here if there is no SBI */
+#else
+
+/* We check for specific SBI implementation here, but actually this is checking
+ * for a specific SBI interface. It does not matter what SBI implementation is
+ * running on a platform implementing this interface.
+ */
+#if !defined(CONFIG_RISCV_SBI_OPENSBI) \
+    && !defined(CONFIG_RISCV_SBI_BBL) \
+    && !defined(CONFIG_RISCV_SBI_ROM)
+#error Unknown SBI implementation
+#endif
+
 #include <stdint.h>
 
 /* See https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc for
@@ -155,3 +170,4 @@ static inline void sbi_remote_sfence_vma_asid(word_t hart_mask,
 }
 
 #endif /* ENABLE_SMP_SUPPORT */
+#endif /* not CONFIG_RISCV_SBI_NONE */

include/arch/riscv/arch/smp/ipi.h

@@ -9,6 +9,7 @@
 #include <config.h>
 
 #ifdef ENABLE_SMP_SUPPORT
+
 typedef enum {
     IpiRemoteCall_Stall,
     IpiRemoteCall_switchFpuOwner,
@@ -18,5 +19,5 @@ typedef enum {
 void ipi_send_target(irq_t irq, word_t cpuTargetList);
 irq_t ipi_get_irq(void);
 void  ipi_clear_irq(irq_t irq);
-#endif
 
+#endif /* ENABLE_SMP_SUPPORT */