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tlyudragonmux
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target/adiv5_swd: add idle SWD cycles
Add missing idle cycles after SWD read transactions. ADIv5 (ARM IHI0031G) §B4.1.1 requires at least 8 idle cycles after any SWD transaction (not just write transactions) before stopping the clock. This does add some delays to read transactions where there were previously none. A future change could conditionally disable the idle cycles for both read and write transactions if it is known that a new transaction will immediately follow.
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src/target/adiv5_swd.c

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,7 @@ static uint32_t firmware_dp_low_read(const uint16_t addr)
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const uint8_t res = swd_proc.seq_in(3U);
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uint32_t data = 0;
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swd_proc.seq_in_parity(&data, 32U);
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swd_proc.seq_out(0, 8U);
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return res == SWDP_ACK_OK ? data : 0;
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}
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@@ -426,19 +427,20 @@ uint32_t firmware_swdp_low_access(adiv5_debug_port_s *dp, const uint8_t RnW, con
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DEBUG_ERROR("SWD access resulted in parity error\n");
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raise_exception(EXCEPTION_ERROR, "SWD parity error");
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}
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} else {
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} else
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swd_proc.seq_out_parity(value, 32U);
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/* ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
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* tells to clock the data through SW-DP to either :
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* - immediate start a new transaction
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* - continue to drive idle cycles
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* - or clock at least 8 idle cycles
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*
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* Implement last option to favour correctness over
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* slight speed decrease
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*/
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swd_proc.seq_out(0, 8U);
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}
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/* ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
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* tells to clock the data through SW-DP to either :
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* - immediate start a new transaction
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* - continue to drive idle cycles
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* - or clock at least 8 idle cycles
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*
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* Implement last option to favour correctness over
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* slight speed decrease
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*/
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swd_proc.seq_out(0, 8U);
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return response;
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}
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