User/dev/ekarabulut/fpga env0

src/abr_libs/config/compile.yml

@@ -10,6 +10,8 @@ targets:
       - $COMPILE_ROOT/rtl/abr_sva.svh
       - $COMPILE_ROOT/rtl/abr_macros.svh
       - $COMPILE_ROOT/rtl/abr_1r1w_ram.sv
+      - $COMPILE_ROOT/rtl/abr_1r1w_be_ram.sv
+      - $COMPILE_ROOT/rtl/abr_1r1w_512x4_ram.sv
       - $COMPILE_ROOT/rtl/abr_ram_regout.sv
       - $COMPILE_ROOT/rtl/abr_icg.sv
       - $COMPILE_ROOT/rtl/abr_2ff_sync.sv
@@ -31,6 +33,8 @@ targets:
       - $COMPILE_ROOT/rtl/abr_sva.svh
       - $COMPILE_ROOT/rtl/abr_macros.svh
       - $COMPILE_ROOT/rtl/abr_1r1w_ram.sv
+      - $COMPILE_ROOT/rtl/abr_1r1w_be_ram.sv
+      - $COMPILE_ROOT/rtl/abr_1r1w_512x4_ram.sv
       - $COMPILE_ROOT/rtl/abr_ram_regout.sv
       - $COMPILE_ROOT/rtl/abr_icg.sv
       - $COMPILE_ROOT/rtl/abr_2ff_sync.sv

src/abr_libs/rtl/abr_1r1w_512x4_ram.sv

@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+`include "config_defines.svh"
+
+module abr_1r1w_512x4_ram #(
+     parameter DEPTH      = 512
+    ,parameter DATA_WIDTH = 4
+    ,parameter ADDR_WIDTH = $clog2(DEPTH)
+
+    )
+    (
+    input  logic                       clk_i,
+
+    input  logic                       we_i,
+    input  logic [ADDR_WIDTH-1:0]      waddr_i,
+    input  logic [DATA_WIDTH-1:0]      wdata_i,
+    input  logic                       re_i,
+    input  logic [ADDR_WIDTH-1:0]      raddr_i,
+    output logic [DATA_WIDTH-1:0]      rdata_o
+    );
+
+    //storage element
+`ifndef RV_FPGA_OPTIMIZE
+    logic [DEPTH-1:0][DATA_WIDTH-1:0] ram;
+`else
+    (* ram_style = "block" *) logic [DATA_WIDTH-1:0] ram [DEPTH-1:0];
+`endif
+
+    always @(posedge clk_i) begin
+        if (we_i) begin
+            ram[waddr_i] <= wdata_i;
+        end
+    end
+
+    always @(posedge clk_i) begin
+        if (re_i) begin
+            rdata_o <= ram[raddr_i];
+        end
+    end
+
+endmodule

src/abr_libs/rtl/abr_1r1w_be_ram.sv

@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`include "config_defines.svh"
+module abr_1r1w_be_ram #(
+     parameter DEPTH      = 64
+    ,parameter DATA_WIDTH = 32
+    ,parameter STROBE_WIDTH = 8
+    ,localparam ADDR_WIDTH = $clog2(DEPTH)
+    )
+    (
+    input  logic                           clk_i,
+
+    input  logic                           we_i,
+    input  logic [(DATA_WIDTH/STROBE_WIDTH)-1:0]      wstrobe_i,
+    input  logic [ADDR_WIDTH-1:0]          waddr_i,
+    input  logic [(DATA_WIDTH/STROBE_WIDTH)-1:0][STROBE_WIDTH-1:0] wdata_i,
+    input  logic                           re_i,
+    input  logic [ADDR_WIDTH-1:0]          raddr_i,
+    output logic [DATA_WIDTH-1:0]          rdata_o
+    );
+
+`ifdef RV_FPGA_OPTIMIZE
+
+
+    logic [DATA_WIDTH-1:0] flattened_wdata;
+
+    // Create a flattened version of the wdata_i using always_comb
+    always_comb begin
+        flattened_wdata = '0;  // Initialize to zero
+        for (int i = 0; i < (DATA_WIDTH/STROBE_WIDTH); i++) begin
+            flattened_wdata[i*STROBE_WIDTH +: STROBE_WIDTH] = wdata_i[i];
+        end
+    end
+
+    // Instantiation of the dual-port byte-write RAM
+    bytewrite_tdp_ram_rf #(
+        .NUM_COL(DATA_WIDTH / STROBE_WIDTH),   // Number of columns (bytes)
+        .COL_WIDTH(STROBE_WIDTH),              // Width of each column (byte width)
+        .ADDR_WIDTH(ADDR_WIDTH),               // Address width
+        .DATA_WIDTH(DATA_WIDTH),                // Data width (total)
+        .DEPTH(DEPTH)
+    ) bytewrite_ram_inst (
+        .clkA(clk_i),                          // Clock for Port A (write)
+        .enaA(we_i),                           // Enable for Port A (write enable)
+        .weA(wstrobe_i),                       // Byte-wise write enable for Port A
+        .addrA(waddr_i),                       // Address for Port A (write)
+        .dinA(flattened_wdata),                // Data input for Port A (flattened)
+        .doutA(),                              // Data output for Port A (unused in write-only)
+
+        .clkB(clk_i),                          // Clock for Port B (read)
+        .enaB(re_i),                           // Enable for Port B (read enable)
+        .weB({(DATA_WIDTH/STROBE_WIDTH){1'b0}}),                         // No write enable for Port B
+        .addrB(raddr_i),                       // Address for Port B (read)
+        .dinB({DATA_WIDTH{1'b0}}),             // No data input for Port B
+        .doutB(rdata_o)                        // Data output for Port B (read data)
+    );
+
+`else
+
+    //storage element
+   logic [(DATA_WIDTH/STROBE_WIDTH)-1:0][STROBE_WIDTH-1:0] ram [DEPTH-1:0];
+
+    always @(posedge clk_i) begin
+        if (we_i) begin
+            for (int i = 0; i < (DATA_WIDTH/STROBE_WIDTH); i++) begin
+                if (wstrobe_i[i])
+                    ram[waddr_i][i] <= wdata_i[i];
+            end
+        end
+    end
+
+    always @(posedge clk_i) begin
+        if (re_i) begin
+            rdata_o <= ram[raddr_i];
+        end
+    end
+
+
+`endif
+
+
+endmodule
+
+`ifdef RV_FPGA_OPTIMIZE
+
+module bytewrite_tdp_ram_rf #(
+    parameter NUM_COL   = 4,    // Number of columns (bytes)
+    parameter COL_WIDTH = 8,    // Width of each column (byte)
+    parameter ADDR_WIDTH = 10,  // Address width
+    parameter DATA_WIDTH = NUM_COL * COL_WIDTH,  // Data width (total)
+    parameter DEPTH = 64
+) (
+    input  wire                      clkA,     // Clock for Port A
+    input  wire                      enaA,     // Enable for Port A
+    input  wire [NUM_COL-1:0]        weA,      // Write enable for Port A (byte-wise)
+    input  wire [ADDR_WIDTH-1:0]     addrA,    // Address for Port A
+    input  wire [DATA_WIDTH-1:0]     dinA,     // Data input for Port A
+    output reg  [DATA_WIDTH-1:0]     doutA,    // Data output for Port A
+
+    input  wire                      clkB,     // Clock for Port B
+    input  wire                      enaB,     // Enable for Port B
+    input  wire [NUM_COL-1:0]        weB,      // Write enable for Port B (byte-wise)
+    input  wire [ADDR_WIDTH-1:0]     addrB,    // Address for Port B
+    input  wire [DATA_WIDTH-1:0]     dinB,     // Data input for Port B
+    output reg  [DATA_WIDTH-1:0]     doutB     // Data output for Port B
+);
+
+    // Core memory storage (True Dual Port)
+     (* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram_block [DEPTH-1:0];  // Memory array
+
+    integer i;
+
+    // Port A Operations
+    always @(posedge clkA) begin
+        if (enaA) begin
+            for (i = 0; i < NUM_COL; i = i + 1) begin
+                if (weA[i]) begin
+                    ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];  // Write byte
+                end
+            end
+            doutA <= ram_block[addrA];  // Read operation (read-first)
+        end
+    end
+
+    // Port B Operations
+    always @(posedge clkB) begin
+        if (enaB) begin
+            for (i = 0; i < NUM_COL; i = i + 1) begin
+                if (weB[i]) begin
+                    ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];  // Write byte
+                end
+            end
+            doutB <= ram_block[addrB];  // Read operation (read-first)
+        end
+    end
+
+endmodule
+
+`endif

src/abr_libs/rtl/abr_1r1w_ram.sv

@@ -12,6 +12,8 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+`include "config_defines.svh"
+`ifndef RV_FPGA_OPTIMIZE
 module abr_1r1w_ram #(
      parameter DEPTH      = 64
     ,parameter DATA_WIDTH = 32
@@ -45,3 +47,39 @@ module abr_1r1w_ram #(
     end
 
 endmodule
+
+`else
+module abr_1r1w_ram #(
+     parameter DEPTH      = 64
+    ,parameter DATA_WIDTH = 32
+    ,parameter ADDR_WIDTH = $clog2(DEPTH)
+
+    )
+    (
+    input  logic                       clk_i,
+
+    input  logic                       we_i,
+    input  logic [ADDR_WIDTH-1:0]      waddr_i,
+    input  logic [DATA_WIDTH-1:0]      wdata_i,
+    input  logic                       re_i,
+    input  logic [ADDR_WIDTH-1:0]      raddr_i,
+    output logic [DATA_WIDTH-1:0]      rdata_o
+    );
+
+    (* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
+
+    always @(posedge clk_i) begin
+        if (we_i) begin
+            if (we_i)
+                ram[waddr_i] <= wdata_i;
+        end
+    end
+
+    always @(posedge clk_i) begin
+        if (re_i)
+            rdata_o <= ram[raddr_i];
+    end
+
+endmodule
+
+`endif

src/abr_libs/rtl/abr_piso.sv

@@ -16,29 +16,31 @@
 module abr_piso
   //    import ::*;
   #(
-     parameter PISO_BUFFER_W    = 1344
-    ,parameter PISO_INPUT_RATE  = 1088
-    ,parameter PISO_OUTPUT_RATE = 80
+     parameter PISO_NUM_MODE    = 1
+    ,parameter PISO_BUFFER_W    = 1344
+    ,parameter integer PISO_INPUT_RATE[PISO_NUM_MODE-1:0]  = {1088}
+    ,parameter integer PISO_OUTPUT_RATE[PISO_NUM_MODE-1:0] = {80}
   )
   (
     input logic                          clk,
     input logic                          rst_b,
     input logic                          zeroize,
 
     //input data
-    input  logic                         valid_i,
-    output logic                         hold_o,
-    input  logic [PISO_INPUT_RATE-1:0]   data_i,
+    input  logic [$clog2(PISO_NUM_MODE)-1:0] mode,
+    input  logic                             valid_i,
+    output logic                             hold_o,
+    input  logic [PISO_INPUT_RATE[0]-1:0]    data_i,
 
     //Output data 
-    output logic                         valid_o,
-    input  logic                         hold_i,
-    output logic [PISO_OUTPUT_RATE-1:0]  data_o
+    output logic                             valid_o,
+    input  logic                             hold_i,
+    output logic [PISO_OUTPUT_RATE[0]-1:0]   data_o
 
   );
 
   parameter PISO_PTR_W = $clog2(PISO_BUFFER_W);
-  parameter BUFFER_W_DELTA = PISO_BUFFER_W - PISO_INPUT_RATE;
+  parameter BUFFER_W_DELTA = PISO_BUFFER_W - PISO_INPUT_RATE[0];
 
   logic [PISO_BUFFER_W-1:0] buffer, buffer_d;
   logic [PISO_PTR_W-1:0] buffer_wr_ptr, buffer_wr_ptr_d;
@@ -47,10 +49,10 @@ module abr_piso
   logic update_buffer;
 
   //hold when not enough room for full input data
-  always_comb hold_o = buffer_wr_ptr > (PISO_BUFFER_W - PISO_INPUT_RATE);
+  always_comb hold_o = buffer_wr_ptr > (PISO_BUFFER_W[PISO_PTR_W-1:0] - PISO_INPUT_RATE[mode][PISO_PTR_W-1:0]);
 
-  always_comb data_o = buffer[PISO_OUTPUT_RATE-1:0];
-  always_comb valid_o = buffer_wr_ptr >= PISO_OUTPUT_RATE;
+  always_comb data_o = buffer[PISO_OUTPUT_RATE[0]-1:0];
+  always_comb valid_o = buffer_wr_ptr >= PISO_OUTPUT_RATE[mode][PISO_PTR_W-1:0];
 
   always_comb buffer_wr = valid_i & ~hold_o;
   always_comb buffer_rd = valid_o & ~hold_i;
@@ -74,23 +76,38 @@ module abr_piso
   always_comb begin
     unique case ({buffer_rd, buffer_wr}) 
       2'b00 : buffer_wr_ptr_d = buffer_wr_ptr;
-      2'b01 : buffer_wr_ptr_d = buffer_wr_ptr + PISO_INPUT_RATE;
-      2'b10 : buffer_wr_ptr_d = buffer_wr_ptr - PISO_OUTPUT_RATE;
-      2'b11 : buffer_wr_ptr_d = buffer_wr_ptr + (PISO_INPUT_RATE - PISO_OUTPUT_RATE);
+      2'b01 : buffer_wr_ptr_d = buffer_wr_ptr + PISO_INPUT_RATE[mode][PISO_PTR_W-1:0];
+      2'b10 : buffer_wr_ptr_d = buffer_wr_ptr - PISO_OUTPUT_RATE[mode][PISO_PTR_W-1:0];
+      2'b11 : buffer_wr_ptr_d = buffer_wr_ptr + (PISO_INPUT_RATE[mode][PISO_PTR_W-1:0] - PISO_OUTPUT_RATE[mode][PISO_PTR_W-1:0]);
       default : buffer_wr_ptr_d = buffer_wr_ptr;
     endcase
   end
 
+  logic [PISO_BUFFER_W-1:0] buffer_wdata;
+  logic [PISO_BUFFER_W-1:0] buffer_wdata_mask;
+
+  always_comb begin
+    buffer_wdata = '0;
+    buffer_wdata_mask = '1;
+    for (int i = 0; i < PISO_NUM_MODE; i++) begin
+      if (i == mode) begin
+        buffer_wdata_mask = PISO_BUFFER_W'(buffer_wdata_mask >> (PISO_BUFFER_W[PISO_PTR_W-1:0] - PISO_INPUT_RATE[mode][PISO_PTR_W-1:0]));
+      end
+    end
+    buffer_wdata = {{BUFFER_W_DELTA{1'b0}},data_i} & buffer_wdata_mask;
+  end
+
   //buffer next logic
   always_comb begin
-    unique case ({buffer_rd, buffer_wr}) 
+    unique case ({buffer_rd, buffer_wr})
       2'b00 : buffer_d = buffer;
-      2'b01 : buffer_d = PISO_BUFFER_W'({{BUFFER_W_DELTA{1'b0}},data_i} << buffer_wr_ptr) | buffer;
-      2'b10 : buffer_d = PISO_BUFFER_W'(buffer >> PISO_OUTPUT_RATE);
-      2'b11 : buffer_d = PISO_BUFFER_W'({{BUFFER_W_DELTA{1'b0}},data_i} << (buffer_wr_ptr - PISO_OUTPUT_RATE)) | PISO_BUFFER_W'(buffer >> PISO_OUTPUT_RATE);
+      2'b10 : buffer_d = PISO_BUFFER_W'(buffer >> PISO_OUTPUT_RATE[mode]);
+      2'b01 : buffer_d = PISO_BUFFER_W'(buffer_wdata << buffer_wr_ptr) | buffer;
+      2'b11 : buffer_d = PISO_BUFFER_W'(buffer_wdata << (buffer_wr_ptr - PISO_OUTPUT_RATE[mode][PISO_PTR_W-1:0])) | PISO_BUFFER_W'(buffer >> PISO_OUTPUT_RATE[mode]);
+
       default : buffer_d = buffer;
     endcase
   end
+ // {{PISO_BUFFER_W - PISO_INPUT_RATE[mode]{1'b0}},
 
-
-endmodule
+endmodule

src/abr_prim/rtl/abr_prim_count.sv

@@ -21,6 +21,7 @@
 // unchanged. The counter is also protected against under- and overflows.
 
 `include "abr_prim_assert.sv"
+`timescale 1ns / 1ps
 
 module abr_prim_count #(
   parameter int Width = 2,

src/abr_prim/rtl/abr_prim_intr_hw.sv

@@ -6,7 +6,8 @@
 // controller registers: INTR_ENABLE, INTR_STATE, INTR_TEST.
 // This module can be instantiated once per interrupt field, or
 // "bussified" with all fields of the interrupt vector.
-
+`include "abr_sva.svh"
+`include "abr_prim_assert.sv"
 module abr_prim_intr_hw # (
   parameter int unsigned Width = 1,
   parameter bit FlopOutput = 1,