fixed mult reduction adder

src/ntt_top/config/compile.yml

@@ -49,6 +49,7 @@ targets:
       # - $COMPILE_ROOT/rtl/ntt_add_sub_mod.sv
       # - $COMPILE_ROOT/rtl/ntt_adder.sv
       - $COMPILE_ROOT/rtl/ntt_mult_reduction.sv
+      - $COMPILE_ROOT/rtl/ntt_special_adder.sv
       - $COMPILE_ROOT/rtl/ntt_div2.sv
       - $COMPILE_ROOT/rtl/ntt_buffer.sv
       - $COMPILE_ROOT/rtl/ntt_twiddle_lookup.sv
@@ -82,6 +83,18 @@ targets:
   sim:
     pre_exec: 'echo "[PRE-EXEC] Copying ntt hex to $PWD" && cp $COMPILE_ROOT/tb/test_vectors/zeta.txt . && cp $COMPILE_ROOT/tb/test_vectors/zeta_inv.hex . && cp $COMPILE_ROOT/tb/test_vectors/ntt_stage0_mem.hex . && cp $COMPILE_ROOT/tb/test_vectors/rand_ntt_stage0_mem.hex . && cp $COMPILE_ROOT/tb/test_vectors/ntt_stage0_out.hex . && cp $COMPILE_ROOT/tb/test_vectors/ntt_stage67.hex . && cp $COMPILE_ROOT/tb/test_vectors/pwm_iter1.hex . && cp $COMPILE_ROOT/tb/test_vectors/pwm_iter2.hex .'
 
+---
+provides: [ntt_mult_reduction_tb]  
+schema_version: 2.4.0
+requires: 
+  - ntt_top
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/tb]
+    files:
+      - $COMPILE_ROOT/tb/ntt_mult_reduction_tb.sv
+    tops: [ntt_mult_reduction_tb]
+
 ---
 provides: [ntt_utb]  
 schema_version: 2.4.0

src/ntt_top/rtl/ntt_mult_reduction.sv

@@ -43,8 +43,7 @@ module ntt_mult_reduction #(
     logic [10:0] d;
     logic [REG_SIZE-1:0] e;
     logic [13:0] f;
-    logic [REG_SIZE:0] g;
-    logic [REG_SIZE:0] g_reduced;
+    logic [REG_SIZE-1:0] g_reduced;
     logic [REG_SIZE-1:0] res;
     logic ready;
     logic ready_e, ready_g_reduced;
@@ -93,25 +92,19 @@ module ntt_mult_reduction #(
         .res_o(e),
         .ready_o() //(ready_e)
     );
-
-
-    //Calculate g, g_reduced, g_reduced_f
-    //--------------------
-    always_comb g = (REG_SIZE+1)'(d[10:0] << 'd13);
 
     //Mod add
-    abr_add_sub_mod #(
-        .REG_SIZE(REG_SIZE+1)
+    ntt_special_adder #(
+        .REG_SIZE(REG_SIZE)
         )
         mod_add_inst_1(
         .clk(clk),
         .reset_n(reset_n),
         .zeroize(zeroize),
         .add_en_i(1'b1), //(enable_reg),
-        .sub_i(1'b0),
-        .opa_i(g),
-        .opb_i({{REG_SIZE-12{1'b0}},z_f[12:0]}), //24 bit input
-        .prime_i({1'b0,PRIME}),
+        .opa_i(d[10:0]),
+        .opb_i(z_f[12:0]), //24 bit input
+        .prime_i(PRIME),
         .res_o(g_reduced),
         .ready_o() //(ready_g_reduced)
     );
@@ -128,7 +121,7 @@ module ntt_mult_reduction #(
         .zeroize(zeroize),
         .add_en_i(1'b1), //(ready_e && ready_g_reduced),
         .sub_i(1'b1),
-        .opa_i(g_reduced[REG_SIZE-1:0]),
+        .opa_i(g_reduced),
         .opb_i(e[22:0]),
         .prime_i(PRIME),
         .res_o(res),

src/ntt_top/rtl/ntt_special_adder.sv

@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+//
+// ntt_special_adder.sv
+// --------
+// Special modular addtion module to compute opa+-opb % prime 
+// to be used special multreduction module
+//
+//
+//======================================================================
+
+module ntt_special_adder #(
+    parameter REG_SIZE      = 24
+    )
+    (
+    // Clock and reset.
+    input wire           clk,
+    input wire           reset_n,
+    input wire           zeroize,
+
+    // DATA PORT
+    input  wire                 add_en_i,
+    input  wire  [10:0]         opa_i,
+    input  wire  [12:0]         opb_i,
+    input  wire  [REG_SIZE-1:0] prime_i,
+    output logic [REG_SIZE-1:0] res_o,
+    output logic                ready_o
+);
+
+    logic [REG_SIZE-1 : 0] opb1;
+    logic [REG_SIZE-1 : 0] r0;
+    logic [REG_SIZE-1 : 0] r1;
+    logic                  carry0; 
+
+    logic [REG_SIZE-1 : 0] r0_reg;
+    logic                  carry0_reg;
+
+    logic                  carry1;
+    logic [1 : 0]          push_result_reg;
+
+
+    always_comb {carry0, r0} = {opa_i, opb_i};
+    always_comb opb1 = ~prime_i;
+
+    abr_adder #(
+        .RADIX(REG_SIZE)
+        ) 
+        adder_inst_1(
+        .a_i(r0_reg),
+        .b_i(opb1),
+        .cin_i(1'b1),
+        .s_o(r1),
+        .cout_o(carry1)
+    );
+
+    always_ff @(posedge clk or negedge reset_n) 
+    begin
+        if(!reset_n) begin
+            r0_reg <= '0;
+            carry0_reg <= '0;
+        end
+        else if (zeroize) begin
+            r0_reg <= '0;
+            carry0_reg <= '0;
+        end
+        else if (add_en_i) begin 
+            r0_reg <= r0;
+            carry0_reg <= carry0;
+        end
+    end
+
+    // Determines when results are ready
+    always_ff @(posedge clk or negedge reset_n) begin
+        if (!reset_n)
+            push_result_reg <= 2'b0;
+        else if (zeroize)
+            push_result_reg <= 2'b0;
+        else if (add_en_i)
+            push_result_reg <= 2'b10;
+        else // one shift to right
+            push_result_reg <= 2'(push_result_reg >> 1);
+    end
+
+    assign ready_o = push_result_reg[0];
+
+    assign res_o = (carry0_reg ^ carry1)? r1 : r0_reg;
+
+endmodule

src/ntt_top/tb/ntt_mult_reduction_tb.sv

@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+//
+// ntt_mult_reduction_tb.sv
+// --------
+//
+//
+//======================================================================
+
+module ntt_mult_reduction_tb 
+    #(
+    parameter   PRIME     = 23'd8380417,
+    parameter   REG_SIZE  = 23,
+    parameter   numOfTest = 1000
+    )
+();
+
+
+parameter CLK_HALF_PERIOD = 5;
+parameter CLK_PERIOD      = 2 * CLK_HALF_PERIOD;
+
+reg [31 : 0]  cycle_ctr;
+reg [31 : 0]  error_ctr;
+reg [31 : 0]  tc_ctr;
+
+reg           clk_tb;
+reg           reset_n_tb;
+reg           zeroize_tb;
+reg [(2*REG_SIZE)-1:0]  opa_i_tb;
+reg [REG_SIZE-1:0]      res_o_tb;
+reg           bf_ready_tb;
+
+logic [REG_SIZE-1:0] a;
+logic [REG_SIZE-1:0] b;
+logic [REG_SIZE-1:0] expected;
+
+ntt_mult_reduction #(
+    .REG_SIZE(REG_SIZE),
+    .PRIME(PRIME) 
+)
+dut (
+    .clk(clk_tb),
+    .reset_n(reset_n_tb),
+    .zeroize(zeroize_tb),
+    .opa_i(opa_i_tb),
+    .res_o(res_o_tb),
+    .ready_o(ready_o_tb)
+);
+
+//----------------------------------------------------------------
+// clk_gen
+//
+// Always running clock generator process.
+//----------------------------------------------------------------
+always
+begin : clk_gen
+  #CLK_HALF_PERIOD;
+  clk_tb = !clk_tb;
+end // clk_gen
+
+//----------------------------------------------------------------
+// sys_monitor()
+//
+// An always running process that creates a cycle counter and
+// conditionally displays information about the DUT.
+//----------------------------------------------------------------
+always
+begin : sys_monitor
+  #(CLK_PERIOD);
+  cycle_ctr = cycle_ctr + 1;
+end
+
+//----------------------------------------------------------------
+// reset_dut()
+//
+// Toggle reset to put the DUT into a well known state.
+//----------------------------------------------------------------
+task reset_dut;
+    begin
+      $display("*** Toggle reset.");
+      reset_n_tb = 0;
+
+      #(2 * CLK_PERIOD);
+      reset_n_tb = 1;
+    end
+endtask // reset_dut
+
+  //----------------------------------------------------------------
+  // display_test_result()
+  //
+  // Display the accumulated test results.
+  //----------------------------------------------------------------
+  task display_test_result;
+    begin
+      if (error_ctr == 0)
+        begin
+          $display("*** All %02d test cases completed successfully.", tc_ctr);
+          $display("* TESTCASE PASSED");
+        end
+      else
+        begin
+          $display("*** %02d test cases completed.", tc_ctr);
+          $display("*** %02d errors detected during testing.", error_ctr);
+          $display("* TESTCASE FAILED");
+        end
+    end
+  endtask // display_test_result
+
+
+//----------------------------------------------------------------
+// init_sim()
+//
+// Initialize all counters and testbed functionality as well
+// as setting the DUT inputs to defined values.
+//----------------------------------------------------------------
+task init_sim;
+    begin
+        $display("Start of init\n");
+        cycle_ctr = 32'h00000000;
+        error_ctr = 32'h00000000;
+        tc_ctr    = 32'h00000000;
+
+        clk_tb        = 0;
+        reset_n_tb    = 0;
+    end
+endtask
+
+//----------------------------------------------------------------
+// ntt_mult_test()
+//
+// Toggle reset to put the DUT into a well known state.
+//----------------------------------------------------------------
+task ntt_mult_test(input [REG_SIZE-1 : 0] op_a, 
+                   input [REG_SIZE-1 : 0] op_b);
+    begin
+
+      $display("*** ntt_mult_test.");
+      #(CLK_PERIOD);
+
+      opa_i_tb = a * b;
+      #(CLK_PERIOD);
+
+      expected = opa_i_tb % PRIME;
+      #(5 * CLK_PERIOD);
+
+      if (res_o_tb == expected)
+        $display("*** successful");
+      else begin
+        $display("*** failed");
+        $display("TC%01d: Expected: 0x%06x", tc_ctr, expected);
+        $display("TC%01d: Got:      0x%06x", tc_ctr, res_o_tb);
+        error_ctr = error_ctr + 1;
+      end
+
+      tc_ctr = tc_ctr + 1;
+      #(2 * CLK_PERIOD);
+    end
+endtask // ntt_mult_test
+
+
+initial begin
+    init_sim();
+    reset_dut();
+
+    @(posedge clk_tb);
+
+    $display("Starting ntt_mult reduction test\n");
+
+    a = 30;
+    b = 40;
+    ntt_mult_test(a, b);
+
+    a = 3054463;
+    b = 809589;
+    ntt_mult_test(a, b);
+
+    a = 3082050;
+    b = 5637242;
+    ntt_mult_test(a, b);
+
+    for (int i = 0; i < numOfTest; i++) begin
+        a = $urandom_range(0, PRIME - 1);
+        b = $urandom_range(0, PRIME - 1);
+        ntt_mult_test(a, b);
+    end
+
+    display_test_result();
+
+    repeat(10) @(posedge clk_tb);
+    $display("   -- Testbench for ntt_mult reduction done. --");
+    $finish;
+end
+
+endmodule