Updated hw/latest/rtl to cdb1034c85dff2aba879be0019c20ccd84122395

chipsalliance · Feb 19, 2025 · a28e2e3 · a28e2e3
1 parent c402172
commit a28e2e3
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Showing 23 changed files with 62 additions and 40 deletions.
diff --git a/hw/latest/registers/src/aes.rs b/hw/latest/registers/src/aes.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/aes_clp.rs b/hw/latest/registers/src/aes_clp.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -13,7 +13,7 @@ pub struct AesClpReg {
     _priv: (),
 }
 impl AesClpReg {
-    pub const PTR: *mut u32 = 0x10011100 as *mut u32;
+    pub const PTR: *mut u32 = 0x10011800 as *mut u32;
     /// # Safety
     ///
     /// Caller must ensure that all concurrent use of this
@@ -81,7 +81,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     pub fn aes_name(&self) -> ureg::Array<2, ureg::RegRef<crate::aes_clp::meta::AesName, &TMmio>> {
         unsafe {
             ureg::Array::new_with_mmio(
-                self.ptr.wrapping_add(0x100 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -96,7 +96,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     ) -> ureg::Array<2, ureg::RegRef<crate::aes_clp::meta::AesVersion, &TMmio>> {
         unsafe {
             ureg::Array::new_with_mmio(
-                self.ptr.wrapping_add(0x108 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(8 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -108,7 +108,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     pub fn aes_kv_rd_key_ctrl(&self) -> ureg::RegRef<crate::aes_clp::meta::AesKvRdKeyCtrl, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
-                self.ptr.wrapping_add(0x600 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x200 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -122,15 +122,15 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     ) -> ureg::RegRef<crate::aes_clp::meta::AesKvRdKeyStatus, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
-                self.ptr.wrapping_add(0x604 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x204 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
     }
     #[inline(always)]
     pub fn intr_block_rf(&self) -> IntrBlockRfBlock<&TMmio> {
         IntrBlockRfBlock {
-            ptr: unsafe { self.ptr.add(0x800 / core::mem::size_of::<u32>()) },
+            ptr: unsafe { self.ptr.add(0x400 / core::mem::size_of::<u32>()) },
             mmio: core::borrow::Borrow::borrow(&self.mmio),
         }
     }
@@ -488,7 +488,7 @@ pub struct IntrBlockRf {
     _priv: (),
 }
 impl IntrBlockRf {
-    pub const PTR: *mut u32 = 0x800 as *mut u32;
+    pub const PTR: *mut u32 = 0x400 as *mut u32;
     /// # Safety
     ///
     /// Caller must ensure that all concurrent use of this

diff --git a/hw/latest/registers/src/axi_dma.rs b/hw/latest/registers/src/axi_dma.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/csrng.rs b/hw/latest/registers/src/csrng.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/doe.rs b/hw/latest/registers/src/doe.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/dv.rs b/hw/latest/registers/src/dv.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/ecc.rs b/hw/latest/registers/src/ecc.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/el2_pic_ctrl.rs b/hw/latest/registers/src/el2_pic_ctrl.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/entropy_src.rs b/hw/latest/registers/src/entropy_src.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/hmac.rs b/hw/latest/registers/src/hmac.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/i3ccsr.rs b/hw/latest/registers/src/i3ccsr.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/kv.rs b/hw/latest/registers/src/kv.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/lib.rs b/hw/latest/registers/src/lib.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![no_std]
 #![allow(clippy::erasing_op)]

diff --git a/hw/latest/registers/src/mbox.rs b/hw/latest/registers/src/mbox.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/mbox_sram.rs b/hw/latest/registers/src/mbox_sram.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/mldsa.rs b/hw/latest/registers/src/mldsa.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -100,14 +100,6 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
         }
     }
     /// Control register to set the type of MLDSA operations.
-    /// [br] bit #[1:0]: This can be:
-    /// [br]            000 for NONE
-    /// [br]            001 for KEYGEN
-    /// [br]            010 for SIGNING
-    /// [br]            011 for VERIFYING
-    /// [br]            100 for KEYGEN+SIGN
-    ///
-    /// [br] bit #3: Zeroize all internal registers after MLDSA process, to avoid SCA leakage.
     ///
     /// Read value: [`mldsa::regs::CtrlReadVal`]; Write value: [`mldsa::regs::CtrlWriteVal`]
     #[inline(always)]
@@ -205,6 +197,21 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    /// 16 32-bit registers storing the external_mu in big-endian representation.
+    /// The external_mu can be any 512-bit value in [0 : 2^512-1].
+    ///
+    /// Read value: [`u32`]; Write value: [`u32`]
+    #[inline(always)]
+    pub fn external_mu(
+        &self,
+    ) -> ureg::Array<16, ureg::RegRef<crate::mldsa::meta::ExternalMu, &TMmio>> {
+        unsafe {
+            ureg::Array::new_with_mmio(
+                self.ptr.wrapping_add(0x118 / core::mem::size_of::<u32>()),
+                core::borrow::Borrow::borrow(&self.mmio),
+            )
+        }
+    }
     /// 648 32-bit registers storing the public key in big-endian representation.
     /// These registers are read by MLDSA user after keygen operation,
     /// or set before verifying operation.
@@ -574,15 +581,24 @@ pub mod regs {
     #[derive(Clone, Copy)]
     pub struct CtrlWriteVal(u32);
     impl CtrlWriteVal {
-        /// Control command field
+        /// Control command field. This can be:
+        /// [br]            000 for NONE
+        /// [br]            001 for KEYGEN
+        /// [br]            010 for SIGNING
+        /// [br]            011 for VERIFYING
+        /// [br]            100 for KEYGEN+SIGN
+        ///                
+        /// [br] After each software write, hardware will erase the register
         #[inline(always)]
         pub fn ctrl(
             self,
             f: impl FnOnce(super::enums::selector::CtrlSelector) -> super::enums::Ctrl,
         ) -> Self {
             Self((self.0 & !(7 << 0)) | (u32::from(f(super::enums::selector::CtrlSelector())) << 0))
         }
-        /// Zeroize all internal registers
+        /// Zeroize all internal registers: Zeroize all internal registers and memories to avoid SCA leakage.
+        /// [br] Software write generates only a single-cycle pulse on the
+        /// hardware interface and then will be erased
         #[inline(always)]
         pub fn zeroize(self, val: bool) -> Self {
             Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
@@ -592,6 +608,11 @@ pub mod regs {
         pub fn pcr_sign(self, val: bool) -> Self {
             Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
         }
+        /// ExternalMu Mode
+        #[inline(always)]
+        pub fn external_mu(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        }
     }
     impl From<u32> for CtrlWriteVal {
         #[inline(always)]
@@ -1308,6 +1329,7 @@ pub mod meta {
     pub type SignRnd = ureg::WriteOnlyReg32<0, u32>;
     pub type Msg = ureg::WriteOnlyReg32<0, u32>;
     pub type VerifyRes = ureg::ReadOnlyReg32<u32>;
+    pub type ExternalMu = ureg::WriteOnlyReg32<0, u32>;
     pub type Pubkey = ureg::ReadWriteReg32<0, u32, u32>;
     pub type Signature = ureg::ReadWriteReg32<0, u32, u32>;
     pub type PrivkeyOut = ureg::ReadOnlyReg32<u32>;

diff --git a/hw/latest/registers/src/pv.rs b/hw/latest/registers/src/pv.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/sha256.rs b/hw/latest/registers/src/sha256.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/sha512.rs b/hw/latest/registers/src/sha512.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/sha512_acc.rs b/hw/latest/registers/src/sha512_acc.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/soc_ifc.rs b/hw/latest/registers/src/soc_ifc.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/registers/src/soc_ifc_trng.rs b/hw/latest/registers/src/soc_ifc_trng.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at cdb1034c85dff2aba879be0019c20ccd84122395
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

diff --git a/hw/latest/rtl b/hw/latest/rtl